git.sur5r.net Git - freertos/blob - FreeRTOS/Source/portable/GCC/ARM_CM33/non_secure/portasm.c

   1 /*\r
   2  * FreeRTOS Kernel V10.2.1\r
   3  * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\r
   4  *\r
   5  * Permission is hereby granted, free of charge, to any person obtaining a copy of\r
   6  * this software and associated documentation files (the "Software"), to deal in\r
   7  * the Software without restriction, including without limitation the rights to\r
   8  * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\r
   9  * the Software, and to permit persons to whom the Software is furnished to do so,\r
  10  * subject to the following conditions:\r
  11  *\r
  12  * The above copyright notice and this permission notice shall be included in all\r
  13  * copies or substantial portions of the Software.\r
  14  *\r
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\r
  17  * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\r
  18  * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r
  19  * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
  20  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
  21  *\r
  22  * http://www.FreeRTOS.org\r
  23  * http://aws.amazon.com/freertos\r
  24  *\r
  25  * 1 tab == 4 spaces!\r
  26  */\r
  27 \r
  28 /* Standard includes. */\r
  29 #include <stdint.h>\r
  30 \r
  31 /* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE ensures that PRIVILEGED_FUNCTION\r
  32  * is defined correctly and privileged functions are placed in correct sections. */\r
  33 #define MPU_WRAPPERS_INCLUDED_FROM_API_FILE\r
  34 \r
  35 /* Portasm includes. */\r
  36 #include "portasm.h"\r
  37 \r
  38 /* MPU_WRAPPERS_INCLUDED_FROM_API_FILE is needed to be defined only for the\r
  39  * header files. */\r
  40 #undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE\r
  41 \r
  42 void vRestoreContextOfFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */\r
  43 {\r
  44         __asm volatile\r
  45         (\r
  46         "       .syntax unified                                                                 \n"\r
  47         "                                                                                                       \n"\r
  48         "       ldr  r2, pxCurrentTCBConst2                                             \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\r
  49         "       ldr  r3, [r2]                                                                   \n" /* Read pxCurrentTCB. */\r
  50         "       ldr  r0, [r3]                                                                   \n" /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */\r
  51         "                                                                                                       \n"\r
  52         #if( configENABLE_MPU == 1 )\r
  53         "       dmb                                                                                             \n" /* Complete outstanding transfers before disabling MPU. */\r
  54         "       ldr r2, xMPUCTRLConst2                                                  \n" /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */\r
  55         "       ldr r4, [r2]                                                                    \n" /* Read the value of MPU_CTRL. */\r
  56         "       bic r4, #1                                                                              \n" /* r4 = r4 & ~1 i.e. Clear the bit 0 in r4. */\r
  57         "       str r4, [r2]                                                                    \n" /* Disable MPU. */\r
  58         "                                                                                                       \n"\r
  59         "       adds r3, #4                                                                             \n" /* r3 = r3 + 4. r3 now points to MAIR0 in TCB. */\r
  60         "       ldr  r4, [r3]                                                                   \n" /* r4 = *r3 i.e. r4 = MAIR0. */\r
  61         "       ldr  r2, xMAIR0Const2                                                   \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */\r
  62         "       str  r4, [r2]                                                                   \n" /* Program MAIR0. */\r
  63         "       ldr  r2, xRNRConst2                                                             \n" /* r2 = 0xe000ed98 [Location of RNR]. */\r
  64         "       movs r4, #4                                                                             \n" /* r4 = 4. */\r
  65         "       str  r4, [r2]                                                                   \n" /* Program RNR = 4. */\r
  66         "       adds r3, #4                                                                             \n" /* r3 = r3 + 4. r3 now points to first RBAR in TCB. */\r
  67         "       ldr  r2, xRBARConst2                                                    \n" /* r2 = 0xe000ed9c [Location of RBAR]. */\r
  68         "       ldmia r3!, {r4-r11}                                                             \n" /* Read 4 set of RBAR/RLAR registers from TCB. */\r
  69         "       stmia r2!, {r4-r11}                                                             \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */\r
  70         "                                                                                                       \n"\r
  71         "       ldr r2, xMPUCTRLConst2                                                  \n" /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */\r
  72         "       ldr r4, [r2]                                                                    \n" /* Read the value of MPU_CTRL. */\r
  73         "       orr r4, #1                                                                              \n" /* r4 = r4 | 1 i.e. Set the bit 0 in r4. */\r
  74         "       str r4, [r2]                                                                    \n" /* Enable MPU. */\r
  75         "       dsb                                                                                             \n" /* Force memory writes before continuing. */\r
  76         #endif /* configENABLE_MPU */\r
  77         "                                                                                                       \n"\r
  78         #if( configENABLE_MPU == 1 )\r
  79         "       ldm  r0!, {r1-r4}                                                               \n" /* Read from stack - r1 = xSecureContext, r2 = PSPLIM, r3 = CONTROL and r4 = EXC_RETURN. */\r
  80         "       ldr  r5, xSecureContextConst2                                   \n"\r
  81         "       str  r1, [r5]                                                                   \n" /* Set xSecureContext to this task's value for the same. */\r
  82         "       msr  psplim, r2                                                                 \n" /* Set this task's PSPLIM value. */\r
  83         "       msr  control, r3                                                                \n" /* Set this task's CONTROL value. */\r
  84         "       adds r0, #32                                                                    \n" /* Discard everything up to r0. */\r
  85         "       msr  psp, r0                                                                    \n" /* This is now the new top of stack to use in the task. */\r
  86         "       isb                                                                                             \n"\r
  87         "       bx   r4                                                                                 \n" /* Finally, branch to EXC_RETURN. */\r
  88         #else /* configENABLE_MPU */\r
  89         "       ldm  r0!, {r1-r3}                                                               \n" /* Read from stack - r1 = xSecureContext, r2 = PSPLIM and r3 = EXC_RETURN. */\r
  90         "       ldr  r4, xSecureContextConst2                                   \n"\r
  91         "       str  r1, [r4]                                                                   \n" /* Set xSecureContext to this task's value for the same. */\r
  92         "       msr  psplim, r2                                                                 \n" /* Set this task's PSPLIM value. */\r
  93         "       movs r1, #2                                                                             \n" /* r1 = 2. */\r
  94         "       msr  CONTROL, r1                                                                \n" /* Switch to use PSP in the thread mode. */\r
  95         "       adds r0, #32                                                                    \n" /* Discard everything up to r0. */\r
  96         "       msr  psp, r0                                                                    \n" /* This is now the new top of stack to use in the task. */\r
  97         "       isb                                                                                             \n"\r
  98         "       bx   r3                                                                                 \n" /* Finally, branch to EXC_RETURN. */\r
  99         #endif /* configENABLE_MPU */\r
 100         "                                                                                                       \n"\r
 101         "       .align 4                                                                                \n"\r
 102         "pxCurrentTCBConst2: .word pxCurrentTCB                         \n"\r
 103         "xSecureContextConst2: .word xSecureContext                     \n"\r
 104         #if( configENABLE_MPU == 1 )\r
 105         "xMPUCTRLConst2: .word 0xe000ed94                                       \n"\r
 106         "xMAIR0Const2: .word 0xe000edc0                                         \n"\r
 107         "xRNRConst2: .word 0xe000ed98                                           \n"\r
 108         "xRBARConst2: .word 0xe000ed9c                                          \n"\r
 109         #endif /* configENABLE_MPU */\r
 110         );\r
 111 }\r
 112 /*-----------------------------------------------------------*/\r
 113 \r
 114 BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */\r
 115 {\r
 116         __asm volatile\r
 117         (\r
 118         "       mrs r0, control                                                                 \n" /* r0 = CONTROL. */\r
 119         "       tst r0, #1                                                                              \n" /* Perform r0 & 1 (bitwise AND) and update the conditions flag. */\r
 120         "       ite ne                                                                                  \n"\r
 121         "       movne r0, #0                                                                    \n" /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */\r
 122         "       moveq r0, #1                                                                    \n" /* CONTROL[0]==0. Return true to indicate that the processor is privileged. */\r
 123         "       bx lr                                                                                   \n" /* Return. */\r
 124         "                                                                                                       \n"\r
 125         "       .align 4                                                                                \n"\r
 126         ::: "r0", "memory"\r
 127         );\r
 128 }\r
 129 /*-----------------------------------------------------------*/\r
 130 \r
 131 void vRaisePrivilege( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */\r
 132 {\r
 133          __asm volatile\r
 134         (\r
 135         "       mrs r0, control                                                                 \n" /* Read the CONTROL register. */\r
 136         "       bic r0, #1                                                                              \n" /* Clear the bit 0. */\r
 137         "       msr control, r0                                                                 \n" /* Write back the new CONTROL value. */\r
 138         "       bx lr                                                                                   \n" /* Return to the caller. */\r
 139         ::: "r0", "memory"\r
 140         );\r
 141 }\r
 142 /*-----------------------------------------------------------*/\r
 143 \r
 144 void vResetPrivilege( void ) /* __attribute__ (( naked )) */\r
 145 {\r
 146         __asm volatile\r
 147         (\r
 148         "       mrs r0, control                                                                 \n" /* r0 = CONTROL. */\r
 149         "       orr r0, #1                                                                              \n" /* r0 = r0 | 1. */\r
 150         "       msr control, r0                                                                 \n" /* CONTROL = r0. */\r
 151         "       bx lr                                                                                   \n" /* Return to the caller. */\r
 152         :::"r0", "memory"\r
 153         );\r
 154 }\r
 155 /*-----------------------------------------------------------*/\r
 156 \r
 157 void vStartFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */\r
 158 {\r
 159         __asm volatile\r
 160         (\r
 161         "       ldr r0, xVTORConst                                                              \n" /* Use the NVIC offset register to locate the stack. */\r
 162         "       ldr r0, [r0]                                                                    \n" /* Read the VTOR register which gives the address of vector table. */\r
 163         "       ldr r0, [r0]                                                                    \n" /* The first entry in vector table is stack pointer. */\r
 164         "       msr msp, r0                                                                             \n" /* Set the MSP back to the start of the stack. */\r
 165         "       cpsie i                                                                                 \n" /* Globally enable interrupts. */\r
 166         "       cpsie f                                                                                 \n"\r
 167         "       dsb                                                                                             \n"\r
 168         "       isb                                                                                             \n"\r
 169         "       svc %0                                                                                  \n" /* System call to start the first task. */\r
 170         "       nop                                                                                             \n"\r
 171         "                                                                                                       \n"\r
 172         "   .align 4                                                                            \n"\r
 173         "xVTORConst: .word 0xe000ed08                                           \n"\r
 174         :: "i" ( portSVC_START_SCHEDULER ) : "memory"\r
 175         );\r
 176 }\r
 177 /*-----------------------------------------------------------*/\r
 178 \r
 179 uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */\r
 180 {\r
 181         __asm volatile\r
 182         (\r
 183         "       mrs r0, basepri                                                                 \n" /* r0 = basepri. Return original basepri value. */\r
 184         "       mov r1, %0                                                                              \n" /* r1 = configMAX_SYSCALL_INTERRUPT_PRIORITY. */\r
 185         "       msr basepri, r1                                                                 \n" /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */\r
 186         "       dsb                                                                                             \n"\r
 187         "       isb                                                                                             \n"\r
 188         "       bx lr                                                                                   \n" /* Return. */\r
 189         :: "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory"\r
 190         );\r
 191 }\r
 192 /*-----------------------------------------------------------*/\r
 193 \r
 194 void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */\r
 195 {\r
 196         __asm volatile\r
 197         (\r
 198         "       msr basepri, r0                                                                 \n" /* basepri = ulMask. */\r
 199         "       dsb                                                                                             \n"\r
 200         "       isb                                                                                             \n"\r
 201         "       bx lr                                                                                   \n" /* Return. */\r
 202         ::: "memory"\r
 203         );\r
 204 }\r
 205 /*-----------------------------------------------------------*/\r
 206 \r
 207 void PendSV_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */\r
 208 {\r
 209         __asm volatile\r
 210         (\r
 211         "       .syntax unified                                                                 \n"\r
 212         "       .extern SecureContext_SaveContext                               \n"\r
 213         "       .extern SecureContext_LoadContext                               \n"\r
 214         "                                                                                                       \n"\r
 215         "       mrs r1, psp                                                                             \n" /* Read PSP in r1. */\r
 216         "       ldr r2, xSecureContextConst                                             \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */\r
 217         "       ldr r0, [r2]                                                                    \n" /* Read xSecureContext - Value of xSecureContext must be in r0 as it is used as a parameter later. */\r
 218         "                                                                                                       \n"\r
 219         "       cbz r0, save_ns_context                                                 \n" /* No secure context to save. */\r
 220         "       push {r0-r2, r14}                                                               \n"\r
 221         "       bl SecureContext_SaveContext                                    \n"\r
 222         "       pop {r0-r3}                                                                             \n" /* LR is now in r3. */\r
 223         "       mov lr, r3                                                                              \n" /* LR = r3. */\r
 224         "       lsls r2, r3, #25                                                                \n" /* r2 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */\r
 225         "       bpl save_ns_context                                                             \n" /* bpl - branch if positive or zero. If r2 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */\r
 226         "       ldr r3, pxCurrentTCBConst                                               \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\r
 227         "       ldr r2, [r3]                                                                    \n" /* Read pxCurrentTCB. */\r
 228         #if( configENABLE_MPU == 1 )\r
 229         "       subs r1, r1, #16                                                                \n" /* Make space for xSecureContext, PSPLIM, CONTROL and LR on the stack. */\r
 230         "       str r1, [r2]                                                                    \n" /* Save the new top of stack in TCB. */\r
 231         "       mrs r2, psplim                                                                  \n" /* r2 = PSPLIM. */\r
 232         "       mrs r3, control                                                                 \n" /* r3 = CONTROL. */\r
 233         "       mov r4, lr                                                                              \n" /* r4 = LR/EXC_RETURN. */\r
 234         "       stmia r1!, {r0, r2-r4}                                                  \n" /* Store xSecureContext, PSPLIM, CONTROL and LR on the stack. */\r
 235         #else /* configENABLE_MPU */\r
 236         "       subs r1, r1, #12                                                                \n" /* Make space for xSecureContext, PSPLIM and LR on the stack. */\r
 237         "       str r1, [r2]                                                                    \n" /* Save the new top of stack in TCB. */\r
 238         "       mrs r2, psplim                                                                  \n" /* r2 = PSPLIM. */\r
 239         "       mov r3, lr                                                                              \n" /* r3 = LR/EXC_RETURN. */\r
 240         "       stmia r1!, {r0, r2-r3}                                                  \n" /* Store xSecureContext, PSPLIM and LR on the stack. */\r
 241         #endif /* configENABLE_MPU */\r
 242         "       b select_next_task                                                              \n"\r
 243         "                                                                                                       \n"\r
 244         " save_ns_context:                                                                      \n"\r
 245         "       ldr r3, pxCurrentTCBConst                                               \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\r
 246         "       ldr r2, [r3]                                                                    \n" /* Read pxCurrentTCB. */\r
 247         #if( configENABLE_FPU == 1 )\r
 248         "       tst lr, #0x10                                                                   \n" /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the FPU is in use. */\r
 249         "       it eq                                                                                   \n"\r
 250         "       vstmdbeq r1!, {s16-s31}                                                 \n" /* Store the FPU registers which are not saved automatically. */\r
 251         #endif /* configENABLE_FPU */\r
 252         #if( configENABLE_MPU == 1 )\r
 253         "       subs r1, r1, #48                                                                \n" /* Make space for xSecureContext, PSPLIM, CONTROL, LR and the remaining registers on the stack. */\r
 254         "       str r1, [r2]                                                                    \n" /* Save the new top of stack in TCB. */\r
 255         "       adds r1, r1, #16                                                                \n" /* r1 = r1 + 16. */\r
 256         "       stm r1, {r4-r11}                                                                \n" /* Store the registers that are not saved automatically. */\r
 257         "       mrs r2, psplim                                                                  \n" /* r2 = PSPLIM. */\r
 258         "       mrs r3, control                                                                 \n" /* r3 = CONTROL. */\r
 259         "       mov r4, lr                                                                              \n" /* r4 = LR/EXC_RETURN. */\r
 260         "       subs r1, r1, #16                                                                \n" /* r1 = r1 - 16. */\r
 261         "       stm r1, {r0, r2-r4}                                                             \n" /* Store xSecureContext, PSPLIM, CONTROL and LR on the stack. */\r
 262         #else /* configENABLE_MPU */\r
 263         "       subs r1, r1, #44                                                                \n" /* Make space for xSecureContext, PSPLIM, LR and the remaining registers on the stack. */\r
 264         "       str r1, [r2]                                                                    \n" /* Save the new top of stack in TCB. */\r
 265         "       adds r1, r1, #12                                                                \n" /* r1 = r1 + 12. */\r
 266         "       stm r1, {r4-r11}                                                                \n" /* Store the registers that are not saved automatically. */\r
 267         "       mrs r2, psplim                                                                  \n" /* r2 = PSPLIM. */\r
 268         "       mov r3, lr                                                                              \n" /* r3 = LR/EXC_RETURN. */\r
 269         "       subs r1, r1, #12                                                                \n" /* r1 = r1 - 12. */\r
 270         "       stmia r1!, {r0, r2-r3}                                                  \n" /* Store xSecureContext, PSPLIM and LR on the stack. */\r
 271         #endif /* configENABLE_MPU */\r
 272         "                                                                                                       \n"\r
 273         " select_next_task:                                                                     \n"\r
 274         "       mov r0, %0                                                                              \n" /* r0 = configMAX_SYSCALL_INTERRUPT_PRIORITY */\r
 275         "       msr basepri, r0                                                                 \n" /* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */\r
 276         "       dsb                                                                                             \n"\r
 277         "       isb                                                                                             \n"\r
 278         "       bl vTaskSwitchContext                                                   \n"\r
 279         "       mov r0, #0                                                                              \n" /* r0 = 0. */\r
 280         "       msr basepri, r0                                                                 \n" /* Enable interrupts. */\r
 281         "                                                                                                       \n"\r
 282         "       ldr r2, pxCurrentTCBConst                                               \n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\r
 283         "       ldr r3, [r2]                                                                    \n" /* Read pxCurrentTCB. */\r
 284         "       ldr r1, [r3]                                                                    \n" /* The first item in pxCurrentTCB is the task top of stack. r1 now points to the top of stack. */\r
 285         "                                                                                                       \n"\r
 286         #if( configENABLE_MPU == 1 )\r
 287         "       dmb                                                                                             \n" /* Complete outstanding transfers before disabling MPU. */\r
 288         "       ldr r2, xMPUCTRLConst                                                   \n" /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */\r
 289         "       ldr r4, [r2]                                                                    \n" /* Read the value of MPU_CTRL. */\r
 290         "       bic r4, #1                                                                              \n" /* r4 = r4 & ~1 i.e. Clear the bit 0 in r4. */\r
 291         "       str r4, [r2]                                                                    \n" /* Disable MPU. */\r
 292         "                                                                                                       \n"\r
 293         "       adds r3, #4                                                                             \n" /* r3 = r3 + 4. r3 now points to MAIR0 in TCB. */\r
 294         "       ldr r4, [r3]                                                                    \n" /* r4 = *r3 i.e. r4 = MAIR0. */\r
 295         "       ldr r2, xMAIR0Const                                                             \n" /* r2 = 0xe000edc0 [Location of MAIR0]. */\r
 296         "       str r4, [r2]                                                                    \n" /* Program MAIR0. */\r
 297         "       ldr r2, xRNRConst                                                               \n" /* r2 = 0xe000ed98 [Location of RNR]. */\r
 298         "       movs r4, #4                                                                             \n" /* r4 = 4. */\r
 299         "       str r4, [r2]                                                                    \n" /* Program RNR = 4. */\r
 300         "       adds r3, #4                                                                             \n" /* r3 = r3 + 4. r3 now points to first RBAR in TCB. */\r
 301         "       ldr  r2, xRBARConst                                                             \n" /* r2 = 0xe000ed9c [Location of RBAR]. */\r
 302         "       ldmia r3!, {r4-r11}                                                             \n" /* Read 4 sets of RBAR/RLAR registers from TCB. */\r
 303         "       stmia r2!, {r4-r11}                                                             \n" /* Write 4 set of RBAR/RLAR registers using alias registers. */\r
 304         "                                                                                                       \n"\r
 305         "       ldr r2, xMPUCTRLConst                                                   \n" /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */\r
 306         "       ldr r4, [r2]                                                                    \n" /* Read the value of MPU_CTRL. */\r
 307         "       orr r4, #1                                                                              \n" /* r4 = r4 | 1 i.e. Set the bit 0 in r4. */\r
 308         "       str r4, [r2]                                                                    \n" /* Enable MPU. */\r
 309         "       dsb                                                                                             \n" /* Force memory writes before continuing. */\r
 310         #endif /* configENABLE_MPU */\r
 311         "                                                                                                       \n"\r
 312         #if( configENABLE_MPU == 1 )\r
 313         "       ldmia r1!, {r0, r2-r4}                                                  \n" /* Read from stack - r0 = xSecureContext, r2 = PSPLIM, r3 = CONTROL and r4 = LR. */\r
 314         "       msr psplim, r2                                                                  \n" /* Restore the PSPLIM register value for the task. */\r
 315         "       msr control, r3                                                                 \n" /* Restore the CONTROL register value for the task. */\r
 316         "       mov lr, r4                                                                              \n" /* LR = r4. */\r
 317         "       ldr r2, xSecureContextConst                                             \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */\r
 318         "       str r0, [r2]                                                                    \n" /* Restore the task's xSecureContext. */\r
 319         "       cbz r0, restore_ns_context                                              \n" /* If there is no secure context for the task, restore the non-secure context. */\r
 320         "       push {r1,r4}                                                                    \n"\r
 321         "       bl SecureContext_LoadContext                                    \n" /* Restore the secure context. */\r
 322         "       pop {r1,r4}                                                                             \n"\r
 323         "       mov lr, r4                                                                              \n" /* LR = r4. */\r
 324         "       lsls r2, r4, #25                                                                \n" /* r2 = r4 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */\r
 325         "       bpl restore_ns_context                                                  \n" /* bpl - branch if positive or zero. If r2 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */\r
 326         "       msr psp, r1                                                                             \n" /* Remember the new top of stack for the task. */\r
 327         "       bx lr                                                                                   \n"\r
 328         #else /* configENABLE_MPU */\r
 329         "       ldmia r1!, {r0, r2-r3}                                                  \n" /* Read from stack - r0 = xSecureContext, r2 = PSPLIM and r3 = LR. */\r
 330         "       msr psplim, r2                                                                  \n" /* Restore the PSPLIM register value for the task. */\r
 331         "       mov lr, r3                                                                              \n" /* LR = r3. */\r
 332         "       ldr r2, xSecureContextConst                                             \n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */\r
 333         "       str r0, [r2]                                                                    \n" /* Restore the task's xSecureContext. */\r
 334         "       cbz r0, restore_ns_context                                              \n" /* If there is no secure context for the task, restore the non-secure context. */\r
 335         "       push {r1,r3}                                                                    \n"\r
 336         "       bl SecureContext_LoadContext                                    \n" /* Restore the secure context. */\r
 337         "       pop {r1,r3}                                                                             \n"\r
 338         "       mov lr, r3                                                                              \n" /* LR = r3. */\r
 339         "       lsls r2, r3, #25                                                                \n" /* r2 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */\r
 340         "       bpl restore_ns_context                                                  \n" /* bpl - branch if positive or zero. If r2 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */\r
 341         "       msr psp, r1                                                                             \n" /* Remember the new top of stack for the task. */\r
 342         "       bx lr                                                                                   \n"\r
 343         #endif /* configENABLE_MPU */\r
 344         "                                                                                                       \n"\r
 345         " restore_ns_context:                                                           \n"\r
 346         "       ldmia r1!, {r4-r11}                                                             \n" /* Restore the registers that are not automatically restored. */\r
 347         #if( configENABLE_FPU == 1 )\r
 348         "       tst lr, #0x10                                                                   \n" /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the FPU is in use. */\r
 349         "       it eq                                                                                   \n"\r
 350         "       vldmiaeq r1!, {s16-s31}                                                 \n" /* Restore the FPU registers which are not restored automatically. */\r
 351         #endif /* configENABLE_FPU */\r
 352         "       msr psp, r1                                                                             \n" /* Remember the new top of stack for the task. */\r
 353         "       bx lr                                                                                   \n"\r
 354         "                                                                                                       \n"\r
 355         "       .align 4                                                                                \n"\r
 356         "pxCurrentTCBConst: .word pxCurrentTCB                          \n"\r
 357         "xSecureContextConst: .word xSecureContext                      \n"\r
 358         #if( configENABLE_MPU == 1 )\r
 359         "xMPUCTRLConst: .word 0xe000ed94                                        \n"\r
 360         "xMAIR0Const: .word 0xe000edc0                                          \n"\r
 361         "xRNRConst: .word 0xe000ed98                                            \n"\r
 362         "xRBARConst: .word 0xe000ed9c                                           \n"\r
 363         #endif /* configENABLE_MPU */\r
 364         :: "i"( configMAX_SYSCALL_INTERRUPT_PRIORITY )\r
 365         );\r
 366 }\r
 367 /*-----------------------------------------------------------*/\r
 368 \r
 369 void SVC_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */\r
 370 {\r
 371         __asm volatile\r
 372         (\r
 373         "       tst lr, #4                                                                              \n"\r
 374         "       ite eq                                                                                  \n"\r
 375         "       mrseq r0, msp                                                                   \n"\r
 376         "       mrsne r0, psp                                                                   \n"\r
 377         "       ldr r1, svchandler_address_const                                \n"\r
 378         "       bx r1                                                                                   \n"\r
 379         "                                                                                                       \n"\r
 380         "       .align 4                                                                                \n"\r
 381         "svchandler_address_const: .word vPortSVCHandler_C      \n"\r
 382         );\r
 383 }\r
 384 /*-----------------------------------------------------------*/\r
 385 \r
 386 void vPortAllocateSecureContext( uint32_t ulSecureStackSize ) /* __attribute__ (( naked )) */\r
 387 {\r
 388         __asm volatile\r
 389         (\r
 390         "       svc %0                                                                                  \n" /* Secure context is allocated in the supervisor call. */\r
 391         "       bx lr                                                                                   \n" /* Return. */\r
 392         :: "i" ( portSVC_ALLOCATE_SECURE_CONTEXT ) : "memory"\r
 393         );\r
 394 }\r
 395 /*-----------------------------------------------------------*/\r
 396 \r
 397 void vPortFreeSecureContext( uint32_t *pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */\r
 398 {\r
 399         __asm volatile\r
 400         (\r
 401         "       ldr r1, [r0]                                                                    \n" /* The first item in the TCB is the top of the stack. */\r
 402         "       ldr r0, [r1]                                                                    \n" /* The first item on the stack is the task's xSecureContext. */\r
 403         "       cmp r0, #0                                                                              \n" /* Raise svc if task's xSecureContext is not NULL. */\r
 404         "       it ne                                                                                   \n"\r
 405         "       svcne %0                                                                                \n" /* Secure context is freed in the supervisor call. */\r
 406         "       bx lr                                                                                   \n" /* Return. */\r
 407         :: "i" ( portSVC_FREE_SECURE_CONTEXT ) : "memory"\r
 408         );\r
 409 }\r
 410 /*-----------------------------------------------------------*/\r