git.sur5r.net Git - freertos/blob - FreeRTOS/Source/portable/GCC/ARM_CM33/secure/secure_context_port.c

   1 /*\r
   2  * FreeRTOS Kernel V10.3.0\r
   3  * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\r
   4  *\r
   5  * Permission is hereby granted, free of charge, to any person obtaining a copy of\r
   6  * this software and associated documentation files (the "Software"), to deal in\r
   7  * the Software without restriction, including without limitation the rights to\r
   8  * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\r
   9  * the Software, and to permit persons to whom the Software is furnished to do so,\r
  10  * subject to the following conditions:\r
  11  *\r
  12  * The above copyright notice and this permission notice shall be included in all\r
  13  * copies or substantial portions of the Software.\r
  14  *\r
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\r
  17  * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\r
  18  * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r
  19  * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
  20  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
  21  *\r
  22  * http://www.FreeRTOS.org\r
  23  * http://aws.amazon.com/freertos\r
  24  *\r
  25  * 1 tab == 4 spaces!\r
  26  */\r
  27 \r
  28 /* Secure context includes. */\r
  29 #include "secure_context.h"\r
  30 \r
  31 /* Secure port macros. */\r
  32 #include "secure_port_macros.h"\r
  33 \r
  34 secureportNON_SECURE_CALLABLE void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle )\r
  35 {\r
  36         /* xSecureContextHandle value is in r0. */\r
  37         __asm volatile\r
  38         (\r
  39         "       .syntax unified                                                 \n"\r
  40         "                                                                                       \n"\r
  41         "       mrs r1, ipsr                                                    \n" /* r1 = IPSR. */\r
  42         "       cbz r1, load_ctx_therad_mode                    \n" /* Do nothing if the processor is running in the Thread Mode. */\r
  43         "       ldmia r0!, {r1, r2}                                             \n" /* r1 = xSecureContextHandle->pucCurrentStackPointer, r2 = xSecureContextHandle->pucStackLimit. */\r
  44         #if( configENABLE_MPU == 1 )\r
  45         "       ldmia r1!, {r3}                                                 \n" /* Read CONTROL register value from task's stack. r3 = CONTROL. */\r
  46         "       msr control, r3                                                 \n" /* CONTROL = r3. */\r
  47         #endif /* configENABLE_MPU */\r
  48         "       msr psplim, r2                                                  \n" /* PSPLIM = r2. */\r
  49         "       msr psp, r1                                                             \n" /* PSP = r1. */\r
  50         "                                                                                       \n"\r
  51         " load_ctx_therad_mode:                                         \n"\r
  52         "       nop                                                                             \n"\r
  53         "                                                                                       \n"\r
  54         :::"r0", "r1", "r2"\r
  55         );\r
  56 }\r
  57 /*-----------------------------------------------------------*/\r
  58 \r
  59 secureportNON_SECURE_CALLABLE void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle )\r
  60 {\r
  61         /* xSecureContextHandle value is in r0. */\r
  62         __asm volatile\r
  63         (\r
  64         "       .syntax unified                                                 \n"\r
  65         "                                                                                       \n"\r
  66         "       mrs r1, ipsr                                                    \n" /* r1 = IPSR. */\r
  67         "       cbz r1, save_ctx_therad_mode                    \n" /* Do nothing if the processor is running in the Thread Mode. */\r
  68         "       mrs r1, psp                                                             \n" /* r1 = PSP. */\r
  69         #if( configENABLE_FPU == 1 )\r
  70         "       vstmdb r1!, {s0}                                                \n" /* Trigger the defferred stacking of FPU registers. */\r
  71         "       vldmia r1!, {s0}                                                \n" /* Nullify the effect of the pervious statement. */\r
  72         #endif /* configENABLE_FPU */\r
  73         #if( configENABLE_MPU == 1 )\r
  74         "       mrs r2, control                                                 \n" /* r2 = CONTROL. */\r
  75         "       stmdb r1!, {r2}                                                 \n" /* Store CONTROL value on the stack. */\r
  76         #endif /* configENABLE_MPU */\r
  77         "       str r1, [r0]                                                    \n" /* Save the top of stack in context. xSecureContextHandle->pucCurrentStackPointer = r1. */\r
  78         "       movs r1, %0                                                             \n" /* r1 = securecontextNO_STACK. */\r
  79         "       msr psplim, r1                                                  \n" /* PSPLIM = securecontextNO_STACK. */\r
  80         "       msr psp, r1                                                             \n" /* PSP = securecontextNO_STACK i.e. No stack for thread mode until next task's context is loaded. */\r
  81         "                                                                                       \n"\r
  82         " save_ctx_therad_mode:                                         \n"\r
  83         "       nop                                                                             \n"\r
  84         "                                                                                       \n"\r
  85         :: "i" ( securecontextNO_STACK ) : "r1", "memory"\r
  86         );\r
  87 }\r
  88 /*-----------------------------------------------------------*/\r