git.sur5r.net Git - freertos/blob - FreeRTOS/Source/portable/GCC/ARM_CM3_MPU/port.c

   1 /*\r
   2     FreeRTOS V9.0.0 - Copyright (C) 2016 Real Time Engineers Ltd.\r
   3     All rights reserved\r
   4 \r
   5     VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
   6 \r
   7     This file is part of the FreeRTOS distribution.\r
   8 \r
   9     FreeRTOS is free software; you can redistribute it and/or modify it under\r
  10     the terms of the GNU General Public License (version 2) as published by the\r
  11     Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception.\r
  12 \r
  13     ***************************************************************************\r
  14     >>!   NOTE: The modification to the GPL is included to allow you to     !<<\r
  15     >>!   distribute a combined work that includes FreeRTOS without being   !<<\r
  16     >>!   obliged to provide the source code for proprietary components     !<<\r
  17     >>!   outside of the FreeRTOS kernel.                                   !<<\r
  18     ***************************************************************************\r
  19 \r
  20     FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
  21     WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
  22     FOR A PARTICULAR PURPOSE.  Full license text is available on the following\r
  23     link: http://www.freertos.org/a00114.html\r
  24 \r
  25     ***************************************************************************\r
  26      *                                                                       *\r
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  33      *    to support the FreeRTOS project by purchasing a FreeRTOS           *\r
  34      *    tutorial book, reference manual, or both:                          *\r
  35      *    http://www.FreeRTOS.org/Documentation                              *\r
  36      *                                                                       *\r
  37     ***************************************************************************\r
  38 \r
  39     http://www.FreeRTOS.org/FAQHelp.html - Having a problem?  Start by reading\r
  40     the FAQ page "My application does not run, what could be wrong?".  Have you\r
  41     defined configASSERT()?\r
  42 \r
  43     http://www.FreeRTOS.org/support - In return for receiving this top quality\r
  44     embedded software for free we request you assist our global community by\r
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  46 \r
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  48     be as productive as possible as early as possible.  Now you can receive\r
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  50     Ltd, and the world's leading authority on the world's leading RTOS.\r
  51 \r
  52     http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
  53     including FreeRTOS+Trace - an indispensable productivity tool, a DOS\r
  54     compatible FAT file system, and our tiny thread aware UDP/IP stack.\r
  55 \r
  56     http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.\r
  57     Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.\r
  58 \r
  59     http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High\r
  60     Integrity Systems ltd. to sell under the OpenRTOS brand.  Low cost OpenRTOS\r
  61     licenses offer ticketed support, indemnification and commercial middleware.\r
  62 \r
  63     http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
  64     engineered and independently SIL3 certified version for use in safety and\r
  65     mission critical applications that require provable dependability.\r
  66 \r
  67     1 tab == 4 spaces!\r
  68 */\r
  69 \r
  70 /*-----------------------------------------------------------\r
  71  * Implementation of functions defined in portable.h for the ARM CM3 port.\r
  72  *----------------------------------------------------------*/\r
  73 \r
  74 /* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining\r
  75 all the API functions to use the MPU wrappers.  That should only be done when\r
  76 task.h is included from an application file. */\r
  77 #define MPU_WRAPPERS_INCLUDED_FROM_API_FILE\r
  78 \r
  79 /* Scheduler includes. */\r
  80 #include "FreeRTOS.h"\r
  81 #include "task.h"\r
  82 #include "queue.h"\r
  83 #include "timers.h"\r
  84 #include "event_groups.h"\r
  85 #include "mpu_prototypes.h"\r
  86 \r
  87 #undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE\r
  88 \r
  89 /* Constants required to access and manipulate the NVIC. */\r
  90 #define portNVIC_SYSTICK_CTRL_REG                               ( * ( ( volatile uint32_t * ) 0xe000e010 ) )\r
  91 #define portNVIC_SYSTICK_LOAD_REG                               ( * ( ( volatile uint32_t * ) 0xe000e014 ) )\r
  92 #define portNVIC_SYSPRI2_REG                                    ( *     ( ( volatile uint32_t * ) 0xe000ed20 ) )\r
  93 #define portNVIC_SYSPRI1_REG                                    ( * ( ( volatile uint32_t * ) 0xe000ed1c ) )\r
  94 #define portNVIC_SYS_CTRL_STATE_REG                             ( * ( ( volatile uint32_t * ) 0xe000ed24 ) )\r
  95 #define portNVIC_MEM_FAULT_ENABLE                               ( 1UL << 16UL )\r
  96 \r
  97 /* Constants required to access and manipulate the MPU. */\r
  98 #define portMPU_TYPE_REG                                                ( * ( ( volatile uint32_t * ) 0xe000ed90 ) )\r
  99 #define portMPU_REGION_BASE_ADDRESS_REG                 ( * ( ( volatile uint32_t * ) 0xe000ed9C ) )\r
 100 #define portMPU_REGION_ATTRIBUTE_REG                    ( * ( ( volatile uint32_t * ) 0xe000edA0 ) )\r
 101 #define portMPU_CTRL_REG                                                ( * ( ( volatile uint32_t * ) 0xe000ed94 ) )\r
 102 #define portEXPECTED_MPU_TYPE_VALUE                             ( 8UL << 8UL ) /* 8 regions, unified. */\r
 103 #define portMPU_ENABLE                                                  ( 0x01UL )\r
 104 #define portMPU_BACKGROUND_ENABLE                               ( 1UL << 2UL )\r
 105 #define portPRIVILEGED_EXECUTION_START_ADDRESS  ( 0UL )\r
 106 #define portMPU_REGION_VALID                                    ( 0x10UL )\r
 107 #define portMPU_REGION_ENABLE                                   ( 0x01UL )\r
 108 #define portPERIPHERALS_START_ADDRESS                   0x40000000UL\r
 109 #define portPERIPHERALS_END_ADDRESS                             0x5FFFFFFFUL\r
 110 \r
 111 /* Constants required to access and manipulate the SysTick. */\r
 112 #define portNVIC_SYSTICK_CLK                                    ( 0x00000004UL )\r
 113 #define portNVIC_SYSTICK_INT                                    ( 0x00000002UL )\r
 114 #define portNVIC_SYSTICK_ENABLE                                 ( 0x00000001UL )\r
 115 #define portNVIC_PENDSV_PRI                                             ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL )\r
 116 #define portNVIC_SYSTICK_PRI                                    ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL )\r
 117 #define portNVIC_SVC_PRI                                                ( ( ( uint32_t ) configMAX_SYSCALL_INTERRUPT_PRIORITY - 1UL ) << 24UL )\r
 118 \r
 119 /* Constants required to set up the initial stack. */\r
 120 #define portINITIAL_XPSR                                                ( 0x01000000 )\r
 121 #define portINITIAL_CONTROL_IF_UNPRIVILEGED             ( 0x03 )\r
 122 #define portINITIAL_CONTROL_IF_PRIVILEGED               ( 0x02 )\r
 123 \r
 124 /* Constants required to check the validity of an interrupt priority. */\r
 125 #define portFIRST_USER_INTERRUPT_NUMBER         ( 16 )\r
 126 #define portNVIC_IP_REGISTERS_OFFSET_16         ( 0xE000E3F0 )\r
 127 #define portAIRCR_REG                                           ( * ( ( volatile uint32_t * ) 0xE000ED0C ) )\r
 128 #define portMAX_8_BIT_VALUE                                     ( ( uint8_t ) 0xff )\r
 129 #define portTOP_BIT_OF_BYTE                                     ( ( uint8_t ) 0x80 )\r
 130 #define portMAX_PRIGROUP_BITS                           ( ( uint8_t ) 7 )\r
 131 #define portPRIORITY_GROUP_MASK                         ( 0x07UL << 8UL )\r
 132 #define portPRIGROUP_SHIFT                                      ( 8UL )\r
 133 \r
 134 /* Offsets in the stack to the parameters when inside the SVC handler. */\r
 135 #define portOFFSET_TO_PC                                                ( 6 )\r
 136 \r
 137 /* For strict compliance with the Cortex-M spec the task start address should\r
 138 have bit-0 clear, as it is loaded into the PC on exit from an ISR. */\r
 139 #define portSTART_ADDRESS_MASK                          ( ( StackType_t ) 0xfffffffeUL )\r
 140 \r
 141 /* Each task maintains its own interrupt status in the critical nesting\r
 142 variable.  Note this is not saved as part of the task context as context\r
 143 switches can only occur when uxCriticalNesting is zero. */\r
 144 static UBaseType_t uxCriticalNesting = 0xaaaaaaaa;\r
 145 \r
 146 /*\r
 147  * Setup the timer to generate the tick interrupts.\r
 148  */\r
 149 static void prvSetupTimerInterrupt( void ) PRIVILEGED_FUNCTION;\r
 150 \r
 151 /*\r
 152  * Configure a number of standard MPU regions that are used by all tasks.\r
 153  */\r
 154 static void prvSetupMPU( void ) PRIVILEGED_FUNCTION;\r
 155 \r
 156 /*\r
 157  * Return the smallest MPU region size that a given number of bytes will fit\r
 158  * into.  The region size is returned as the value that should be programmed\r
 159  * into the region attribute register for that region.\r
 160  */\r
 161 static uint32_t prvGetMPURegionSizeSetting( uint32_t ulActualSizeInBytes ) PRIVILEGED_FUNCTION;\r
 162 \r
 163 /*\r
 164  * Checks to see if being called from the context of an unprivileged task, and\r
 165  * if so raises the privilege level and returns false - otherwise does nothing\r
 166  * other than return true.\r
 167  */\r
 168 BaseType_t xPortRaisePrivilege( void ) __attribute__(( naked ));\r
 169 \r
 170 /*\r
 171  * Standard FreeRTOS exception handlers.\r
 172  */\r
 173 void xPortPendSVHandler( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;\r
 174 void xPortSysTickHandler( void )  __attribute__ ((optimize("3"))) PRIVILEGED_FUNCTION;\r
 175 void vPortSVCHandler( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;\r
 176 \r
 177 /*\r
 178  * Starts the scheduler by restoring the context of the first task to run.\r
 179  */\r
 180 static void prvRestoreContextOfFirstTask( void ) __attribute__(( naked )) PRIVILEGED_FUNCTION;\r
 181 \r
 182 /*\r
 183  * C portion of the SVC handler.  The SVC handler is split between an asm entry\r
 184  * and a C wrapper for simplicity of coding and maintenance.\r
 185  */\r
 186 static void prvSVCHandler( uint32_t *pulRegisters ) __attribute__(( noinline )) PRIVILEGED_FUNCTION;\r
 187 \r
 188 /*\r
 189  * Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure\r
 190  * FreeRTOS API functions are not called from interrupts that have been assigned\r
 191  * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY.\r
 192  */\r
 193 #if ( configASSERT_DEFINED == 1 )\r
 194          static uint8_t ucMaxSysCallPriority = 0;\r
 195          static uint32_t ulMaxPRIGROUPValue = 0;\r
 196          static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const volatile uint8_t * const ) portNVIC_IP_REGISTERS_OFFSET_16;\r
 197 #endif /* configASSERT_DEFINED */\r
 198 \r
 199 /*-----------------------------------------------------------*/\r
 200 \r
 201 /*\r
 202  * See header file for description.\r
 203  */\r
 204 StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters, BaseType_t xRunPrivileged )\r
 205 {\r
 206         /* Simulate the stack frame as it would be created by a context switch\r
 207         interrupt. */\r
 208         pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */\r
 209         *pxTopOfStack = portINITIAL_XPSR;       /* xPSR */\r
 210         pxTopOfStack--;\r
 211         *pxTopOfStack = ( ( StackType_t ) pxCode ) & portSTART_ADDRESS_MASK;    /* PC */\r
 212         pxTopOfStack--;\r
 213         *pxTopOfStack = 0;      /* LR */\r
 214         pxTopOfStack -= 5;      /* R12, R3, R2 and R1. */\r
 215         *pxTopOfStack = ( StackType_t ) pvParameters;   /* R0 */\r
 216         pxTopOfStack -= 9;      /* R11, R10, R9, R8, R7, R6, R5 and R4. */\r
 217 \r
 218         if( xRunPrivileged == pdTRUE )\r
 219         {\r
 220                 *pxTopOfStack = portINITIAL_CONTROL_IF_PRIVILEGED;\r
 221         }\r
 222         else\r
 223         {\r
 224                 *pxTopOfStack = portINITIAL_CONTROL_IF_UNPRIVILEGED;\r
 225         }\r
 226 \r
 227         return pxTopOfStack;\r
 228 }\r
 229 /*-----------------------------------------------------------*/\r
 230 \r
 231 void vPortSVCHandler( void )\r
 232 {\r
 233         /* Assumes psp was in use. */\r
 234         __asm volatile\r
 235         (\r
 236                 #ifndef USE_PROCESS_STACK       /* Code should not be required if a main() is using the process stack. */\r
 237                         "       tst lr, #4                                              \n"\r
 238                         "       ite eq                                                  \n"\r
 239                         "       mrseq r0, msp                                   \n"\r
 240                         "       mrsne r0, psp                                   \n"\r
 241                 #else\r
 242                         "       mrs r0, psp                                             \n"\r
 243                 #endif\r
 244                         "       b %0                                                    \n"\r
 245                         ::"i"(prvSVCHandler):"r0"\r
 246         );\r
 247 }\r
 248 /*-----------------------------------------------------------*/\r
 249 \r
 250 static void prvSVCHandler(      uint32_t *pulParam )\r
 251 {\r
 252 uint8_t ucSVCNumber;\r
 253 \r
 254         /* The stack contains: r0, r1, r2, r3, r12, r14, the return address and\r
 255         xPSR.  The first argument (r0) is pulParam[ 0 ]. */\r
 256         ucSVCNumber = ( ( uint8_t * ) pulParam[ portOFFSET_TO_PC ] )[ -2 ];\r
 257         switch( ucSVCNumber )\r
 258         {\r
 259                 case portSVC_START_SCHEDULER    :       portNVIC_SYSPRI1_REG |= portNVIC_SVC_PRI;\r
 260                                                                                         prvRestoreContextOfFirstTask();\r
 261                                                                                         break;\r
 262 \r
 263                 case portSVC_YIELD                              :       portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;\r
 264                                                                                         /* Barriers are normally not required\r
 265                                                                                         but do ensure the code is completely\r
 266                                                                                         within the specified behaviour for the\r
 267                                                                                         architecture. */\r
 268                                                                                         __asm volatile( "dsb" );\r
 269                                                                                         __asm volatile( "isb" );\r
 270 \r
 271                                                                                         break;\r
 272 \r
 273                 case portSVC_RAISE_PRIVILEGE    :       __asm volatile\r
 274                                                                                         (\r
 275                                                                                                 "       mrs r1, control         \n" /* Obtain current control value. */\r
 276                                                                                                 "       bic r1, #1                      \n" /* Set privilege bit. */\r
 277                                                                                                 "       msr control, r1         \n" /* Write back new control value. */\r
 278                                                                                                 :::"r1"\r
 279                                                                                         );\r
 280                                                                                         break;\r
 281 \r
 282                 default                                                 :       /* Unknown SVC call. */\r
 283                                                                                         break;\r
 284         }\r
 285 }\r
 286 /*-----------------------------------------------------------*/\r
 287 \r
 288 static void prvRestoreContextOfFirstTask( void )\r
 289 {\r
 290         __asm volatile\r
 291         (\r
 292                 "       ldr r0, =0xE000ED08                             \n" /* Use the NVIC offset register to locate the stack. */\r
 293                 "       ldr r0, [r0]                                    \n"\r
 294                 "       ldr r0, [r0]                                    \n"\r
 295                 "       msr msp, r0                                             \n" /* Set the msp back to the start of the stack. */\r
 296                 "       ldr     r3, pxCurrentTCBConst2          \n" /* Restore the context. */\r
 297                 "       ldr r1, [r3]                                    \n"\r
 298                 "       ldr r0, [r1]                                    \n" /* The first item in the TCB is the task top of stack. */\r
 299                 "       add r1, r1, #4                                  \n" /* Move onto the second item in the TCB... */\r
 300                 "       ldr r2, =0xe000ed9c                             \n" /* Region Base Address register. */\r
 301                 "       ldmia r1!, {r4-r11}                             \n" /* Read 4 sets of MPU registers. */\r
 302                 "       stmia r2!, {r4-r11}                             \n" /* Write 4 sets of MPU registers. */\r
 303                 "       ldmia r0!, {r3, r4-r11}                 \n" /* Pop the registers that are not automatically saved on exception entry. */\r
 304                 "       msr control, r3                                 \n"\r
 305                 "       msr psp, r0                                             \n" /* Restore the task stack pointer. */\r
 306                 "       mov r0, #0                                              \n"\r
 307                 "       msr     basepri, r0                                     \n"\r
 308                 "       ldr r14, =0xfffffffd                    \n" /* Load exec return code. */\r
 309                 "       bx r14                                                  \n"\r
 310                 "                                                                       \n"\r
 311                 "       .align 4                                                \n"\r
 312                 "pxCurrentTCBConst2: .word pxCurrentTCB \n"\r
 313         );\r
 314 }\r
 315 /*-----------------------------------------------------------*/\r
 316 \r
 317 /*\r
 318  * See header file for description.\r
 319  */\r
 320 BaseType_t xPortStartScheduler( void )\r
 321 {\r
 322         /* configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0.  See\r
 323         http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */\r
 324         configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) );\r
 325 \r
 326         #if( configASSERT_DEFINED == 1 )\r
 327         {\r
 328                 volatile uint32_t ulOriginalPriority;\r
 329                 volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER );\r
 330                 volatile uint8_t ucMaxPriorityValue;\r
 331 \r
 332                 /* Determine the maximum priority from which ISR safe FreeRTOS API\r
 333                 functions can be called.  ISR safe functions are those that end in\r
 334                 "FromISR".  FreeRTOS maintains separate thread and ISR API functions to\r
 335                 ensure interrupt entry is as fast and simple as possible.\r
 336 \r
 337                 Save the interrupt priority value that is about to be clobbered. */\r
 338                 ulOriginalPriority = *pucFirstUserPriorityRegister;\r
 339 \r
 340                 /* Determine the number of priority bits available.  First write to all\r
 341                 possible bits. */\r
 342                 *pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;\r
 343 \r
 344                 /* Read the value back to see how many bits stuck. */\r
 345                 ucMaxPriorityValue = *pucFirstUserPriorityRegister;\r
 346 \r
 347                 /* Use the same mask on the maximum system call priority. */\r
 348                 ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;\r
 349 \r
 350                 /* Calculate the maximum acceptable priority group value for the number\r
 351                 of bits read back. */\r
 352                 ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;\r
 353                 while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )\r
 354                 {\r
 355                         ulMaxPRIGROUPValue--;\r
 356                         ucMaxPriorityValue <<= ( uint8_t ) 0x01;\r
 357                 }\r
 358 \r
 359                 /* Shift the priority group value back to its position within the AIRCR\r
 360                 register. */\r
 361                 ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;\r
 362                 ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;\r
 363 \r
 364                 /* Restore the clobbered interrupt priority register to its original\r
 365                 value. */\r
 366                 *pucFirstUserPriorityRegister = ulOriginalPriority;\r
 367         }\r
 368         #endif /* conifgASSERT_DEFINED */\r
 369 \r
 370         /* Make PendSV and SysTick the same priority as the kernel, and the SVC\r
 371         handler higher priority so it can be used to exit a critical section (where\r
 372         lower priorities are masked). */\r
 373         portNVIC_SYSPRI2_REG |= portNVIC_PENDSV_PRI;\r
 374         portNVIC_SYSPRI2_REG |= portNVIC_SYSTICK_PRI;\r
 375 \r
 376         /* Configure the regions in the MPU that are common to all tasks. */\r
 377         prvSetupMPU();\r
 378 \r
 379         /* Start the timer that generates the tick ISR.  Interrupts are disabled\r
 380         here already. */\r
 381         prvSetupTimerInterrupt();\r
 382 \r
 383         /* Initialise the critical nesting count ready for the first task. */\r
 384         uxCriticalNesting = 0;\r
 385 \r
 386         /* Start the first task. */\r
 387         __asm volatile(\r
 388                                         " ldr r0, =0xE000ED08   \n" /* Use the NVIC offset register to locate the stack. */\r
 389                                         " ldr r0, [r0]                  \n"\r
 390                                         " ldr r0, [r0]                  \n"\r
 391                                         " msr msp, r0                   \n" /* Set the msp back to the start of the stack. */\r
 392                                         " cpsie i                               \n" /* Globally enable interrupts. */\r
 393                                         " cpsie f                               \n"\r
 394                                         " dsb                                   \n"\r
 395                                         " isb                                   \n"\r
 396                                         " svc %0                                \n" /* System call to start first task. */\r
 397                                         " nop                                   \n"\r
 398                                         :: "i" (portSVC_START_SCHEDULER) );\r
 399 \r
 400         /* Should not get here! */\r
 401         return 0;\r
 402 }\r
 403 /*-----------------------------------------------------------*/\r
 404 \r
 405 void vPortEndScheduler( void )\r
 406 {\r
 407         /* Not implemented in ports where there is nothing to return to.\r
 408         Artificially force an assert. */\r
 409         configASSERT( uxCriticalNesting == 1000UL );\r
 410 }\r
 411 /*-----------------------------------------------------------*/\r
 412 \r
 413 void vPortEnterCritical( void )\r
 414 {\r
 415 BaseType_t xRunningPrivileged = xPortRaisePrivilege();\r
 416 \r
 417         portDISABLE_INTERRUPTS();\r
 418         uxCriticalNesting++;\r
 419 \r
 420         vPortResetPrivilege( xRunningPrivileged );\r
 421 }\r
 422 /*-----------------------------------------------------------*/\r
 423 \r
 424 void vPortExitCritical( void )\r
 425 {\r
 426 BaseType_t xRunningPrivileged = xPortRaisePrivilege();\r
 427 \r
 428         configASSERT( uxCriticalNesting );\r
 429         uxCriticalNesting--;\r
 430         if( uxCriticalNesting == 0 )\r
 431         {\r
 432                 portENABLE_INTERRUPTS();\r
 433         }\r
 434         vPortResetPrivilege( xRunningPrivileged );\r
 435 }\r
 436 /*-----------------------------------------------------------*/\r
 437 \r
 438 void xPortPendSVHandler( void )\r
 439 {\r
 440         /* This is a naked function. */\r
 441 \r
 442         __asm volatile\r
 443         (\r
 444                 "       mrs r0, psp                                                     \n"\r
 445                 "                                                                               \n"\r
 446                 "       ldr     r3, pxCurrentTCBConst                   \n" /* Get the location of the current TCB. */\r
 447                 "       ldr     r2, [r3]                                                \n"\r
 448                 "                                                                               \n"\r
 449                 "       mrs r1, control                                         \n"\r
 450                 "       stmdb r0!, {r1, r4-r11}                         \n" /* Save the remaining registers. */\r
 451                 "       str r0, [r2]                                            \n" /* Save the new top of stack into the first member of the TCB. */\r
 452                 "                                                                               \n"\r
 453                 "       stmdb sp!, {r3, r14}                            \n"\r
 454                 "       mov r0, %0                                                      \n"\r
 455                 "       msr basepri, r0                                         \n"\r
 456                 "       bl vTaskSwitchContext                           \n"\r
 457                 "       mov r0, #0                                                      \n"\r
 458                 "       msr basepri, r0                                         \n"\r
 459                 "       ldmia sp!, {r3, r14}                            \n"\r
 460                 "                                                                               \n"     /* Restore the context. */\r
 461                 "       ldr r1, [r3]                                            \n"\r
 462                 "       ldr r0, [r1]                                            \n" /* The first item in the TCB is the task top of stack. */\r
 463                 "       add r1, r1, #4                                          \n" /* Move onto the second item in the TCB... */\r
 464                 "       ldr r2, =0xe000ed9c                                     \n" /* Region Base Address register. */\r
 465                 "       ldmia r1!, {r4-r11}                                     \n" /* Read 4 sets of MPU registers. */\r
 466                 "       stmia r2!, {r4-r11}                                     \n" /* Write 4 sets of MPU registers. */\r
 467                 "       ldmia r0!, {r3, r4-r11}                         \n" /* Pop the registers that are not automatically saved on exception entry. */\r
 468                 "       msr control, r3                                         \n"\r
 469                 "                                                                               \n"\r
 470                 "       msr psp, r0                                                     \n"\r
 471                 "       bx r14                                                          \n"\r
 472                 "                                                                               \n"\r
 473                 "       .align 4                                                        \n"\r
 474                 "pxCurrentTCBConst: .word pxCurrentTCB  \n"\r
 475                 ::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY)\r
 476         );\r
 477 }\r
 478 /*-----------------------------------------------------------*/\r
 479 \r
 480 void xPortSysTickHandler( void )\r
 481 {\r
 482 uint32_t ulDummy;\r
 483 \r
 484         ulDummy = portSET_INTERRUPT_MASK_FROM_ISR();\r
 485         {\r
 486                 /* Increment the RTOS tick. */\r
 487                 if( xTaskIncrementTick() != pdFALSE )\r
 488                 {\r
 489                         /* Pend a context switch. */\r
 490                         portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;\r
 491                 }\r
 492         }\r
 493         portCLEAR_INTERRUPT_MASK_FROM_ISR( ulDummy );\r
 494 }\r
 495 /*-----------------------------------------------------------*/\r
 496 \r
 497 /*\r
 498  * Setup the systick timer to generate the tick interrupts at the required\r
 499  * frequency.\r
 500  */\r
 501 static void prvSetupTimerInterrupt( void )\r
 502 {\r
 503         /* Configure SysTick to interrupt at the requested rate. */\r
 504         portNVIC_SYSTICK_LOAD_REG = ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;\r
 505         portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK | portNVIC_SYSTICK_INT | portNVIC_SYSTICK_ENABLE;\r
 506 }\r
 507 /*-----------------------------------------------------------*/\r
 508 \r
 509 static void prvSetupMPU( void )\r
 510 {\r
 511 extern uint32_t __privileged_functions_end__[];\r
 512 extern uint32_t __FLASH_segment_start__[];\r
 513 extern uint32_t __FLASH_segment_end__[];\r
 514 extern uint32_t __privileged_data_start__[];\r
 515 extern uint32_t __privileged_data_end__[];\r
 516 \r
 517         /* Check the expected MPU is present. */\r
 518         if( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE )\r
 519         {\r
 520                 /* First setup the entire flash for unprivileged read only access. */\r
 521                 portMPU_REGION_BASE_ADDRESS_REG =       ( ( uint32_t ) __FLASH_segment_start__ ) | /* Base address. */\r
 522                                                                                         ( portMPU_REGION_VALID ) |\r
 523                                                                                         ( portUNPRIVILEGED_FLASH_REGION );\r
 524 \r
 525                 portMPU_REGION_ATTRIBUTE_REG =  ( portMPU_REGION_READ_ONLY ) |\r
 526                                                                                 ( portMPU_REGION_CACHEABLE_BUFFERABLE ) |\r
 527                                                                                 ( prvGetMPURegionSizeSetting( ( uint32_t ) __FLASH_segment_end__ - ( uint32_t ) __FLASH_segment_start__ ) ) |\r
 528                                                                                 ( portMPU_REGION_ENABLE );\r
 529 \r
 530                 /* Setup the first 16K for privileged only access (even though less\r
 531                 than 10K is actually being used).  This is where the kernel code is\r
 532                 placed. */\r
 533                 portMPU_REGION_BASE_ADDRESS_REG =       ( ( uint32_t ) __FLASH_segment_start__ ) | /* Base address. */\r
 534                                                                                         ( portMPU_REGION_VALID ) |\r
 535                                                                                         ( portPRIVILEGED_FLASH_REGION );\r
 536 \r
 537                 portMPU_REGION_ATTRIBUTE_REG =  ( portMPU_REGION_PRIVILEGED_READ_ONLY ) |\r
 538                                                                                 ( portMPU_REGION_CACHEABLE_BUFFERABLE ) |\r
 539                                                                                 ( prvGetMPURegionSizeSetting( ( uint32_t ) __privileged_functions_end__ - ( uint32_t ) __FLASH_segment_start__ ) ) |\r
 540                                                                                 ( portMPU_REGION_ENABLE );\r
 541 \r
 542                 /* Setup the privileged data RAM region.  This is where the kernel data\r
 543                 is placed. */\r
 544                 portMPU_REGION_BASE_ADDRESS_REG =       ( ( uint32_t ) __privileged_data_start__ ) | /* Base address. */\r
 545                                                                                         ( portMPU_REGION_VALID ) |\r
 546                                                                                         ( portPRIVILEGED_RAM_REGION );\r
 547 \r
 548                 portMPU_REGION_ATTRIBUTE_REG =  ( portMPU_REGION_PRIVILEGED_READ_WRITE ) |\r
 549                                                                                 ( portMPU_REGION_CACHEABLE_BUFFERABLE ) |\r
 550                                                                                 prvGetMPURegionSizeSetting( ( uint32_t ) __privileged_data_end__ - ( uint32_t ) __privileged_data_start__ ) |\r
 551                                                                                 ( portMPU_REGION_ENABLE );\r
 552 \r
 553                 /* By default allow everything to access the general peripherals.  The\r
 554                 system peripherals and registers are protected. */\r
 555                 portMPU_REGION_BASE_ADDRESS_REG =       ( portPERIPHERALS_START_ADDRESS ) |\r
 556                                                                                         ( portMPU_REGION_VALID ) |\r
 557                                                                                         ( portGENERAL_PERIPHERALS_REGION );\r
 558 \r
 559                 portMPU_REGION_ATTRIBUTE_REG =  ( portMPU_REGION_READ_WRITE | portMPU_REGION_EXECUTE_NEVER ) |\r
 560                                                                                 ( prvGetMPURegionSizeSetting( portPERIPHERALS_END_ADDRESS - portPERIPHERALS_START_ADDRESS ) ) |\r
 561                                                                                 ( portMPU_REGION_ENABLE );\r
 562 \r
 563                 /* Enable the memory fault exception. */\r
 564                 portNVIC_SYS_CTRL_STATE_REG |= portNVIC_MEM_FAULT_ENABLE;\r
 565 \r
 566                 /* Enable the MPU with the background region configured. */\r
 567                 portMPU_CTRL_REG |= ( portMPU_ENABLE | portMPU_BACKGROUND_ENABLE );\r
 568         }\r
 569 }\r
 570 /*-----------------------------------------------------------*/\r
 571 \r
 572 static uint32_t prvGetMPURegionSizeSetting( uint32_t ulActualSizeInBytes )\r
 573 {\r
 574 uint32_t ulRegionSize, ulReturnValue = 4;\r
 575 \r
 576         /* 32 is the smallest region size, 31 is the largest valid value for\r
 577         ulReturnValue. */\r
 578         for( ulRegionSize = 32UL; ulReturnValue < 31UL; ( ulRegionSize <<= 1UL ) )\r
 579         {\r
 580                 if( ulActualSizeInBytes <= ulRegionSize )\r
 581                 {\r
 582                         break;\r
 583                 }\r
 584                 else\r
 585                 {\r
 586                         ulReturnValue++;\r
 587                 }\r
 588         }\r
 589 \r
 590         /* Shift the code by one before returning so it can be written directly\r
 591         into the the correct bit position of the attribute register. */\r
 592         return ( ulReturnValue << 1UL );\r
 593 }\r
 594 /*-----------------------------------------------------------*/\r
 595 \r
 596 BaseType_t xPortRaisePrivilege( void )\r
 597 {\r
 598         __asm volatile\r
 599         (\r
 600                 "       mrs r0, control                                         \n"\r
 601                 "       tst r0, #1                                                      \n" /* Is the task running privileged? */\r
 602                 "       itte ne                                                         \n"\r
 603                 "       movne r0, #0                                            \n" /* CONTROL[0]!=0, return false. */\r
 604                 "       svcne %0                                                        \n" /* Switch to privileged. */\r
 605                 "       moveq r0, #1                                            \n" /* CONTROL[0]==0, return true. */\r
 606                 "       bx lr                                                           \n"\r
 607                 :: "i" (portSVC_RAISE_PRIVILEGE) : "r0"\r
 608         );\r
 609 \r
 610         return 0;\r
 611 }\r
 612 /*-----------------------------------------------------------*/\r
 613 \r
 614 void vPortStoreTaskMPUSettings( xMPU_SETTINGS *xMPUSettings, const struct xMEMORY_REGION * const xRegions, StackType_t *pxBottomOfStack, uint32_t ulStackDepth )\r
 615 {\r
 616 extern uint32_t __SRAM_segment_start__[];\r
 617 extern uint32_t __SRAM_segment_end__[];\r
 618 extern uint32_t __privileged_data_start__[];\r
 619 extern uint32_t __privileged_data_end__[];\r
 620 int32_t lIndex;\r
 621 uint32_t ul;\r
 622 \r
 623         if( xRegions == NULL )\r
 624         {\r
 625                 /* No MPU regions are specified so allow access to all RAM. */\r
 626                 xMPUSettings->xRegion[ 0 ].ulRegionBaseAddress =\r
 627                                 ( ( uint32_t ) __SRAM_segment_start__ ) | /* Base address. */\r
 628                                 ( portMPU_REGION_VALID ) |\r
 629                                 ( portSTACK_REGION );\r
 630 \r
 631                 xMPUSettings->xRegion[ 0 ].ulRegionAttribute =\r
 632                                 ( portMPU_REGION_READ_WRITE ) |\r
 633                                 ( portMPU_REGION_CACHEABLE_BUFFERABLE ) |\r
 634                                 ( prvGetMPURegionSizeSetting( ( uint32_t ) __SRAM_segment_end__ - ( uint32_t ) __SRAM_segment_start__ ) ) |\r
 635                                 ( portMPU_REGION_ENABLE );\r
 636 \r
 637                 /* Re-instate the privileged only RAM region as xRegion[ 0 ] will have\r
 638                 just removed the privileged only parameters. */\r
 639                 xMPUSettings->xRegion[ 1 ].ulRegionBaseAddress =\r
 640                                 ( ( uint32_t ) __privileged_data_start__ ) | /* Base address. */\r
 641                                 ( portMPU_REGION_VALID ) |\r
 642                                 ( portSTACK_REGION + 1 );\r
 643 \r
 644                 xMPUSettings->xRegion[ 1 ].ulRegionAttribute =\r
 645                                 ( portMPU_REGION_PRIVILEGED_READ_WRITE ) |\r
 646                                 ( portMPU_REGION_CACHEABLE_BUFFERABLE ) |\r
 647                                 prvGetMPURegionSizeSetting( ( uint32_t ) __privileged_data_end__ - ( uint32_t ) __privileged_data_start__ ) |\r
 648                                 ( portMPU_REGION_ENABLE );\r
 649 \r
 650                 /* Invalidate all other regions. */\r
 651                 for( ul = 2; ul <= portNUM_CONFIGURABLE_REGIONS; ul++ )\r
 652                 {\r
 653                         xMPUSettings->xRegion[ ul ].ulRegionBaseAddress = ( portSTACK_REGION + ul ) | portMPU_REGION_VALID;\r
 654                         xMPUSettings->xRegion[ ul ].ulRegionAttribute = 0UL;\r
 655                 }\r
 656         }\r
 657         else\r
 658         {\r
 659                 /* This function is called automatically when the task is created - in\r
 660                 which case the stack region parameters will be valid.  At all other\r
 661                 times the stack parameters will not be valid and it is assumed that the\r
 662                 stack region has already been configured. */\r
 663                 if( ulStackDepth > 0 )\r
 664                 {\r
 665                         /* Define the region that allows access to the stack. */\r
 666                         xMPUSettings->xRegion[ 0 ].ulRegionBaseAddress =\r
 667                                         ( ( uint32_t ) pxBottomOfStack ) |\r
 668                                         ( portMPU_REGION_VALID ) |\r
 669                                         ( portSTACK_REGION ); /* Region number. */\r
 670 \r
 671                         xMPUSettings->xRegion[ 0 ].ulRegionAttribute =\r
 672                                         ( portMPU_REGION_READ_WRITE ) | /* Read and write. */\r
 673                                         ( prvGetMPURegionSizeSetting( ulStackDepth * ( uint32_t ) sizeof( StackType_t ) ) ) |\r
 674                                         ( portMPU_REGION_CACHEABLE_BUFFERABLE ) |\r
 675                                         ( portMPU_REGION_ENABLE );\r
 676                 }\r
 677 \r
 678                 lIndex = 0;\r
 679 \r
 680                 for( ul = 1; ul <= portNUM_CONFIGURABLE_REGIONS; ul++ )\r
 681                 {\r
 682                         if( ( xRegions[ lIndex ] ).ulLengthInBytes > 0UL )\r
 683                         {\r
 684                                 /* Translate the generic region definition contained in\r
 685                                 xRegions into the CM3 specific MPU settings that are then\r
 686                                 stored in xMPUSettings. */\r
 687                                 xMPUSettings->xRegion[ ul ].ulRegionBaseAddress =\r
 688                                                 ( ( uint32_t ) xRegions[ lIndex ].pvBaseAddress ) |\r
 689                                                 ( portMPU_REGION_VALID ) |\r
 690                                                 ( portSTACK_REGION + ul ); /* Region number. */\r
 691 \r
 692                                 xMPUSettings->xRegion[ ul ].ulRegionAttribute =\r
 693                                                 ( prvGetMPURegionSizeSetting( xRegions[ lIndex ].ulLengthInBytes ) ) |\r
 694                                                 ( xRegions[ lIndex ].ulParameters ) |\r
 695                                                 ( portMPU_REGION_ENABLE );\r
 696                         }\r
 697                         else\r
 698                         {\r
 699                                 /* Invalidate the region. */\r
 700                                 xMPUSettings->xRegion[ ul ].ulRegionBaseAddress = ( portSTACK_REGION + ul ) | portMPU_REGION_VALID;\r
 701                                 xMPUSettings->xRegion[ ul ].ulRegionAttribute = 0UL;\r
 702                         }\r
 703 \r
 704                         lIndex++;\r
 705                 }\r
 706         }\r
 707 }\r
 708 /*-----------------------------------------------------------*/\r
 709 \r
 710 #if( configASSERT_DEFINED == 1 )\r
 711 \r
 712         void vPortValidateInterruptPriority( void )\r
 713         {\r
 714         uint32_t ulCurrentInterrupt;\r
 715         uint8_t ucCurrentPriority;\r
 716 \r
 717                 /* Obtain the number of the currently executing interrupt. */\r
 718                 __asm volatile( "mrs %0, ipsr" : "=r"( ulCurrentInterrupt ) );\r
 719 \r
 720                 /* Is the interrupt number a user defined interrupt? */\r
 721                 if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER )\r
 722                 {\r
 723                         /* Look up the interrupt's priority. */\r
 724                         ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ];\r
 725 \r
 726                         /* The following assertion will fail if a service routine (ISR) for\r
 727                         an interrupt that has been assigned a priority above\r
 728                         configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API\r
 729                         function.  ISR safe FreeRTOS API functions must *only* be called\r
 730                         from interrupts that have been assigned a priority at or below\r
 731                         configMAX_SYSCALL_INTERRUPT_PRIORITY.\r
 732 \r
 733                         Numerically low interrupt priority numbers represent logically high\r
 734                         interrupt priorities, therefore the priority of the interrupt must\r
 735                         be set to a value equal to or numerically *higher* than\r
 736                         configMAX_SYSCALL_INTERRUPT_PRIORITY.\r
 737 \r
 738                         Interrupts that use the FreeRTOS API must not be left at their\r
 739                         default priority of     zero as that is the highest possible priority,\r
 740                         which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY,\r
 741                         and     therefore also guaranteed to be invalid.\r
 742 \r
 743                         FreeRTOS maintains separate thread and ISR API functions to ensure\r
 744                         interrupt entry is as fast and simple as possible.\r
 745 \r
 746                         The following links provide detailed information:\r
 747                         http://www.freertos.org/RTOS-Cortex-M3-M4.html\r
 748                         http://www.freertos.org/FAQHelp.html */\r
 749                         configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );\r
 750                 }\r
 751 \r
 752                 /* Priority grouping:  The interrupt controller (NVIC) allows the bits\r
 753                 that define each interrupt's priority to be split between bits that\r
 754                 define the interrupt's pre-emption priority bits and bits that define\r
 755                 the interrupt's sub-priority.  For simplicity all bits must be defined\r
 756                 to be pre-emption priority bits.  The following assertion will fail if\r
 757                 this is not the case (if some bits represent a sub-priority).\r
 758 \r
 759                 If the application only uses CMSIS libraries for interrupt\r
 760                 configuration then the correct setting can be achieved on all Cortex-M\r
 761                 devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the\r
 762                 scheduler.  Note however that some vendor specific peripheral libraries\r
 763                 assume a non-zero priority group setting, in which cases using a value\r
 764                 of zero will result in unpredicable behaviour. */\r
 765                 configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );\r
 766         }\r
 767 \r
 768 #endif /* configASSERT_DEFINED */\r
 769 /*-----------------------------------------------------------*/\r
 770 \r
 771 \r