git.sur5r.net Git - freertos/blob - FreeRTOS/Source/portable/GCC/ARM_CM3_MPU/port.c

   1 /*\r
   2  * FreeRTOS Kernel V10.2.1\r
   3  * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\r
   4  *\r
   5  * Permission is hereby granted, free of charge, to any person obtaining a copy of\r
   6  * this software and associated documentation files (the "Software"), to deal in\r
   7  * the Software without restriction, including without limitation the rights to\r
   8  * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\r
   9  * the Software, and to permit persons to whom the Software is furnished to do so,\r
  10  * subject to the following conditions:\r
  11  *\r
  12  * The above copyright notice and this permission notice shall be included in all\r
  13  * copies or substantial portions of the Software.\r
  14  *\r
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\r
  17  * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\r
  18  * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r
  19  * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
  20  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
  21  *\r
  22  * http://www.FreeRTOS.org\r
  23  * http://aws.amazon.com/freertos\r
  24  *\r
  25  * 1 tab == 4 spaces!\r
  26  */\r
  27 \r
  28 /*-----------------------------------------------------------\r
  29  * Implementation of functions defined in portable.h for the ARM CM3 port.\r
  30  *----------------------------------------------------------*/\r
  31 \r
  32 /* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining\r
  33 all the API functions to use the MPU wrappers.  That should only be done when\r
  34 task.h is included from an application file. */\r
  35 #define MPU_WRAPPERS_INCLUDED_FROM_API_FILE\r
  36 \r
  37 /* Scheduler includes. */\r
  38 #include "FreeRTOS.h"\r
  39 #include "task.h"\r
  40 \r
  41 #undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE\r
  42 \r
  43 #ifndef configSYSTICK_CLOCK_HZ\r
  44         #define configSYSTICK_CLOCK_HZ configCPU_CLOCK_HZ\r
  45         /* Ensure the SysTick is clocked at the same frequency as the core. */\r
  46         #define portNVIC_SYSTICK_CLK    ( 1UL << 2UL )\r
  47 #else\r
  48         /* The way the SysTick is clocked is not modified in case it is not the same\r
  49         as the core. */\r
  50         #define portNVIC_SYSTICK_CLK    ( 0 )\r
  51 #endif\r
  52 \r
  53 /* Constants required to access and manipulate the NVIC. */\r
  54 #define portNVIC_SYSTICK_CTRL_REG                               ( * ( ( volatile uint32_t * ) 0xe000e010 ) )\r
  55 #define portNVIC_SYSTICK_LOAD_REG                               ( * ( ( volatile uint32_t * ) 0xe000e014 ) )\r
  56 #define portNVIC_SYSTICK_CURRENT_VALUE_REG              ( * ( ( volatile uint32_t * ) 0xe000e018 ) )\r
  57 #define portNVIC_SYSPRI2_REG                                    ( *     ( ( volatile uint32_t * ) 0xe000ed20 ) )\r
  58 #define portNVIC_SYSPRI1_REG                                    ( * ( ( volatile uint32_t * ) 0xe000ed1c ) )\r
  59 #define portNVIC_SYS_CTRL_STATE_REG                             ( * ( ( volatile uint32_t * ) 0xe000ed24 ) )\r
  60 #define portNVIC_MEM_FAULT_ENABLE                               ( 1UL << 16UL )\r
  61 \r
  62 /* Constants required to access and manipulate the MPU. */\r
  63 #define portMPU_TYPE_REG                                                ( * ( ( volatile uint32_t * ) 0xe000ed90 ) )\r
  64 #define portMPU_REGION_BASE_ADDRESS_REG                 ( * ( ( volatile uint32_t * ) 0xe000ed9C ) )\r
  65 #define portMPU_REGION_ATTRIBUTE_REG                    ( * ( ( volatile uint32_t * ) 0xe000edA0 ) )\r
  66 #define portMPU_CTRL_REG                                                ( * ( ( volatile uint32_t * ) 0xe000ed94 ) )\r
  67 #define portEXPECTED_MPU_TYPE_VALUE                             ( 8UL << 8UL ) /* 8 regions, unified. */\r
  68 #define portMPU_ENABLE                                                  ( 0x01UL )\r
  69 #define portMPU_BACKGROUND_ENABLE                               ( 1UL << 2UL )\r
  70 #define portPRIVILEGED_EXECUTION_START_ADDRESS  ( 0UL )\r
  71 #define portMPU_REGION_VALID                                    ( 0x10UL )\r
  72 #define portMPU_REGION_ENABLE                                   ( 0x01UL )\r
  73 #define portPERIPHERALS_START_ADDRESS                   0x40000000UL\r
  74 #define portPERIPHERALS_END_ADDRESS                             0x5FFFFFFFUL\r
  75 \r
  76 /* Constants required to access and manipulate the SysTick. */\r
  77 #define portNVIC_SYSTICK_INT                                    ( 0x00000002UL )\r
  78 #define portNVIC_SYSTICK_ENABLE                                 ( 0x00000001UL )\r
  79 #define portNVIC_PENDSV_PRI                                             ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL )\r
  80 #define portNVIC_SYSTICK_PRI                                    ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL )\r
  81 #define portNVIC_SVC_PRI                                                ( ( ( uint32_t ) configMAX_SYSCALL_INTERRUPT_PRIORITY - 1UL ) << 24UL )\r
  82 \r
  83 /* Constants required to set up the initial stack. */\r
  84 #define portINITIAL_XPSR                                                ( 0x01000000 )\r
  85 #define portINITIAL_CONTROL_IF_UNPRIVILEGED             ( 0x03 )\r
  86 #define portINITIAL_CONTROL_IF_PRIVILEGED               ( 0x02 )\r
  87 \r
  88 /* Constants required to check the validity of an interrupt priority. */\r
  89 #define portFIRST_USER_INTERRUPT_NUMBER         ( 16 )\r
  90 #define portNVIC_IP_REGISTERS_OFFSET_16         ( 0xE000E3F0 )\r
  91 #define portAIRCR_REG                                           ( * ( ( volatile uint32_t * ) 0xE000ED0C ) )\r
  92 #define portMAX_8_BIT_VALUE                                     ( ( uint8_t ) 0xff )\r
  93 #define portTOP_BIT_OF_BYTE                                     ( ( uint8_t ) 0x80 )\r
  94 #define portMAX_PRIGROUP_BITS                           ( ( uint8_t ) 7 )\r
  95 #define portPRIORITY_GROUP_MASK                         ( 0x07UL << 8UL )\r
  96 #define portPRIGROUP_SHIFT                                      ( 8UL )\r
  97 \r
  98 /* Offsets in the stack to the parameters when inside the SVC handler. */\r
  99 #define portOFFSET_TO_PC                                                ( 6 )\r
 100 \r
 101 /* For strict compliance with the Cortex-M spec the task start address should\r
 102 have bit-0 clear, as it is loaded into the PC on exit from an ISR. */\r
 103 #define portSTART_ADDRESS_MASK                          ( ( StackType_t ) 0xfffffffeUL )\r
 104 \r
 105 /*\r
 106  * Configure a number of standard MPU regions that are used by all tasks.\r
 107  */\r
 108 static void prvSetupMPU( void ) PRIVILEGED_FUNCTION;\r
 109 \r
 110 /*\r
 111  * Return the smallest MPU region size that a given number of bytes will fit\r
 112  * into.  The region size is returned as the value that should be programmed\r
 113  * into the region attribute register for that region.\r
 114  */\r
 115 static uint32_t prvGetMPURegionSizeSetting( uint32_t ulActualSizeInBytes ) PRIVILEGED_FUNCTION;\r
 116 \r
 117 /*\r
 118  * Setup the timer to generate the tick interrupts.  The implementation in this\r
 119  * file is weak to allow application writers to change the timer used to\r
 120  * generate the tick interrupt.\r
 121  */\r
 122 void vPortSetupTimerInterrupt( void );\r
 123 \r
 124 /*\r
 125  * Standard FreeRTOS exception handlers.\r
 126  */\r
 127 void xPortPendSVHandler( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;\r
 128 void xPortSysTickHandler( void )  __attribute__ ((optimize("3"))) PRIVILEGED_FUNCTION;\r
 129 void vPortSVCHandler( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;\r
 130 \r
 131 /*\r
 132  * Starts the scheduler by restoring the context of the first task to run.\r
 133  */\r
 134 static void prvRestoreContextOfFirstTask( void ) __attribute__(( naked )) PRIVILEGED_FUNCTION;\r
 135 \r
 136 /*\r
 137  * C portion of the SVC handler.  The SVC handler is split between an asm entry\r
 138  * and a C wrapper for simplicity of coding and maintenance.\r
 139  */\r
 140 static void prvSVCHandler( uint32_t *pulRegisters ) __attribute__(( noinline )) PRIVILEGED_FUNCTION;\r
 141 \r
 142 /**\r
 143  * @brief Checks whether or not the processor is privileged.\r
 144  *\r
 145  * @return 1 if the processor is already privileged, 0 otherwise.\r
 146  */\r
 147 BaseType_t xIsPrivileged( void ) __attribute__ (( naked ));\r
 148 \r
 149 /**\r
 150  * @brief Lowers the privilege level by setting the bit 0 of the CONTROL\r
 151  * register.\r
 152  *\r
 153  * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.\r
 154  *  Bit[0] = 0 --> The processor is running privileged\r
 155  *  Bit[0] = 1 --> The processor is running unprivileged.\r
 156  */\r
 157 void vResetPrivilege( void ) __attribute__ (( naked ));\r
 158 \r
 159 /**\r
 160  * @brief Calls the port specific code to raise the privilege.\r
 161  *\r
 162  * @return pdFALSE if privilege was raised, pdTRUE otherwise.\r
 163  */\r
 164 extern BaseType_t xPortRaisePrivilege( void );\r
 165 \r
 166 /**\r
 167  * @brief If xRunningPrivileged is not pdTRUE, calls the port specific\r
 168  * code to reset the privilege, otherwise does nothing.\r
 169  */\r
 170 extern void vPortResetPrivilege( BaseType_t xRunningPrivileged );\r
 171 /*-----------------------------------------------------------*/\r
 172 \r
 173 /* Each task maintains its own interrupt status in the critical nesting\r
 174 variable.  Note this is not saved as part of the task context as context\r
 175 switches can only occur when uxCriticalNesting is zero. */\r
 176 static UBaseType_t uxCriticalNesting = 0xaaaaaaaa;\r
 177 \r
 178 /*\r
 179  * Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure\r
 180  * FreeRTOS API functions are not called from interrupts that have been assigned\r
 181  * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY.\r
 182  */\r
 183 #if ( configASSERT_DEFINED == 1 )\r
 184          static uint8_t ucMaxSysCallPriority = 0;\r
 185          static uint32_t ulMaxPRIGROUPValue = 0;\r
 186          static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const volatile uint8_t * const ) portNVIC_IP_REGISTERS_OFFSET_16;\r
 187 #endif /* configASSERT_DEFINED */\r
 188 \r
 189 /*-----------------------------------------------------------*/\r
 190 \r
 191 /*\r
 192  * See header file for description.\r
 193  */\r
 194 StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters, BaseType_t xRunPrivileged )\r
 195 {\r
 196         /* Simulate the stack frame as it would be created by a context switch\r
 197         interrupt. */\r
 198         pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */\r
 199         *pxTopOfStack = portINITIAL_XPSR;       /* xPSR */\r
 200         pxTopOfStack--;\r
 201         *pxTopOfStack = ( ( StackType_t ) pxCode ) & portSTART_ADDRESS_MASK;    /* PC */\r
 202         pxTopOfStack--;\r
 203         *pxTopOfStack = 0;      /* LR */\r
 204         pxTopOfStack -= 5;      /* R12, R3, R2 and R1. */\r
 205         *pxTopOfStack = ( StackType_t ) pvParameters;   /* R0 */\r
 206         pxTopOfStack -= 9;      /* R11, R10, R9, R8, R7, R6, R5 and R4. */\r
 207 \r
 208         if( xRunPrivileged == pdTRUE )\r
 209         {\r
 210                 *pxTopOfStack = portINITIAL_CONTROL_IF_PRIVILEGED;\r
 211         }\r
 212         else\r
 213         {\r
 214                 *pxTopOfStack = portINITIAL_CONTROL_IF_UNPRIVILEGED;\r
 215         }\r
 216 \r
 217         return pxTopOfStack;\r
 218 }\r
 219 /*-----------------------------------------------------------*/\r
 220 \r
 221 void vPortSVCHandler( void )\r
 222 {\r
 223         /* Assumes psp was in use. */\r
 224         __asm volatile\r
 225         (\r
 226                 #ifndef USE_PROCESS_STACK       /* Code should not be required if a main() is using the process stack. */\r
 227                         "       tst lr, #4                                              \n"\r
 228                         "       ite eq                                                  \n"\r
 229                         "       mrseq r0, msp                                   \n"\r
 230                         "       mrsne r0, psp                                   \n"\r
 231                 #else\r
 232                         "       mrs r0, psp                                             \n"\r
 233                 #endif\r
 234                         "       b %0                                                    \n"\r
 235                         ::"i"(prvSVCHandler):"r0", "memory"\r
 236         );\r
 237 }\r
 238 /*-----------------------------------------------------------*/\r
 239 \r
 240 static void prvSVCHandler(      uint32_t *pulParam )\r
 241 {\r
 242 uint8_t ucSVCNumber;\r
 243 \r
 244         /* The stack contains: r0, r1, r2, r3, r12, r14, the return address and\r
 245         xPSR.  The first argument (r0) is pulParam[ 0 ]. */\r
 246         ucSVCNumber = ( ( uint8_t * ) pulParam[ portOFFSET_TO_PC ] )[ -2 ];\r
 247         switch( ucSVCNumber )\r
 248         {\r
 249                 case portSVC_START_SCHEDULER    :       portNVIC_SYSPRI1_REG |= portNVIC_SVC_PRI;\r
 250                                                                                         prvRestoreContextOfFirstTask();\r
 251                                                                                         break;\r
 252 \r
 253                 case portSVC_YIELD                              :       portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;\r
 254                                                                                         /* Barriers are normally not required\r
 255                                                                                         but do ensure the code is completely\r
 256                                                                                         within the specified behaviour for the\r
 257                                                                                         architecture. */\r
 258                                                                                         __asm volatile( "dsb" ::: "memory" );\r
 259                                                                                         __asm volatile( "isb" );\r
 260 \r
 261                                                                                         break;\r
 262 \r
 263                 case portSVC_RAISE_PRIVILEGE    :       __asm volatile\r
 264                                                                                         (\r
 265                                                                                                 "       mrs r1, control         \n" /* Obtain current control value. */\r
 266                                                                                                 "       bic r1, #1                      \n" /* Set privilege bit. */\r
 267                                                                                                 "       msr control, r1         \n" /* Write back new control value. */\r
 268                                                                                                 ::: "r1", "memory"\r
 269                                                                                         );\r
 270                                                                                         break;\r
 271 \r
 272                 default                                                 :       /* Unknown SVC call. */\r
 273                                                                                         break;\r
 274         }\r
 275 }\r
 276 /*-----------------------------------------------------------*/\r
 277 \r
 278 static void prvRestoreContextOfFirstTask( void )\r
 279 {\r
 280         __asm volatile\r
 281         (\r
 282                 "       ldr r0, =0xE000ED08                             \n" /* Use the NVIC offset register to locate the stack. */\r
 283                 "       ldr r0, [r0]                                    \n"\r
 284                 "       ldr r0, [r0]                                    \n"\r
 285                 "       msr msp, r0                                             \n" /* Set the msp back to the start of the stack. */\r
 286                 "       ldr     r3, pxCurrentTCBConst2          \n" /* Restore the context. */\r
 287                 "       ldr r1, [r3]                                    \n"\r
 288                 "       ldr r0, [r1]                                    \n" /* The first item in the TCB is the task top of stack. */\r
 289                 "       add r1, r1, #4                                  \n" /* Move onto the second item in the TCB... */\r
 290                 "       ldr r2, =0xe000ed9c                             \n" /* Region Base Address register. */\r
 291                 "       ldmia r1!, {r4-r11}                             \n" /* Read 4 sets of MPU registers. */\r
 292                 "       stmia r2!, {r4-r11}                             \n" /* Write 4 sets of MPU registers. */\r
 293                 "       ldmia r0!, {r3, r4-r11}                 \n" /* Pop the registers that are not automatically saved on exception entry. */\r
 294                 "       msr control, r3                                 \n"\r
 295                 "       msr psp, r0                                             \n" /* Restore the task stack pointer. */\r
 296                 "       mov r0, #0                                              \n"\r
 297                 "       msr     basepri, r0                                     \n"\r
 298                 "       ldr r14, =0xfffffffd                    \n" /* Load exec return code. */\r
 299                 "       bx r14                                                  \n"\r
 300                 "                                                                       \n"\r
 301                 "       .align 4                                                \n"\r
 302                 "pxCurrentTCBConst2: .word pxCurrentTCB \n"\r
 303         );\r
 304 }\r
 305 /*-----------------------------------------------------------*/\r
 306 \r
 307 /*\r
 308  * See header file for description.\r
 309  */\r
 310 BaseType_t xPortStartScheduler( void )\r
 311 {\r
 312         /* configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0.  See\r
 313         http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */\r
 314         configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) );\r
 315 \r
 316         #if( configASSERT_DEFINED == 1 )\r
 317         {\r
 318                 volatile uint32_t ulOriginalPriority;\r
 319                 volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER );\r
 320                 volatile uint8_t ucMaxPriorityValue;\r
 321 \r
 322                 /* Determine the maximum priority from which ISR safe FreeRTOS API\r
 323                 functions can be called.  ISR safe functions are those that end in\r
 324                 "FromISR".  FreeRTOS maintains separate thread and ISR API functions to\r
 325                 ensure interrupt entry is as fast and simple as possible.\r
 326 \r
 327                 Save the interrupt priority value that is about to be clobbered. */\r
 328                 ulOriginalPriority = *pucFirstUserPriorityRegister;\r
 329 \r
 330                 /* Determine the number of priority bits available.  First write to all\r
 331                 possible bits. */\r
 332                 *pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;\r
 333 \r
 334                 /* Read the value back to see how many bits stuck. */\r
 335                 ucMaxPriorityValue = *pucFirstUserPriorityRegister;\r
 336 \r
 337                 /* Use the same mask on the maximum system call priority. */\r
 338                 ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;\r
 339 \r
 340                 /* Calculate the maximum acceptable priority group value for the number\r
 341                 of bits read back. */\r
 342                 ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;\r
 343                 while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )\r
 344                 {\r
 345                         ulMaxPRIGROUPValue--;\r
 346                         ucMaxPriorityValue <<= ( uint8_t ) 0x01;\r
 347                 }\r
 348 \r
 349                 #ifdef __NVIC_PRIO_BITS\r
 350                 {\r
 351                         /* Check the CMSIS configuration that defines the number of\r
 352                         priority bits matches the number of priority bits actually queried\r
 353                         from the hardware. */\r
 354                         configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == __NVIC_PRIO_BITS );\r
 355                 }\r
 356                 #endif\r
 357 \r
 358                 #ifdef configPRIO_BITS\r
 359                 {\r
 360                         /* Check the FreeRTOS configuration that defines the number of\r
 361                         priority bits matches the number of priority bits actually queried\r
 362                         from the hardware. */\r
 363                         configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == configPRIO_BITS );\r
 364                 }\r
 365                 #endif\r
 366 \r
 367                 /* Shift the priority group value back to its position within the AIRCR\r
 368                 register. */\r
 369                 ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;\r
 370                 ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;\r
 371 \r
 372                 /* Restore the clobbered interrupt priority register to its original\r
 373                 value. */\r
 374                 *pucFirstUserPriorityRegister = ulOriginalPriority;\r
 375         }\r
 376         #endif /* conifgASSERT_DEFINED */\r
 377 \r
 378         /* Make PendSV and SysTick the same priority as the kernel, and the SVC\r
 379         handler higher priority so it can be used to exit a critical section (where\r
 380         lower priorities are masked). */\r
 381         portNVIC_SYSPRI2_REG |= portNVIC_PENDSV_PRI;\r
 382         portNVIC_SYSPRI2_REG |= portNVIC_SYSTICK_PRI;\r
 383 \r
 384         /* Configure the regions in the MPU that are common to all tasks. */\r
 385         prvSetupMPU();\r
 386 \r
 387         /* Start the timer that generates the tick ISR.  Interrupts are disabled\r
 388         here already. */\r
 389         vPortSetupTimerInterrupt();\r
 390 \r
 391         /* Initialise the critical nesting count ready for the first task. */\r
 392         uxCriticalNesting = 0;\r
 393 \r
 394         /* Start the first task. */\r
 395         __asm volatile(\r
 396                                         " ldr r0, =0xE000ED08   \n" /* Use the NVIC offset register to locate the stack. */\r
 397                                         " ldr r0, [r0]                  \n"\r
 398                                         " ldr r0, [r0]                  \n"\r
 399                                         " msr msp, r0                   \n" /* Set the msp back to the start of the stack. */\r
 400                                         " cpsie i                               \n" /* Globally enable interrupts. */\r
 401                                         " cpsie f                               \n"\r
 402                                         " dsb                                   \n"\r
 403                                         " isb                                   \n"\r
 404                                         " svc %0                                \n" /* System call to start first task. */\r
 405                                         " nop                                   \n"\r
 406                                         :: "i" (portSVC_START_SCHEDULER) : "memory" );\r
 407 \r
 408         /* Should not get here! */\r
 409         return 0;\r
 410 }\r
 411 /*-----------------------------------------------------------*/\r
 412 \r
 413 void vPortEndScheduler( void )\r
 414 {\r
 415         /* Not implemented in ports where there is nothing to return to.\r
 416         Artificially force an assert. */\r
 417         configASSERT( uxCriticalNesting == 1000UL );\r
 418 }\r
 419 /*-----------------------------------------------------------*/\r
 420 \r
 421 void vPortEnterCritical( void )\r
 422 {\r
 423 BaseType_t xRunningPrivileged = xPortRaisePrivilege();\r
 424 \r
 425         portDISABLE_INTERRUPTS();\r
 426         uxCriticalNesting++;\r
 427 \r
 428         vPortResetPrivilege( xRunningPrivileged );\r
 429 }\r
 430 /*-----------------------------------------------------------*/\r
 431 \r
 432 void vPortExitCritical( void )\r
 433 {\r
 434 BaseType_t xRunningPrivileged = xPortRaisePrivilege();\r
 435 \r
 436         configASSERT( uxCriticalNesting );\r
 437         uxCriticalNesting--;\r
 438         if( uxCriticalNesting == 0 )\r
 439         {\r
 440                 portENABLE_INTERRUPTS();\r
 441         }\r
 442         vPortResetPrivilege( xRunningPrivileged );\r
 443 }\r
 444 /*-----------------------------------------------------------*/\r
 445 \r
 446 void xPortPendSVHandler( void )\r
 447 {\r
 448         /* This is a naked function. */\r
 449 \r
 450         __asm volatile\r
 451         (\r
 452                 "       mrs r0, psp                                                     \n"\r
 453                 "                                                                               \n"\r
 454                 "       ldr     r3, pxCurrentTCBConst                   \n" /* Get the location of the current TCB. */\r
 455                 "       ldr     r2, [r3]                                                \n"\r
 456                 "                                                                               \n"\r
 457                 "       mrs r1, control                                         \n"\r
 458                 "       stmdb r0!, {r1, r4-r11}                         \n" /* Save the remaining registers. */\r
 459                 "       str r0, [r2]                                            \n" /* Save the new top of stack into the first member of the TCB. */\r
 460                 "                                                                               \n"\r
 461                 "       stmdb sp!, {r3, r14}                            \n"\r
 462                 "       mov r0, %0                                                      \n"\r
 463                 "       msr basepri, r0                                         \n"\r
 464                 "       dsb                                                                     \n"\r
 465                 "       isb                                                                     \n"\r
 466                 "       bl vTaskSwitchContext                           \n"\r
 467                 "       mov r0, #0                                                      \n"\r
 468                 "       msr basepri, r0                                         \n"\r
 469                 "       ldmia sp!, {r3, r14}                            \n"\r
 470                 "                                                                               \n"     /* Restore the context. */\r
 471                 "       ldr r1, [r3]                                            \n"\r
 472                 "       ldr r0, [r1]                                            \n" /* The first item in the TCB is the task top of stack. */\r
 473                 "       add r1, r1, #4                                          \n" /* Move onto the second item in the TCB... */\r
 474                 "       ldr r2, =0xe000ed9c                                     \n" /* Region Base Address register. */\r
 475                 "       ldmia r1!, {r4-r11}                                     \n" /* Read 4 sets of MPU registers. */\r
 476                 "       stmia r2!, {r4-r11}                                     \n" /* Write 4 sets of MPU registers. */\r
 477                 "       ldmia r0!, {r3, r4-r11}                         \n" /* Pop the registers that are not automatically saved on exception entry. */\r
 478                 "       msr control, r3                                         \n"\r
 479                 "                                                                               \n"\r
 480                 "       msr psp, r0                                                     \n"\r
 481                 "       bx r14                                                          \n"\r
 482                 "                                                                               \n"\r
 483                 "       .align 4                                                        \n"\r
 484                 "pxCurrentTCBConst: .word pxCurrentTCB  \n"\r
 485                 ::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY)\r
 486         );\r
 487 }\r
 488 /*-----------------------------------------------------------*/\r
 489 \r
 490 void xPortSysTickHandler( void )\r
 491 {\r
 492 uint32_t ulDummy;\r
 493 \r
 494         ulDummy = portSET_INTERRUPT_MASK_FROM_ISR();\r
 495         {\r
 496                 /* Increment the RTOS tick. */\r
 497                 if( xTaskIncrementTick() != pdFALSE )\r
 498                 {\r
 499                         /* Pend a context switch. */\r
 500                         portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;\r
 501                 }\r
 502         }\r
 503         portCLEAR_INTERRUPT_MASK_FROM_ISR( ulDummy );\r
 504 }\r
 505 /*-----------------------------------------------------------*/\r
 506 \r
 507 /*\r
 508  * Setup the systick timer to generate the tick interrupts at the required\r
 509  * frequency.\r
 510  */\r
 511 __attribute__(( weak )) void vPortSetupTimerInterrupt( void )\r
 512 {\r
 513         /* Stop and clear the SysTick. */\r
 514         portNVIC_SYSTICK_CTRL_REG = 0UL;\r
 515         portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;\r
 516 \r
 517         /* Configure SysTick to interrupt at the requested rate. */\r
 518         portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;\r
 519         portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK | portNVIC_SYSTICK_INT | portNVIC_SYSTICK_ENABLE );\r
 520 }\r
 521 /*-----------------------------------------------------------*/\r
 522 \r
 523 static void prvSetupMPU( void )\r
 524 {\r
 525 extern uint32_t __privileged_functions_end__[];\r
 526 extern uint32_t __FLASH_segment_start__[];\r
 527 extern uint32_t __FLASH_segment_end__[];\r
 528 extern uint32_t __privileged_data_start__[];\r
 529 extern uint32_t __privileged_data_end__[];\r
 530 \r
 531         /* Check the expected MPU is present. */\r
 532         if( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE )\r
 533         {\r
 534                 /* First setup the entire flash for unprivileged read only access. */\r
 535                 portMPU_REGION_BASE_ADDRESS_REG =       ( ( uint32_t ) __FLASH_segment_start__ ) | /* Base address. */\r
 536                                                                                         ( portMPU_REGION_VALID ) |\r
 537                                                                                         ( portUNPRIVILEGED_FLASH_REGION );\r
 538 \r
 539                 portMPU_REGION_ATTRIBUTE_REG =  ( portMPU_REGION_READ_ONLY ) |\r
 540                                                                                 ( portMPU_REGION_CACHEABLE_BUFFERABLE ) |\r
 541                                                                                 ( prvGetMPURegionSizeSetting( ( uint32_t ) __FLASH_segment_end__ - ( uint32_t ) __FLASH_segment_start__ ) ) |\r
 542                                                                                 ( portMPU_REGION_ENABLE );\r
 543 \r
 544                 /* Setup the first 16K for privileged only access (even though less\r
 545                 than 10K is actually being used).  This is where the kernel code is\r
 546                 placed. */\r
 547                 portMPU_REGION_BASE_ADDRESS_REG =       ( ( uint32_t ) __FLASH_segment_start__ ) | /* Base address. */\r
 548                                                                                         ( portMPU_REGION_VALID ) |\r
 549                                                                                         ( portPRIVILEGED_FLASH_REGION );\r
 550 \r
 551                 portMPU_REGION_ATTRIBUTE_REG =  ( portMPU_REGION_PRIVILEGED_READ_ONLY ) |\r
 552                                                                                 ( portMPU_REGION_CACHEABLE_BUFFERABLE ) |\r
 553                                                                                 ( prvGetMPURegionSizeSetting( ( uint32_t ) __privileged_functions_end__ - ( uint32_t ) __FLASH_segment_start__ ) ) |\r
 554                                                                                 ( portMPU_REGION_ENABLE );\r
 555 \r
 556                 /* Setup the privileged data RAM region.  This is where the kernel data\r
 557                 is placed. */\r
 558                 portMPU_REGION_BASE_ADDRESS_REG =       ( ( uint32_t ) __privileged_data_start__ ) | /* Base address. */\r
 559                                                                                         ( portMPU_REGION_VALID ) |\r
 560                                                                                         ( portPRIVILEGED_RAM_REGION );\r
 561 \r
 562                 portMPU_REGION_ATTRIBUTE_REG =  ( portMPU_REGION_PRIVILEGED_READ_WRITE ) |\r
 563                                                                                 ( portMPU_REGION_CACHEABLE_BUFFERABLE ) |\r
 564                                                                                 prvGetMPURegionSizeSetting( ( uint32_t ) __privileged_data_end__ - ( uint32_t ) __privileged_data_start__ ) |\r
 565                                                                                 ( portMPU_REGION_ENABLE );\r
 566 \r
 567                 /* By default allow everything to access the general peripherals.  The\r
 568                 system peripherals and registers are protected. */\r
 569                 portMPU_REGION_BASE_ADDRESS_REG =       ( portPERIPHERALS_START_ADDRESS ) |\r
 570                                                                                         ( portMPU_REGION_VALID ) |\r
 571                                                                                         ( portGENERAL_PERIPHERALS_REGION );\r
 572 \r
 573                 portMPU_REGION_ATTRIBUTE_REG =  ( portMPU_REGION_READ_WRITE | portMPU_REGION_EXECUTE_NEVER ) |\r
 574                                                                                 ( prvGetMPURegionSizeSetting( portPERIPHERALS_END_ADDRESS - portPERIPHERALS_START_ADDRESS ) ) |\r
 575                                                                                 ( portMPU_REGION_ENABLE );\r
 576 \r
 577                 /* Enable the memory fault exception. */\r
 578                 portNVIC_SYS_CTRL_STATE_REG |= portNVIC_MEM_FAULT_ENABLE;\r
 579 \r
 580                 /* Enable the MPU with the background region configured. */\r
 581                 portMPU_CTRL_REG |= ( portMPU_ENABLE | portMPU_BACKGROUND_ENABLE );\r
 582         }\r
 583 }\r
 584 /*-----------------------------------------------------------*/\r
 585 \r
 586 static uint32_t prvGetMPURegionSizeSetting( uint32_t ulActualSizeInBytes )\r
 587 {\r
 588 uint32_t ulRegionSize, ulReturnValue = 4;\r
 589 \r
 590         /* 32 is the smallest region size, 31 is the largest valid value for\r
 591         ulReturnValue. */\r
 592         for( ulRegionSize = 32UL; ulReturnValue < 31UL; ( ulRegionSize <<= 1UL ) )\r
 593         {\r
 594                 if( ulActualSizeInBytes <= ulRegionSize )\r
 595                 {\r
 596                         break;\r
 597                 }\r
 598                 else\r
 599                 {\r
 600                         ulReturnValue++;\r
 601                 }\r
 602         }\r
 603 \r
 604         /* Shift the code by one before returning so it can be written directly\r
 605         into the the correct bit position of the attribute register. */\r
 606         return ( ulReturnValue << 1UL );\r
 607 }\r
 608 /*-----------------------------------------------------------*/\r
 609 \r
 610 BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */\r
 611 {\r
 612         __asm volatile\r
 613         (\r
 614         "       mrs r0, control                                                 \n" /* r0 = CONTROL. */\r
 615         "       tst r0, #1                                                              \n" /* Perform r0 & 1 (bitwise AND) and update the conditions flag. */\r
 616         "       ite ne                                                                  \n"\r
 617         "       movne r0, #0                                                    \n" /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */\r
 618         "       moveq r0, #1                                                    \n" /* CONTROL[0]==0. Return true to indicate that the processor is privileged. */\r
 619         "       bx lr                                                                   \n" /* Return. */\r
 620         "                                                                                       \n"\r
 621         "       .align 4                                                                \n"\r
 622         ::: "r0", "memory"\r
 623         );\r
 624 }\r
 625 /*-----------------------------------------------------------*/\r
 626 \r
 627 void vResetPrivilege( void ) /* __attribute__ (( naked )) */\r
 628 {\r
 629         __asm volatile\r
 630         (\r
 631         "       mrs r0, control                                                 \n" /* r0 = CONTROL. */\r
 632         "       orr r0, #1                                                              \n" /* r0 = r0 | 1. */\r
 633         "       msr control, r0                                                 \n" /* CONTROL = r0. */\r
 634         "       bx lr                                                                   \n" /* Return to the caller. */\r
 635         :::"r0", "memory"\r
 636         );\r
 637 }\r
 638 /*-----------------------------------------------------------*/\r
 639 \r
 640 void vPortStoreTaskMPUSettings( xMPU_SETTINGS *xMPUSettings, const struct xMEMORY_REGION * const xRegions, StackType_t *pxBottomOfStack, uint32_t ulStackDepth )\r
 641 {\r
 642 extern uint32_t __SRAM_segment_start__[];\r
 643 extern uint32_t __SRAM_segment_end__[];\r
 644 extern uint32_t __privileged_data_start__[];\r
 645 extern uint32_t __privileged_data_end__[];\r
 646 int32_t lIndex;\r
 647 uint32_t ul;\r
 648 \r
 649         if( xRegions == NULL )\r
 650         {\r
 651                 /* No MPU regions are specified so allow access to all RAM. */\r
 652                 xMPUSettings->xRegion[ 0 ].ulRegionBaseAddress =\r
 653                                 ( ( uint32_t ) __SRAM_segment_start__ ) | /* Base address. */\r
 654                                 ( portMPU_REGION_VALID ) |\r
 655                                 ( portSTACK_REGION );\r
 656 \r
 657                 xMPUSettings->xRegion[ 0 ].ulRegionAttribute =\r
 658                                 ( portMPU_REGION_READ_WRITE ) |\r
 659                                 ( portMPU_REGION_CACHEABLE_BUFFERABLE ) |\r
 660                                 ( prvGetMPURegionSizeSetting( ( uint32_t ) __SRAM_segment_end__ - ( uint32_t ) __SRAM_segment_start__ ) ) |\r
 661                                 ( portMPU_REGION_ENABLE );\r
 662 \r
 663                 /* Re-instate the privileged only RAM region as xRegion[ 0 ] will have\r
 664                 just removed the privileged only parameters. */\r
 665                 xMPUSettings->xRegion[ 1 ].ulRegionBaseAddress =\r
 666                                 ( ( uint32_t ) __privileged_data_start__ ) | /* Base address. */\r
 667                                 ( portMPU_REGION_VALID ) |\r
 668                                 ( portSTACK_REGION + 1 );\r
 669 \r
 670                 xMPUSettings->xRegion[ 1 ].ulRegionAttribute =\r
 671                                 ( portMPU_REGION_PRIVILEGED_READ_WRITE ) |\r
 672                                 ( portMPU_REGION_CACHEABLE_BUFFERABLE ) |\r
 673                                 prvGetMPURegionSizeSetting( ( uint32_t ) __privileged_data_end__ - ( uint32_t ) __privileged_data_start__ ) |\r
 674                                 ( portMPU_REGION_ENABLE );\r
 675 \r
 676                 /* Invalidate all other regions. */\r
 677                 for( ul = 2; ul <= portNUM_CONFIGURABLE_REGIONS; ul++ )\r
 678                 {\r
 679                         xMPUSettings->xRegion[ ul ].ulRegionBaseAddress = ( portSTACK_REGION + ul ) | portMPU_REGION_VALID;\r
 680                         xMPUSettings->xRegion[ ul ].ulRegionAttribute = 0UL;\r
 681                 }\r
 682         }\r
 683         else\r
 684         {\r
 685                 /* This function is called automatically when the task is created - in\r
 686                 which case the stack region parameters will be valid.  At all other\r
 687                 times the stack parameters will not be valid and it is assumed that the\r
 688                 stack region has already been configured. */\r
 689                 if( ulStackDepth > 0 )\r
 690                 {\r
 691                         /* Define the region that allows access to the stack. */\r
 692                         xMPUSettings->xRegion[ 0 ].ulRegionBaseAddress =\r
 693                                         ( ( uint32_t ) pxBottomOfStack ) |\r
 694                                         ( portMPU_REGION_VALID ) |\r
 695                                         ( portSTACK_REGION ); /* Region number. */\r
 696 \r
 697                         xMPUSettings->xRegion[ 0 ].ulRegionAttribute =\r
 698                                         ( portMPU_REGION_READ_WRITE ) | /* Read and write. */\r
 699                                         ( prvGetMPURegionSizeSetting( ulStackDepth * ( uint32_t ) sizeof( StackType_t ) ) ) |\r
 700                                         ( portMPU_REGION_CACHEABLE_BUFFERABLE ) |\r
 701                                         ( portMPU_REGION_ENABLE );\r
 702                 }\r
 703 \r
 704                 lIndex = 0;\r
 705 \r
 706                 for( ul = 1; ul <= portNUM_CONFIGURABLE_REGIONS; ul++ )\r
 707                 {\r
 708                         if( ( xRegions[ lIndex ] ).ulLengthInBytes > 0UL )\r
 709                         {\r
 710                                 /* Translate the generic region definition contained in\r
 711                                 xRegions into the CM3 specific MPU settings that are then\r
 712                                 stored in xMPUSettings. */\r
 713                                 xMPUSettings->xRegion[ ul ].ulRegionBaseAddress =\r
 714                                                 ( ( uint32_t ) xRegions[ lIndex ].pvBaseAddress ) |\r
 715                                                 ( portMPU_REGION_VALID ) |\r
 716                                                 ( portSTACK_REGION + ul ); /* Region number. */\r
 717 \r
 718                                 xMPUSettings->xRegion[ ul ].ulRegionAttribute =\r
 719                                                 ( prvGetMPURegionSizeSetting( xRegions[ lIndex ].ulLengthInBytes ) ) |\r
 720                                                 ( xRegions[ lIndex ].ulParameters ) |\r
 721                                                 ( portMPU_REGION_ENABLE );\r
 722                         }\r
 723                         else\r
 724                         {\r
 725                                 /* Invalidate the region. */\r
 726                                 xMPUSettings->xRegion[ ul ].ulRegionBaseAddress = ( portSTACK_REGION + ul ) | portMPU_REGION_VALID;\r
 727                                 xMPUSettings->xRegion[ ul ].ulRegionAttribute = 0UL;\r
 728                         }\r
 729 \r
 730                         lIndex++;\r
 731                 }\r
 732         }\r
 733 }\r
 734 /*-----------------------------------------------------------*/\r
 735 \r
 736 #if( configASSERT_DEFINED == 1 )\r
 737 \r
 738         void vPortValidateInterruptPriority( void )\r
 739         {\r
 740         uint32_t ulCurrentInterrupt;\r
 741         uint8_t ucCurrentPriority;\r
 742 \r
 743                 /* Obtain the number of the currently executing interrupt. */\r
 744                 __asm volatile( "mrs %0, ipsr" : "=r"( ulCurrentInterrupt ) :: "memory" );\r
 745 \r
 746                 /* Is the interrupt number a user defined interrupt? */\r
 747                 if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER )\r
 748                 {\r
 749                         /* Look up the interrupt's priority. */\r
 750                         ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ];\r
 751 \r
 752                         /* The following assertion will fail if a service routine (ISR) for\r
 753                         an interrupt that has been assigned a priority above\r
 754                         configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API\r
 755                         function.  ISR safe FreeRTOS API functions must *only* be called\r
 756                         from interrupts that have been assigned a priority at or below\r
 757                         configMAX_SYSCALL_INTERRUPT_PRIORITY.\r
 758 \r
 759                         Numerically low interrupt priority numbers represent logically high\r
 760                         interrupt priorities, therefore the priority of the interrupt must\r
 761                         be set to a value equal to or numerically *higher* than\r
 762                         configMAX_SYSCALL_INTERRUPT_PRIORITY.\r
 763 \r
 764                         Interrupts that use the FreeRTOS API must not be left at their\r
 765                         default priority of     zero as that is the highest possible priority,\r
 766                         which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY,\r
 767                         and     therefore also guaranteed to be invalid.\r
 768 \r
 769                         FreeRTOS maintains separate thread and ISR API functions to ensure\r
 770                         interrupt entry is as fast and simple as possible.\r
 771 \r
 772                         The following links provide detailed information:\r
 773                         http://www.freertos.org/RTOS-Cortex-M3-M4.html\r
 774                         http://www.freertos.org/FAQHelp.html */\r
 775                         configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );\r
 776                 }\r
 777 \r
 778                 /* Priority grouping:  The interrupt controller (NVIC) allows the bits\r
 779                 that define each interrupt's priority to be split between bits that\r
 780                 define the interrupt's pre-emption priority bits and bits that define\r
 781                 the interrupt's sub-priority.  For simplicity all bits must be defined\r
 782                 to be pre-emption priority bits.  The following assertion will fail if\r
 783                 this is not the case (if some bits represent a sub-priority).\r
 784 \r
 785                 If the application only uses CMSIS libraries for interrupt\r
 786                 configuration then the correct setting can be achieved on all Cortex-M\r
 787                 devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the\r
 788                 scheduler.  Note however that some vendor specific peripheral libraries\r
 789                 assume a non-zero priority group setting, in which cases using a value\r
 790                 of zero will result in unpredicable behaviour. */\r
 791                 configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );\r
 792         }\r
 793 \r
 794 #endif /* configASSERT_DEFINED */\r
 795 /*-----------------------------------------------------------*/\r
 796 \r
 797 \r