git.sur5r.net Git - freertos/blob - FreeRTOS/Source/portable/GCC/ARM_CM3_MPU/port.c

   1 /*\r
   2  * FreeRTOS Kernel V10.0.0\r
   3  * Copyright (C) 2017 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\r
   4  *\r
   5  * Permission is hereby granted, free of charge, to any person obtaining a copy of\r
   6  * this software and associated documentation files (the "Software"), to deal in\r
   7  * the Software without restriction, including without limitation the rights to\r
   8  * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\r
   9  * the Software, and to permit persons to whom the Software is furnished to do so,\r
  10  * subject to the following conditions:\r
  11  *\r
  12  * The above copyright notice and this permission notice shall be included in all\r
  13  * copies or substantial portions of the Software. If you wish to use our Amazon\r
  14  * FreeRTOS name, please do so in a fair use way that does not cause confusion.\r
  15  *\r
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\r
  18  * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\r
  19  * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r
  20  * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
  21  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
  22  *\r
  23  * http://www.FreeRTOS.org\r
  24  * http://aws.amazon.com/freertos\r
  25  *\r
  26  * 1 tab == 4 spaces!\r
  27  */\r
  28 \r
  29 /*-----------------------------------------------------------\r
  30  * Implementation of functions defined in portable.h for the ARM CM3 port.\r
  31  *----------------------------------------------------------*/\r
  32 \r
  33 /* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining\r
  34 all the API functions to use the MPU wrappers.  That should only be done when\r
  35 task.h is included from an application file. */\r
  36 #define MPU_WRAPPERS_INCLUDED_FROM_API_FILE\r
  37 \r
  38 /* Scheduler includes. */\r
  39 #include "FreeRTOS.h"\r
  40 #include "task.h"\r
  41 \r
  42 #undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE\r
  43 \r
  44 #ifndef configSYSTICK_CLOCK_HZ\r
  45         #define configSYSTICK_CLOCK_HZ configCPU_CLOCK_HZ\r
  46         /* Ensure the SysTick is clocked at the same frequency as the core. */\r
  47         #define portNVIC_SYSTICK_CLK    ( 1UL << 2UL )\r
  48 #else\r
  49         /* The way the SysTick is clocked is not modified in case it is not the same\r
  50         as the core. */\r
  51         #define portNVIC_SYSTICK_CLK    ( 0 )\r
  52 #endif\r
  53 \r
  54 /* Constants required to access and manipulate the NVIC. */\r
  55 #define portNVIC_SYSTICK_CTRL_REG                               ( * ( ( volatile uint32_t * ) 0xe000e010 ) )\r
  56 #define portNVIC_SYSTICK_LOAD_REG                               ( * ( ( volatile uint32_t * ) 0xe000e014 ) )\r
  57 #define portNVIC_SYSTICK_CURRENT_VALUE_REG              ( * ( ( volatile uint32_t * ) 0xe000e018 ) )\r
  58 #define portNVIC_SYSPRI2_REG                                    ( *     ( ( volatile uint32_t * ) 0xe000ed20 ) )\r
  59 #define portNVIC_SYSPRI1_REG                                    ( * ( ( volatile uint32_t * ) 0xe000ed1c ) )\r
  60 #define portNVIC_SYS_CTRL_STATE_REG                             ( * ( ( volatile uint32_t * ) 0xe000ed24 ) )\r
  61 #define portNVIC_MEM_FAULT_ENABLE                               ( 1UL << 16UL )\r
  62 \r
  63 /* Constants required to access and manipulate the MPU. */\r
  64 #define portMPU_TYPE_REG                                                ( * ( ( volatile uint32_t * ) 0xe000ed90 ) )\r
  65 #define portMPU_REGION_BASE_ADDRESS_REG                 ( * ( ( volatile uint32_t * ) 0xe000ed9C ) )\r
  66 #define portMPU_REGION_ATTRIBUTE_REG                    ( * ( ( volatile uint32_t * ) 0xe000edA0 ) )\r
  67 #define portMPU_CTRL_REG                                                ( * ( ( volatile uint32_t * ) 0xe000ed94 ) )\r
  68 #define portEXPECTED_MPU_TYPE_VALUE                             ( 8UL << 8UL ) /* 8 regions, unified. */\r
  69 #define portMPU_ENABLE                                                  ( 0x01UL )\r
  70 #define portMPU_BACKGROUND_ENABLE                               ( 1UL << 2UL )\r
  71 #define portPRIVILEGED_EXECUTION_START_ADDRESS  ( 0UL )\r
  72 #define portMPU_REGION_VALID                                    ( 0x10UL )\r
  73 #define portMPU_REGION_ENABLE                                   ( 0x01UL )\r
  74 #define portPERIPHERALS_START_ADDRESS                   0x40000000UL\r
  75 #define portPERIPHERALS_END_ADDRESS                             0x5FFFFFFFUL\r
  76 \r
  77 /* Constants required to access and manipulate the SysTick. */\r
  78 #define portNVIC_SYSTICK_INT                                    ( 0x00000002UL )\r
  79 #define portNVIC_SYSTICK_ENABLE                                 ( 0x00000001UL )\r
  80 #define portNVIC_PENDSV_PRI                                             ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL )\r
  81 #define portNVIC_SYSTICK_PRI                                    ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL )\r
  82 #define portNVIC_SVC_PRI                                                ( ( ( uint32_t ) configMAX_SYSCALL_INTERRUPT_PRIORITY - 1UL ) << 24UL )\r
  83 \r
  84 /* Constants required to set up the initial stack. */\r
  85 #define portINITIAL_XPSR                                                ( 0x01000000 )\r
  86 #define portINITIAL_CONTROL_IF_UNPRIVILEGED             ( 0x03 )\r
  87 #define portINITIAL_CONTROL_IF_PRIVILEGED               ( 0x02 )\r
  88 \r
  89 /* Constants required to check the validity of an interrupt priority. */\r
  90 #define portFIRST_USER_INTERRUPT_NUMBER         ( 16 )\r
  91 #define portNVIC_IP_REGISTERS_OFFSET_16         ( 0xE000E3F0 )\r
  92 #define portAIRCR_REG                                           ( * ( ( volatile uint32_t * ) 0xE000ED0C ) )\r
  93 #define portMAX_8_BIT_VALUE                                     ( ( uint8_t ) 0xff )\r
  94 #define portTOP_BIT_OF_BYTE                                     ( ( uint8_t ) 0x80 )\r
  95 #define portMAX_PRIGROUP_BITS                           ( ( uint8_t ) 7 )\r
  96 #define portPRIORITY_GROUP_MASK                         ( 0x07UL << 8UL )\r
  97 #define portPRIGROUP_SHIFT                                      ( 8UL )\r
  98 \r
  99 /* Offsets in the stack to the parameters when inside the SVC handler. */\r
 100 #define portOFFSET_TO_PC                                                ( 6 )\r
 101 \r
 102 /* For strict compliance with the Cortex-M spec the task start address should\r
 103 have bit-0 clear, as it is loaded into the PC on exit from an ISR. */\r
 104 #define portSTART_ADDRESS_MASK                          ( ( StackType_t ) 0xfffffffeUL )\r
 105 \r
 106 /*\r
 107  * Configure a number of standard MPU regions that are used by all tasks.\r
 108  */\r
 109 static void prvSetupMPU( void ) PRIVILEGED_FUNCTION;\r
 110 \r
 111 /*\r
 112  * Return the smallest MPU region size that a given number of bytes will fit\r
 113  * into.  The region size is returned as the value that should be programmed\r
 114  * into the region attribute register for that region.\r
 115  */\r
 116 static uint32_t prvGetMPURegionSizeSetting( uint32_t ulActualSizeInBytes ) PRIVILEGED_FUNCTION;\r
 117 \r
 118 /*\r
 119  * Checks to see if being called from the context of an unprivileged task, and\r
 120  * if so raises the privilege level and returns false - otherwise does nothing\r
 121  * other than return true.\r
 122  */\r
 123 BaseType_t xPortRaisePrivilege( void ) __attribute__(( naked ));\r
 124 \r
 125 /*\r
 126  * Setup the timer to generate the tick interrupts.  The implementation in this\r
 127  * file is weak to allow application writers to change the timer used to\r
 128  * generate the tick interrupt.\r
 129  */\r
 130 void vPortSetupTimerInterrupt( void );\r
 131 \r
 132 /*\r
 133  * Standard FreeRTOS exception handlers.\r
 134  */\r
 135 void xPortPendSVHandler( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;\r
 136 void xPortSysTickHandler( void )  __attribute__ ((optimize("3"))) PRIVILEGED_FUNCTION;\r
 137 void vPortSVCHandler( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;\r
 138 \r
 139 /*\r
 140  * Starts the scheduler by restoring the context of the first task to run.\r
 141  */\r
 142 static void prvRestoreContextOfFirstTask( void ) __attribute__(( naked )) PRIVILEGED_FUNCTION;\r
 143 \r
 144 /*\r
 145  * C portion of the SVC handler.  The SVC handler is split between an asm entry\r
 146  * and a C wrapper for simplicity of coding and maintenance.\r
 147  */\r
 148 static void prvSVCHandler( uint32_t *pulRegisters ) __attribute__(( noinline )) PRIVILEGED_FUNCTION;\r
 149 \r
 150 /*-----------------------------------------------------------*/\r
 151 \r
 152 /* Each task maintains its own interrupt status in the critical nesting\r
 153 variable.  Note this is not saved as part of the task context as context\r
 154 switches can only occur when uxCriticalNesting is zero. */\r
 155 static UBaseType_t uxCriticalNesting = 0xaaaaaaaa;\r
 156 \r
 157 /*\r
 158  * Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure\r
 159  * FreeRTOS API functions are not called from interrupts that have been assigned\r
 160  * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY.\r
 161  */\r
 162 #if ( configASSERT_DEFINED == 1 )\r
 163          static uint8_t ucMaxSysCallPriority = 0;\r
 164          static uint32_t ulMaxPRIGROUPValue = 0;\r
 165          static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const volatile uint8_t * const ) portNVIC_IP_REGISTERS_OFFSET_16;\r
 166 #endif /* configASSERT_DEFINED */\r
 167 \r
 168 /*-----------------------------------------------------------*/\r
 169 \r
 170 /*\r
 171  * See header file for description.\r
 172  */\r
 173 StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters, BaseType_t xRunPrivileged )\r
 174 {\r
 175         /* Simulate the stack frame as it would be created by a context switch\r
 176         interrupt. */\r
 177         pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */\r
 178         *pxTopOfStack = portINITIAL_XPSR;       /* xPSR */\r
 179         pxTopOfStack--;\r
 180         *pxTopOfStack = ( ( StackType_t ) pxCode ) & portSTART_ADDRESS_MASK;    /* PC */\r
 181         pxTopOfStack--;\r
 182         *pxTopOfStack = 0;      /* LR */\r
 183         pxTopOfStack -= 5;      /* R12, R3, R2 and R1. */\r
 184         *pxTopOfStack = ( StackType_t ) pvParameters;   /* R0 */\r
 185         pxTopOfStack -= 9;      /* R11, R10, R9, R8, R7, R6, R5 and R4. */\r
 186 \r
 187         if( xRunPrivileged == pdTRUE )\r
 188         {\r
 189                 *pxTopOfStack = portINITIAL_CONTROL_IF_PRIVILEGED;\r
 190         }\r
 191         else\r
 192         {\r
 193                 *pxTopOfStack = portINITIAL_CONTROL_IF_UNPRIVILEGED;\r
 194         }\r
 195 \r
 196         return pxTopOfStack;\r
 197 }\r
 198 /*-----------------------------------------------------------*/\r
 199 \r
 200 void vPortSVCHandler( void )\r
 201 {\r
 202         /* Assumes psp was in use. */\r
 203         __asm volatile\r
 204         (\r
 205                 #ifndef USE_PROCESS_STACK       /* Code should not be required if a main() is using the process stack. */\r
 206                         "       tst lr, #4                                              \n"\r
 207                         "       ite eq                                                  \n"\r
 208                         "       mrseq r0, msp                                   \n"\r
 209                         "       mrsne r0, psp                                   \n"\r
 210                 #else\r
 211                         "       mrs r0, psp                                             \n"\r
 212                 #endif\r
 213                         "       b %0                                                    \n"\r
 214                         ::"i"(prvSVCHandler):"r0", "memory"\r
 215         );\r
 216 }\r
 217 /*-----------------------------------------------------------*/\r
 218 \r
 219 static void prvSVCHandler(      uint32_t *pulParam )\r
 220 {\r
 221 uint8_t ucSVCNumber;\r
 222 \r
 223         /* The stack contains: r0, r1, r2, r3, r12, r14, the return address and\r
 224         xPSR.  The first argument (r0) is pulParam[ 0 ]. */\r
 225         ucSVCNumber = ( ( uint8_t * ) pulParam[ portOFFSET_TO_PC ] )[ -2 ];\r
 226         switch( ucSVCNumber )\r
 227         {\r
 228                 case portSVC_START_SCHEDULER    :       portNVIC_SYSPRI1_REG |= portNVIC_SVC_PRI;\r
 229                                                                                         prvRestoreContextOfFirstTask();\r
 230                                                                                         break;\r
 231 \r
 232                 case portSVC_YIELD                              :       portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;\r
 233                                                                                         /* Barriers are normally not required\r
 234                                                                                         but do ensure the code is completely\r
 235                                                                                         within the specified behaviour for the\r
 236                                                                                         architecture. */\r
 237                                                                                         __asm volatile( "dsb" ::: "memory" );\r
 238                                                                                         __asm volatile( "isb" );\r
 239 \r
 240                                                                                         break;\r
 241 \r
 242                 case portSVC_RAISE_PRIVILEGE    :       __asm volatile\r
 243                                                                                         (\r
 244                                                                                                 "       mrs r1, control         \n" /* Obtain current control value. */\r
 245                                                                                                 "       bic r1, #1                      \n" /* Set privilege bit. */\r
 246                                                                                                 "       msr control, r1         \n" /* Write back new control value. */\r
 247                                                                                                 ::: "r1", "memory"\r
 248                                                                                         );\r
 249                                                                                         break;\r
 250 \r
 251                 default                                                 :       /* Unknown SVC call. */\r
 252                                                                                         break;\r
 253         }\r
 254 }\r
 255 /*-----------------------------------------------------------*/\r
 256 \r
 257 static void prvRestoreContextOfFirstTask( void )\r
 258 {\r
 259         __asm volatile\r
 260         (\r
 261                 "       ldr r0, =0xE000ED08                             \n" /* Use the NVIC offset register to locate the stack. */\r
 262                 "       ldr r0, [r0]                                    \n"\r
 263                 "       ldr r0, [r0]                                    \n"\r
 264                 "       msr msp, r0                                             \n" /* Set the msp back to the start of the stack. */\r
 265                 "       ldr     r3, pxCurrentTCBConst2          \n" /* Restore the context. */\r
 266                 "       ldr r1, [r3]                                    \n"\r
 267                 "       ldr r0, [r1]                                    \n" /* The first item in the TCB is the task top of stack. */\r
 268                 "       add r1, r1, #4                                  \n" /* Move onto the second item in the TCB... */\r
 269                 "       ldr r2, =0xe000ed9c                             \n" /* Region Base Address register. */\r
 270                 "       ldmia r1!, {r4-r11}                             \n" /* Read 4 sets of MPU registers. */\r
 271                 "       stmia r2!, {r4-r11}                             \n" /* Write 4 sets of MPU registers. */\r
 272                 "       ldmia r0!, {r3, r4-r11}                 \n" /* Pop the registers that are not automatically saved on exception entry. */\r
 273                 "       msr control, r3                                 \n"\r
 274                 "       msr psp, r0                                             \n" /* Restore the task stack pointer. */\r
 275                 "       mov r0, #0                                              \n"\r
 276                 "       msr     basepri, r0                                     \n"\r
 277                 "       ldr r14, =0xfffffffd                    \n" /* Load exec return code. */\r
 278                 "       bx r14                                                  \n"\r
 279                 "                                                                       \n"\r
 280                 "       .align 4                                                \n"\r
 281                 "pxCurrentTCBConst2: .word pxCurrentTCB \n"\r
 282         );\r
 283 }\r
 284 /*-----------------------------------------------------------*/\r
 285 \r
 286 /*\r
 287  * See header file for description.\r
 288  */\r
 289 BaseType_t xPortStartScheduler( void )\r
 290 {\r
 291         /* configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0.  See\r
 292         http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */\r
 293         configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) );\r
 294 \r
 295         #if( configASSERT_DEFINED == 1 )\r
 296         {\r
 297                 volatile uint32_t ulOriginalPriority;\r
 298                 volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER );\r
 299                 volatile uint8_t ucMaxPriorityValue;\r
 300 \r
 301                 /* Determine the maximum priority from which ISR safe FreeRTOS API\r
 302                 functions can be called.  ISR safe functions are those that end in\r
 303                 "FromISR".  FreeRTOS maintains separate thread and ISR API functions to\r
 304                 ensure interrupt entry is as fast and simple as possible.\r
 305 \r
 306                 Save the interrupt priority value that is about to be clobbered. */\r
 307                 ulOriginalPriority = *pucFirstUserPriorityRegister;\r
 308 \r
 309                 /* Determine the number of priority bits available.  First write to all\r
 310                 possible bits. */\r
 311                 *pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;\r
 312 \r
 313                 /* Read the value back to see how many bits stuck. */\r
 314                 ucMaxPriorityValue = *pucFirstUserPriorityRegister;\r
 315 \r
 316                 /* Use the same mask on the maximum system call priority. */\r
 317                 ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;\r
 318 \r
 319                 /* Calculate the maximum acceptable priority group value for the number\r
 320                 of bits read back. */\r
 321                 ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;\r
 322                 while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )\r
 323                 {\r
 324                         ulMaxPRIGROUPValue--;\r
 325                         ucMaxPriorityValue <<= ( uint8_t ) 0x01;\r
 326                 }\r
 327 \r
 328                 #ifdef __NVIC_PRIO_BITS\r
 329                 {\r
 330                         /* Check the CMSIS configuration that defines the number of\r
 331                         priority bits matches the number of priority bits actually queried\r
 332                         from the hardware. */\r
 333                         configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == __NVIC_PRIO_BITS );\r
 334                 }\r
 335                 #endif\r
 336 \r
 337                 #ifdef configPRIO_BITS\r
 338                 {\r
 339                         /* Check the FreeRTOS configuration that defines the number of\r
 340                         priority bits matches the number of priority bits actually queried\r
 341                         from the hardware. */\r
 342                         configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == configPRIO_BITS );\r
 343                 }\r
 344                 #endif\r
 345 \r
 346                 /* Shift the priority group value back to its position within the AIRCR\r
 347                 register. */\r
 348                 ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;\r
 349                 ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;\r
 350 \r
 351                 /* Restore the clobbered interrupt priority register to its original\r
 352                 value. */\r
 353                 *pucFirstUserPriorityRegister = ulOriginalPriority;\r
 354         }\r
 355         #endif /* conifgASSERT_DEFINED */\r
 356 \r
 357         /* Make PendSV and SysTick the same priority as the kernel, and the SVC\r
 358         handler higher priority so it can be used to exit a critical section (where\r
 359         lower priorities are masked). */\r
 360         portNVIC_SYSPRI2_REG |= portNVIC_PENDSV_PRI;\r
 361         portNVIC_SYSPRI2_REG |= portNVIC_SYSTICK_PRI;\r
 362 \r
 363         /* Configure the regions in the MPU that are common to all tasks. */\r
 364         prvSetupMPU();\r
 365 \r
 366         /* Start the timer that generates the tick ISR.  Interrupts are disabled\r
 367         here already. */\r
 368         vPortSetupTimerInterrupt();\r
 369 \r
 370         /* Initialise the critical nesting count ready for the first task. */\r
 371         uxCriticalNesting = 0;\r
 372 \r
 373         /* Start the first task. */\r
 374         __asm volatile(\r
 375                                         " ldr r0, =0xE000ED08   \n" /* Use the NVIC offset register to locate the stack. */\r
 376                                         " ldr r0, [r0]                  \n"\r
 377                                         " ldr r0, [r0]                  \n"\r
 378                                         " msr msp, r0                   \n" /* Set the msp back to the start of the stack. */\r
 379                                         " cpsie i                               \n" /* Globally enable interrupts. */\r
 380                                         " cpsie f                               \n"\r
 381                                         " dsb                                   \n"\r
 382                                         " isb                                   \n"\r
 383                                         " svc %0                                \n" /* System call to start first task. */\r
 384                                         " nop                                   \n"\r
 385                                         :: "i" (portSVC_START_SCHEDULER) : "memory" );\r
 386 \r
 387         /* Should not get here! */\r
 388         return 0;\r
 389 }\r
 390 /*-----------------------------------------------------------*/\r
 391 \r
 392 void vPortEndScheduler( void )\r
 393 {\r
 394         /* Not implemented in ports where there is nothing to return to.\r
 395         Artificially force an assert. */\r
 396         configASSERT( uxCriticalNesting == 1000UL );\r
 397 }\r
 398 /*-----------------------------------------------------------*/\r
 399 \r
 400 void vPortEnterCritical( void )\r
 401 {\r
 402 BaseType_t xRunningPrivileged = xPortRaisePrivilege();\r
 403 \r
 404         portDISABLE_INTERRUPTS();\r
 405         uxCriticalNesting++;\r
 406 \r
 407         vPortResetPrivilege( xRunningPrivileged );\r
 408 }\r
 409 /*-----------------------------------------------------------*/\r
 410 \r
 411 void vPortExitCritical( void )\r
 412 {\r
 413 BaseType_t xRunningPrivileged = xPortRaisePrivilege();\r
 414 \r
 415         configASSERT( uxCriticalNesting );\r
 416         uxCriticalNesting--;\r
 417         if( uxCriticalNesting == 0 )\r
 418         {\r
 419                 portENABLE_INTERRUPTS();\r
 420         }\r
 421         vPortResetPrivilege( xRunningPrivileged );\r
 422 }\r
 423 /*-----------------------------------------------------------*/\r
 424 \r
 425 void xPortPendSVHandler( void )\r
 426 {\r
 427         /* This is a naked function. */\r
 428 \r
 429         __asm volatile\r
 430         (\r
 431                 "       mrs r0, psp                                                     \n"\r
 432                 "                                                                               \n"\r
 433                 "       ldr     r3, pxCurrentTCBConst                   \n" /* Get the location of the current TCB. */\r
 434                 "       ldr     r2, [r3]                                                \n"\r
 435                 "                                                                               \n"\r
 436                 "       mrs r1, control                                         \n"\r
 437                 "       stmdb r0!, {r1, r4-r11}                         \n" /* Save the remaining registers. */\r
 438                 "       str r0, [r2]                                            \n" /* Save the new top of stack into the first member of the TCB. */\r
 439                 "                                                                               \n"\r
 440                 "       stmdb sp!, {r3, r14}                            \n"\r
 441                 "       mov r0, %0                                                      \n"\r
 442                 "       msr basepri, r0                                         \n"\r
 443                 "       dsb                                                                     \n"\r
 444                 "       isb                                                                     \n"\r
 445                 "       bl vTaskSwitchContext                           \n"\r
 446                 "       mov r0, #0                                                      \n"\r
 447                 "       msr basepri, r0                                         \n"\r
 448                 "       ldmia sp!, {r3, r14}                            \n"\r
 449                 "                                                                               \n"     /* Restore the context. */\r
 450                 "       ldr r1, [r3]                                            \n"\r
 451                 "       ldr r0, [r1]                                            \n" /* The first item in the TCB is the task top of stack. */\r
 452                 "       add r1, r1, #4                                          \n" /* Move onto the second item in the TCB... */\r
 453                 "       ldr r2, =0xe000ed9c                                     \n" /* Region Base Address register. */\r
 454                 "       ldmia r1!, {r4-r11}                                     \n" /* Read 4 sets of MPU registers. */\r
 455                 "       stmia r2!, {r4-r11}                                     \n" /* Write 4 sets of MPU registers. */\r
 456                 "       ldmia r0!, {r3, r4-r11}                         \n" /* Pop the registers that are not automatically saved on exception entry. */\r
 457                 "       msr control, r3                                         \n"\r
 458                 "                                                                               \n"\r
 459                 "       msr psp, r0                                                     \n"\r
 460                 "       bx r14                                                          \n"\r
 461                 "                                                                               \n"\r
 462                 "       .align 4                                                        \n"\r
 463                 "pxCurrentTCBConst: .word pxCurrentTCB  \n"\r
 464                 ::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY)\r
 465         );\r
 466 }\r
 467 /*-----------------------------------------------------------*/\r
 468 \r
 469 void xPortSysTickHandler( void )\r
 470 {\r
 471 uint32_t ulDummy;\r
 472 \r
 473         ulDummy = portSET_INTERRUPT_MASK_FROM_ISR();\r
 474         {\r
 475                 /* Increment the RTOS tick. */\r
 476                 if( xTaskIncrementTick() != pdFALSE )\r
 477                 {\r
 478                         /* Pend a context switch. */\r
 479                         portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;\r
 480                 }\r
 481         }\r
 482         portCLEAR_INTERRUPT_MASK_FROM_ISR( ulDummy );\r
 483 }\r
 484 /*-----------------------------------------------------------*/\r
 485 \r
 486 /*\r
 487  * Setup the systick timer to generate the tick interrupts at the required\r
 488  * frequency.\r
 489  */\r
 490 __attribute__(( weak )) void vPortSetupTimerInterrupt( void )\r
 491 {\r
 492         /* Stop and clear the SysTick. */\r
 493         portNVIC_SYSTICK_CTRL_REG = 0UL;\r
 494         portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;\r
 495 \r
 496         /* Configure SysTick to interrupt at the requested rate. */\r
 497         portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;\r
 498         portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK | portNVIC_SYSTICK_INT | portNVIC_SYSTICK_ENABLE );\r
 499 }\r
 500 /*-----------------------------------------------------------*/\r
 501 \r
 502 static void prvSetupMPU( void )\r
 503 {\r
 504 extern uint32_t __privileged_functions_end__[];\r
 505 extern uint32_t __FLASH_segment_start__[];\r
 506 extern uint32_t __FLASH_segment_end__[];\r
 507 extern uint32_t __privileged_data_start__[];\r
 508 extern uint32_t __privileged_data_end__[];\r
 509 \r
 510         /* Check the expected MPU is present. */\r
 511         if( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE )\r
 512         {\r
 513                 /* First setup the entire flash for unprivileged read only access. */\r
 514                 portMPU_REGION_BASE_ADDRESS_REG =       ( ( uint32_t ) __FLASH_segment_start__ ) | /* Base address. */\r
 515                                                                                         ( portMPU_REGION_VALID ) |\r
 516                                                                                         ( portUNPRIVILEGED_FLASH_REGION );\r
 517 \r
 518                 portMPU_REGION_ATTRIBUTE_REG =  ( portMPU_REGION_READ_ONLY ) |\r
 519                                                                                 ( portMPU_REGION_CACHEABLE_BUFFERABLE ) |\r
 520                                                                                 ( prvGetMPURegionSizeSetting( ( uint32_t ) __FLASH_segment_end__ - ( uint32_t ) __FLASH_segment_start__ ) ) |\r
 521                                                                                 ( portMPU_REGION_ENABLE );\r
 522 \r
 523                 /* Setup the first 16K for privileged only access (even though less\r
 524                 than 10K is actually being used).  This is where the kernel code is\r
 525                 placed. */\r
 526                 portMPU_REGION_BASE_ADDRESS_REG =       ( ( uint32_t ) __FLASH_segment_start__ ) | /* Base address. */\r
 527                                                                                         ( portMPU_REGION_VALID ) |\r
 528                                                                                         ( portPRIVILEGED_FLASH_REGION );\r
 529 \r
 530                 portMPU_REGION_ATTRIBUTE_REG =  ( portMPU_REGION_PRIVILEGED_READ_ONLY ) |\r
 531                                                                                 ( portMPU_REGION_CACHEABLE_BUFFERABLE ) |\r
 532                                                                                 ( prvGetMPURegionSizeSetting( ( uint32_t ) __privileged_functions_end__ - ( uint32_t ) __FLASH_segment_start__ ) ) |\r
 533                                                                                 ( portMPU_REGION_ENABLE );\r
 534 \r
 535                 /* Setup the privileged data RAM region.  This is where the kernel data\r
 536                 is placed. */\r
 537                 portMPU_REGION_BASE_ADDRESS_REG =       ( ( uint32_t ) __privileged_data_start__ ) | /* Base address. */\r
 538                                                                                         ( portMPU_REGION_VALID ) |\r
 539                                                                                         ( portPRIVILEGED_RAM_REGION );\r
 540 \r
 541                 portMPU_REGION_ATTRIBUTE_REG =  ( portMPU_REGION_PRIVILEGED_READ_WRITE ) |\r
 542                                                                                 ( portMPU_REGION_CACHEABLE_BUFFERABLE ) |\r
 543                                                                                 prvGetMPURegionSizeSetting( ( uint32_t ) __privileged_data_end__ - ( uint32_t ) __privileged_data_start__ ) |\r
 544                                                                                 ( portMPU_REGION_ENABLE );\r
 545 \r
 546                 /* By default allow everything to access the general peripherals.  The\r
 547                 system peripherals and registers are protected. */\r
 548                 portMPU_REGION_BASE_ADDRESS_REG =       ( portPERIPHERALS_START_ADDRESS ) |\r
 549                                                                                         ( portMPU_REGION_VALID ) |\r
 550                                                                                         ( portGENERAL_PERIPHERALS_REGION );\r
 551 \r
 552                 portMPU_REGION_ATTRIBUTE_REG =  ( portMPU_REGION_READ_WRITE | portMPU_REGION_EXECUTE_NEVER ) |\r
 553                                                                                 ( prvGetMPURegionSizeSetting( portPERIPHERALS_END_ADDRESS - portPERIPHERALS_START_ADDRESS ) ) |\r
 554                                                                                 ( portMPU_REGION_ENABLE );\r
 555 \r
 556                 /* Enable the memory fault exception. */\r
 557                 portNVIC_SYS_CTRL_STATE_REG |= portNVIC_MEM_FAULT_ENABLE;\r
 558 \r
 559                 /* Enable the MPU with the background region configured. */\r
 560                 portMPU_CTRL_REG |= ( portMPU_ENABLE | portMPU_BACKGROUND_ENABLE );\r
 561         }\r
 562 }\r
 563 /*-----------------------------------------------------------*/\r
 564 \r
 565 static uint32_t prvGetMPURegionSizeSetting( uint32_t ulActualSizeInBytes )\r
 566 {\r
 567 uint32_t ulRegionSize, ulReturnValue = 4;\r
 568 \r
 569         /* 32 is the smallest region size, 31 is the largest valid value for\r
 570         ulReturnValue. */\r
 571         for( ulRegionSize = 32UL; ulReturnValue < 31UL; ( ulRegionSize <<= 1UL ) )\r
 572         {\r
 573                 if( ulActualSizeInBytes <= ulRegionSize )\r
 574                 {\r
 575                         break;\r
 576                 }\r
 577                 else\r
 578                 {\r
 579                         ulReturnValue++;\r
 580                 }\r
 581         }\r
 582 \r
 583         /* Shift the code by one before returning so it can be written directly\r
 584         into the the correct bit position of the attribute register. */\r
 585         return ( ulReturnValue << 1UL );\r
 586 }\r
 587 /*-----------------------------------------------------------*/\r
 588 \r
 589 BaseType_t xPortRaisePrivilege( void )\r
 590 {\r
 591         __asm volatile\r
 592         (\r
 593                 "       mrs r0, control                                         \n"\r
 594                 "       tst r0, #1                                                      \n" /* Is the task running privileged? */\r
 595                 "       itte ne                                                         \n"\r
 596                 "       movne r0, #0                                            \n" /* CONTROL[0]!=0, return false. */\r
 597                 "       svcne %0                                                        \n" /* Switch to privileged. */\r
 598                 "       moveq r0, #1                                            \n" /* CONTROL[0]==0, return true. */\r
 599                 "       bx lr                                                           \n"\r
 600                 :: "i" (portSVC_RAISE_PRIVILEGE) : "r0", "memory"\r
 601         );\r
 602 \r
 603         return 0;\r
 604 }\r
 605 /*-----------------------------------------------------------*/\r
 606 \r
 607 void vPortStoreTaskMPUSettings( xMPU_SETTINGS *xMPUSettings, const struct xMEMORY_REGION * const xRegions, StackType_t *pxBottomOfStack, uint32_t ulStackDepth )\r
 608 {\r
 609 extern uint32_t __SRAM_segment_start__[];\r
 610 extern uint32_t __SRAM_segment_end__[];\r
 611 extern uint32_t __privileged_data_start__[];\r
 612 extern uint32_t __privileged_data_end__[];\r
 613 int32_t lIndex;\r
 614 uint32_t ul;\r
 615 \r
 616         if( xRegions == NULL )\r
 617         {\r
 618                 /* No MPU regions are specified so allow access to all RAM. */\r
 619                 xMPUSettings->xRegion[ 0 ].ulRegionBaseAddress =\r
 620                                 ( ( uint32_t ) __SRAM_segment_start__ ) | /* Base address. */\r
 621                                 ( portMPU_REGION_VALID ) |\r
 622                                 ( portSTACK_REGION );\r
 623 \r
 624                 xMPUSettings->xRegion[ 0 ].ulRegionAttribute =\r
 625                                 ( portMPU_REGION_READ_WRITE ) |\r
 626                                 ( portMPU_REGION_CACHEABLE_BUFFERABLE ) |\r
 627                                 ( prvGetMPURegionSizeSetting( ( uint32_t ) __SRAM_segment_end__ - ( uint32_t ) __SRAM_segment_start__ ) ) |\r
 628                                 ( portMPU_REGION_ENABLE );\r
 629 \r
 630                 /* Re-instate the privileged only RAM region as xRegion[ 0 ] will have\r
 631                 just removed the privileged only parameters. */\r
 632                 xMPUSettings->xRegion[ 1 ].ulRegionBaseAddress =\r
 633                                 ( ( uint32_t ) __privileged_data_start__ ) | /* Base address. */\r
 634                                 ( portMPU_REGION_VALID ) |\r
 635                                 ( portSTACK_REGION + 1 );\r
 636 \r
 637                 xMPUSettings->xRegion[ 1 ].ulRegionAttribute =\r
 638                                 ( portMPU_REGION_PRIVILEGED_READ_WRITE ) |\r
 639                                 ( portMPU_REGION_CACHEABLE_BUFFERABLE ) |\r
 640                                 prvGetMPURegionSizeSetting( ( uint32_t ) __privileged_data_end__ - ( uint32_t ) __privileged_data_start__ ) |\r
 641                                 ( portMPU_REGION_ENABLE );\r
 642 \r
 643                 /* Invalidate all other regions. */\r
 644                 for( ul = 2; ul <= portNUM_CONFIGURABLE_REGIONS; ul++ )\r
 645                 {\r
 646                         xMPUSettings->xRegion[ ul ].ulRegionBaseAddress = ( portSTACK_REGION + ul ) | portMPU_REGION_VALID;\r
 647                         xMPUSettings->xRegion[ ul ].ulRegionAttribute = 0UL;\r
 648                 }\r
 649         }\r
 650         else\r
 651         {\r
 652                 /* This function is called automatically when the task is created - in\r
 653                 which case the stack region parameters will be valid.  At all other\r
 654                 times the stack parameters will not be valid and it is assumed that the\r
 655                 stack region has already been configured. */\r
 656                 if( ulStackDepth > 0 )\r
 657                 {\r
 658                         /* Define the region that allows access to the stack. */\r
 659                         xMPUSettings->xRegion[ 0 ].ulRegionBaseAddress =\r
 660                                         ( ( uint32_t ) pxBottomOfStack ) |\r
 661                                         ( portMPU_REGION_VALID ) |\r
 662                                         ( portSTACK_REGION ); /* Region number. */\r
 663 \r
 664                         xMPUSettings->xRegion[ 0 ].ulRegionAttribute =\r
 665                                         ( portMPU_REGION_READ_WRITE ) | /* Read and write. */\r
 666                                         ( prvGetMPURegionSizeSetting( ulStackDepth * ( uint32_t ) sizeof( StackType_t ) ) ) |\r
 667                                         ( portMPU_REGION_CACHEABLE_BUFFERABLE ) |\r
 668                                         ( portMPU_REGION_ENABLE );\r
 669                 }\r
 670 \r
 671                 lIndex = 0;\r
 672 \r
 673                 for( ul = 1; ul <= portNUM_CONFIGURABLE_REGIONS; ul++ )\r
 674                 {\r
 675                         if( ( xRegions[ lIndex ] ).ulLengthInBytes > 0UL )\r
 676                         {\r
 677                                 /* Translate the generic region definition contained in\r
 678                                 xRegions into the CM3 specific MPU settings that are then\r
 679                                 stored in xMPUSettings. */\r
 680                                 xMPUSettings->xRegion[ ul ].ulRegionBaseAddress =\r
 681                                                 ( ( uint32_t ) xRegions[ lIndex ].pvBaseAddress ) |\r
 682                                                 ( portMPU_REGION_VALID ) |\r
 683                                                 ( portSTACK_REGION + ul ); /* Region number. */\r
 684 \r
 685                                 xMPUSettings->xRegion[ ul ].ulRegionAttribute =\r
 686                                                 ( prvGetMPURegionSizeSetting( xRegions[ lIndex ].ulLengthInBytes ) ) |\r
 687                                                 ( xRegions[ lIndex ].ulParameters ) |\r
 688                                                 ( portMPU_REGION_ENABLE );\r
 689                         }\r
 690                         else\r
 691                         {\r
 692                                 /* Invalidate the region. */\r
 693                                 xMPUSettings->xRegion[ ul ].ulRegionBaseAddress = ( portSTACK_REGION + ul ) | portMPU_REGION_VALID;\r
 694                                 xMPUSettings->xRegion[ ul ].ulRegionAttribute = 0UL;\r
 695                         }\r
 696 \r
 697                         lIndex++;\r
 698                 }\r
 699         }\r
 700 }\r
 701 /*-----------------------------------------------------------*/\r
 702 \r
 703 #if( configASSERT_DEFINED == 1 )\r
 704 \r
 705         void vPortValidateInterruptPriority( void )\r
 706         {\r
 707         uint32_t ulCurrentInterrupt;\r
 708         uint8_t ucCurrentPriority;\r
 709 \r
 710                 /* Obtain the number of the currently executing interrupt. */\r
 711                 __asm volatile( "mrs %0, ipsr" : "=r"( ulCurrentInterrupt ) :: "memory" );\r
 712 \r
 713                 /* Is the interrupt number a user defined interrupt? */\r
 714                 if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER )\r
 715                 {\r
 716                         /* Look up the interrupt's priority. */\r
 717                         ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ];\r
 718 \r
 719                         /* The following assertion will fail if a service routine (ISR) for\r
 720                         an interrupt that has been assigned a priority above\r
 721                         configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API\r
 722                         function.  ISR safe FreeRTOS API functions must *only* be called\r
 723                         from interrupts that have been assigned a priority at or below\r
 724                         configMAX_SYSCALL_INTERRUPT_PRIORITY.\r
 725 \r
 726                         Numerically low interrupt priority numbers represent logically high\r
 727                         interrupt priorities, therefore the priority of the interrupt must\r
 728                         be set to a value equal to or numerically *higher* than\r
 729                         configMAX_SYSCALL_INTERRUPT_PRIORITY.\r
 730 \r
 731                         Interrupts that use the FreeRTOS API must not be left at their\r
 732                         default priority of     zero as that is the highest possible priority,\r
 733                         which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY,\r
 734                         and     therefore also guaranteed to be invalid.\r
 735 \r
 736                         FreeRTOS maintains separate thread and ISR API functions to ensure\r
 737                         interrupt entry is as fast and simple as possible.\r
 738 \r
 739                         The following links provide detailed information:\r
 740                         http://www.freertos.org/RTOS-Cortex-M3-M4.html\r
 741                         http://www.freertos.org/FAQHelp.html */\r
 742                         configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );\r
 743                 }\r
 744 \r
 745                 /* Priority grouping:  The interrupt controller (NVIC) allows the bits\r
 746                 that define each interrupt's priority to be split between bits that\r
 747                 define the interrupt's pre-emption priority bits and bits that define\r
 748                 the interrupt's sub-priority.  For simplicity all bits must be defined\r
 749                 to be pre-emption priority bits.  The following assertion will fail if\r
 750                 this is not the case (if some bits represent a sub-priority).\r
 751 \r
 752                 If the application only uses CMSIS libraries for interrupt\r
 753                 configuration then the correct setting can be achieved on all Cortex-M\r
 754                 devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the\r
 755                 scheduler.  Note however that some vendor specific peripheral libraries\r
 756                 assume a non-zero priority group setting, in which cases using a value\r
 757                 of zero will result in unpredicable behaviour. */\r
 758                 configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );\r
 759         }\r
 760 \r
 761 #endif /* configASSERT_DEFINED */\r
 762 /*-----------------------------------------------------------*/\r
 763 \r
 764 \r