git.sur5r.net Git - freertos/blob - FreeRTOS/Source/portable/GCC/ARM_CM3_MPU/port.c

   1 /*\r
   2     FreeRTOS V9.0.0rc2 - Copyright (C) 2016 Real Time Engineers Ltd.\r
   3     All rights reserved\r
   4 \r
   5     VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
   6 \r
   7     This file is part of the FreeRTOS distribution.\r
   8 \r
   9     FreeRTOS is free software; you can redistribute it and/or modify it under\r
  10     the terms of the GNU General Public License (version 2) as published by the\r
  11     Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception.\r
  12 \r
  13     ***************************************************************************\r
  14     >>!   NOTE: The modification to the GPL is included to allow you to     !<<\r
  15     >>!   distribute a combined work that includes FreeRTOS without being   !<<\r
  16     >>!   obliged to provide the source code for proprietary components     !<<\r
  17     >>!   outside of the FreeRTOS kernel.                                   !<<\r
  18     ***************************************************************************\r
  19 \r
  20     FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
  21     WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
  22     FOR A PARTICULAR PURPOSE.  Full license text is available on the following\r
  23     link: http://www.freertos.org/a00114.html\r
  24 \r
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  36      *                                                                       *\r
  37     ***************************************************************************\r
  38 \r
  39     http://www.FreeRTOS.org/FAQHelp.html - Having a problem?  Start by reading\r
  40     the FAQ page "My application does not run, what could be wrong?".  Have you\r
  41     defined configASSERT()?\r
  42 \r
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  62 \r
  63     http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
  64     engineered and independently SIL3 certified version for use in safety and\r
  65     mission critical applications that require provable dependability.\r
  66 \r
  67     1 tab == 4 spaces!\r
  68 */\r
  69 \r
  70 /*-----------------------------------------------------------\r
  71  * Implementation of functions defined in portable.h for the ARM CM3 port.\r
  72  *----------------------------------------------------------*/\r
  73 \r
  74 /* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining\r
  75 all the API functions to use the MPU wrappers.  That should only be done when\r
  76 task.h is included from an application file. */\r
  77 #define MPU_WRAPPERS_INCLUDED_FROM_API_FILE\r
  78 \r
  79 /* Scheduler includes. */\r
  80 #include "FreeRTOS.h"\r
  81 #include "task.h"\r
  82 #include "queue.h"\r
  83 \r
  84 #undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE\r
  85 \r
  86 /* Constants required to access and manipulate the NVIC. */\r
  87 #define portNVIC_SYSTICK_CTRL                                   ( ( volatile uint32_t * ) 0xe000e010 )\r
  88 #define portNVIC_SYSTICK_LOAD                                   ( ( volatile uint32_t * ) 0xe000e014 )\r
  89 #define portNVIC_SYSPRI2                                                ( ( volatile uint32_t * ) 0xe000ed20 )\r
  90 #define portNVIC_SYSPRI1                                                ( ( volatile uint32_t * ) 0xe000ed1c )\r
  91 #define portNVIC_SYS_CTRL_STATE                                 ( ( volatile uint32_t * ) 0xe000ed24 )\r
  92 #define portNVIC_MEM_FAULT_ENABLE                               ( 1UL << 16UL )\r
  93 \r
  94 /* Constants required to access and manipulate the MPU. */\r
  95 #define portMPU_TYPE                                                    ( ( volatile uint32_t * ) 0xe000ed90 )\r
  96 #define portMPU_REGION_BASE_ADDRESS                             ( ( volatile uint32_t * ) 0xe000ed9C )\r
  97 #define portMPU_REGION_ATTRIBUTE                                ( ( volatile uint32_t * ) 0xe000edA0 )\r
  98 #define portMPU_CTRL                                                    ( ( volatile uint32_t * ) 0xe000ed94 )\r
  99 #define portEXPECTED_MPU_TYPE_VALUE                             ( 8UL << 8UL ) /* 8 regions, unified. */\r
 100 #define portMPU_ENABLE                                                  ( 0x01UL )\r
 101 #define portMPU_BACKGROUND_ENABLE                               ( 1UL << 2UL )\r
 102 #define portPRIVILEGED_EXECUTION_START_ADDRESS  ( 0UL )\r
 103 #define portMPU_REGION_VALID                                    ( 0x10UL )\r
 104 #define portMPU_REGION_ENABLE                                   ( 0x01UL )\r
 105 #define portPERIPHERALS_START_ADDRESS                   0x40000000UL\r
 106 #define portPERIPHERALS_END_ADDRESS                             0x5FFFFFFFUL\r
 107 \r
 108 /* Constants required to access and manipulate the SysTick. */\r
 109 #define portNVIC_SYSTICK_CLK                                    ( 0x00000004UL )\r
 110 #define portNVIC_SYSTICK_INT                                    ( 0x00000002UL )\r
 111 #define portNVIC_SYSTICK_ENABLE                                 ( 0x00000001UL )\r
 112 #define portNVIC_PENDSV_PRI                                             ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL )\r
 113 #define portNVIC_SYSTICK_PRI                                    ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL )\r
 114 #define portNVIC_SVC_PRI                                                ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL )\r
 115 \r
 116 /* Constants required to set up the initial stack. */\r
 117 #define portINITIAL_XPSR                                                ( 0x01000000 )\r
 118 #define portINITIAL_CONTROL_IF_UNPRIVILEGED             ( 0x03 )\r
 119 #define portINITIAL_CONTROL_IF_PRIVILEGED               ( 0x02 )\r
 120 \r
 121 /* Offsets in the stack to the parameters when inside the SVC handler. */\r
 122 #define portOFFSET_TO_PC                                                ( 6 )\r
 123 \r
 124 /* Set the privilege level to user mode if xRunningPrivileged is false. */\r
 125 #define portRESET_PRIVILEGE( xRunningPrivileged ) if( xRunningPrivileged != pdTRUE ) __asm volatile ( " mrs r0, control \n orr r0, #1 \n msr control, r0" :::"r0" )\r
 126 \r
 127 /* For strict compliance with the Cortex-M spec the task start address should\r
 128 have bit-0 clear, as it is loaded into the PC on exit from an ISR. */\r
 129 #define portSTART_ADDRESS_MASK                          ( ( StackType_t ) 0xfffffffeUL )\r
 130 \r
 131 /* Each task maintains its own interrupt status in the critical nesting\r
 132 variable.  Note this is not saved as part of the task context as context\r
 133 switches can only occur when uxCriticalNesting is zero. */\r
 134 static UBaseType_t uxCriticalNesting = 0xaaaaaaaa;\r
 135 \r
 136 /*\r
 137  * Setup the timer to generate the tick interrupts.\r
 138  */\r
 139 static void prvSetupTimerInterrupt( void ) PRIVILEGED_FUNCTION;\r
 140 \r
 141 /*\r
 142  * Configure a number of standard MPU regions that are used by all tasks.\r
 143  */\r
 144 static void prvSetupMPU( void ) PRIVILEGED_FUNCTION;\r
 145 \r
 146 /*\r
 147  * Return the smallest MPU region size that a given number of bytes will fit\r
 148  * into.  The region size is returned as the value that should be programmed\r
 149  * into the region attribute register for that region.\r
 150  */\r
 151 static uint32_t prvGetMPURegionSizeSetting( uint32_t ulActualSizeInBytes ) PRIVILEGED_FUNCTION;\r
 152 \r
 153 /*\r
 154  * Checks to see if being called from the context of an unprivileged task, and\r
 155  * if so raises the privilege level and returns false - otherwise does nothing\r
 156  * other than return true.\r
 157  */\r
 158 static BaseType_t prvRaisePrivilege( void ) __attribute__(( naked ));\r
 159 \r
 160 /*\r
 161  * Standard FreeRTOS exception handlers.\r
 162  */\r
 163 void xPortPendSVHandler( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;\r
 164 void xPortSysTickHandler( void )  __attribute__ ((optimize("3"))) PRIVILEGED_FUNCTION;\r
 165 void vPortSVCHandler( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;\r
 166 \r
 167 /*\r
 168  * Starts the scheduler by restoring the context of the first task to run.\r
 169  */\r
 170 static void prvRestoreContextOfFirstTask( void ) __attribute__(( naked )) PRIVILEGED_FUNCTION;\r
 171 \r
 172 /*\r
 173  * C portion of the SVC handler.  The SVC handler is split between an asm entry\r
 174  * and a C wrapper for simplicity of coding and maintenance.\r
 175  */\r
 176 static void prvSVCHandler( uint32_t *pulRegisters ) __attribute__(( noinline )) PRIVILEGED_FUNCTION;\r
 177 \r
 178 /*\r
 179  * Prototypes for all the MPU wrappers.\r
 180  */\r
 181 BaseType_t MPU_xTaskCreateRestricted( const TaskParameters_t * const pxTaskDefinition, TaskHandle_t *pxCreatedTask );\r
 182 BaseType_t MPU_xTaskCreate( TaskFunction_t pvTaskCode, const char * const pcName, uint16_t usStackDepth, void *pvParameters, UBaseType_t uxPriority, TaskHandle_t *pxCreatedTask );\r
 183 void MPU_vTaskAllocateMPURegions( TaskHandle_t xTask, const MemoryRegion_t * const xRegions );\r
 184 void MPU_vTaskDelete( TaskHandle_t pxTaskToDelete );\r
 185 void MPU_vTaskDelayUntil( TickType_t * const pxPreviousWakeTime, TickType_t xTimeIncrement );\r
 186 void MPU_vTaskDelay( TickType_t xTicksToDelay );\r
 187 UBaseType_t MPU_uxTaskPriorityGet( TaskHandle_t pxTask );\r
 188 void MPU_vTaskPrioritySet( TaskHandle_t pxTask, UBaseType_t uxNewPriority );\r
 189 eTaskState MPU_eTaskGetState( TaskHandle_t pxTask );\r
 190 void MPU_vTaskSuspend( TaskHandle_t pxTaskToSuspend );\r
 191 void MPU_vTaskResume( TaskHandle_t pxTaskToResume );\r
 192 void MPU_vTaskSuspendAll( void );\r
 193 BaseType_t MPU_xTaskResumeAll( void );\r
 194 TickType_t MPU_xTaskGetTickCount( void );\r
 195 UBaseType_t MPU_uxTaskGetNumberOfTasks( void );\r
 196 void MPU_vTaskList( char *pcWriteBuffer );\r
 197 void MPU_vTaskGetRunTimeStats( char *pcWriteBuffer );\r
 198 void MPU_vTaskSetApplicationTaskTag( TaskHandle_t xTask, TaskHookFunction_t pxTagValue );\r
 199 TaskHookFunction_t MPU_xTaskGetApplicationTaskTag( TaskHandle_t xTask );\r
 200 BaseType_t MPU_xTaskCallApplicationTaskHook( TaskHandle_t xTask, void *pvParameter );\r
 201 UBaseType_t MPU_uxTaskGetStackHighWaterMark( TaskHandle_t xTask );\r
 202 TaskHandle_t MPU_xTaskGetCurrentTaskHandle( void );\r
 203 BaseType_t MPU_xTaskGetSchedulerState( void );\r
 204 TaskHandle_t MPU_xTaskGetIdleTaskHandle( void );\r
 205 UBaseType_t MPU_uxTaskGetSystemState( TaskStatus_t *pxTaskStatusArray, UBaseType_t uxArraySize, uint32_t *pulTotalRunTime );\r
 206 QueueHandle_t MPU_xQueueGenericCreate( UBaseType_t uxQueueLength, UBaseType_t uxItemSize, uint8_t ucQueueType );\r
 207 BaseType_t MPU_xQueueGenericSend( QueueHandle_t xQueue, const void * const pvItemToQueue, TickType_t xTicksToWait, BaseType_t xCopyPosition );\r
 208 BaseType_t MPU_xQueueGenericReset( QueueHandle_t pxQueue, BaseType_t xNewQueue );\r
 209 UBaseType_t MPU_uxQueueMessagesWaiting( const QueueHandle_t pxQueue );\r
 210 BaseType_t MPU_xQueueGenericReceive( QueueHandle_t pxQueue, void * const pvBuffer, TickType_t xTicksToWait, BaseType_t xJustPeeking );\r
 211 QueueHandle_t MPU_xQueueCreateMutex( void );\r
 212 QueueHandle_t MPU_xQueueCreateCountingSemaphore( UBaseType_t uxCountValue, UBaseType_t uxInitialCount );\r
 213 BaseType_t MPU_xQueueTakeMutexRecursive( QueueHandle_t xMutex, TickType_t xBlockTime );\r
 214 BaseType_t MPU_xQueueGiveMutexRecursive( QueueHandle_t xMutex );\r
 215 void MPU_vQueueAddToRegistry( QueueHandle_t xQueue, char *pcName );\r
 216 void MPU_vQueueDelete( QueueHandle_t xQueue );\r
 217 void *MPU_pvPortMalloc( size_t xSize );\r
 218 void MPU_vPortFree( void *pv );\r
 219 void MPU_vPortInitialiseBlocks( void );\r
 220 size_t MPU_xPortGetFreeHeapSize( void );\r
 221 QueueSetHandle_t MPU_xQueueCreateSet( UBaseType_t uxEventQueueLength );\r
 222 QueueSetMemberHandle_t MPU_xQueueSelectFromSet( QueueSetHandle_t xQueueSet, TickType_t xBlockTimeTicks );\r
 223 BaseType_t MPU_xQueueAddToSet( QueueSetMemberHandle_t xQueueOrSemaphore, QueueSetHandle_t xQueueSet );\r
 224 BaseType_t MPU_xQueueRemoveFromSet( QueueSetMemberHandle_t xQueueOrSemaphore, QueueSetHandle_t xQueueSet );\r
 225 BaseType_t MPU_xQueuePeekFromISR( QueueHandle_t xQueue, void * const pvBuffer );\r
 226 void* MPU_xQueueGetMutexHolder( QueueHandle_t xSemaphore );\r
 227 \r
 228 /*-----------------------------------------------------------*/\r
 229 \r
 230 /*\r
 231  * See header file for description.\r
 232  */\r
 233 StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters, BaseType_t xRunPrivileged )\r
 234 {\r
 235         /* Simulate the stack frame as it would be created by a context switch\r
 236         interrupt. */\r
 237         pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */\r
 238         *pxTopOfStack = portINITIAL_XPSR;       /* xPSR */\r
 239         pxTopOfStack--;\r
 240         *pxTopOfStack = ( ( StackType_t ) pxCode ) & portSTART_ADDRESS_MASK;    /* PC */\r
 241         pxTopOfStack--;\r
 242         *pxTopOfStack = 0;      /* LR */\r
 243         pxTopOfStack -= 5;      /* R12, R3, R2 and R1. */\r
 244         *pxTopOfStack = ( StackType_t ) pvParameters;   /* R0 */\r
 245         pxTopOfStack -= 9;      /* R11, R10, R9, R8, R7, R6, R5 and R4. */\r
 246 \r
 247         if( xRunPrivileged == pdTRUE )\r
 248         {\r
 249                 *pxTopOfStack = portINITIAL_CONTROL_IF_PRIVILEGED;\r
 250         }\r
 251         else\r
 252         {\r
 253                 *pxTopOfStack = portINITIAL_CONTROL_IF_UNPRIVILEGED;\r
 254         }\r
 255 \r
 256         return pxTopOfStack;\r
 257 }\r
 258 /*-----------------------------------------------------------*/\r
 259 \r
 260 void vPortSVCHandler( void )\r
 261 {\r
 262         /* Assumes psp was in use. */\r
 263         __asm volatile\r
 264         (\r
 265                 #ifndef USE_PROCESS_STACK       /* Code should not be required if a main() is using the process stack. */\r
 266                         "       tst lr, #4                                              \n"\r
 267                         "       ite eq                                                  \n"\r
 268                         "       mrseq r0, msp                                   \n"\r
 269                         "       mrsne r0, psp                                   \n"\r
 270                 #else\r
 271                         "       mrs r0, psp                                             \n"\r
 272                 #endif\r
 273                         "       b %0                                                    \n"\r
 274                         ::"i"(prvSVCHandler):"r0"\r
 275         );\r
 276 }\r
 277 /*-----------------------------------------------------------*/\r
 278 \r
 279 static void prvSVCHandler(      uint32_t *pulParam )\r
 280 {\r
 281 uint8_t ucSVCNumber;\r
 282 \r
 283         /* The stack contains: r0, r1, r2, r3, r12, r14, the return address and\r
 284         xPSR.  The first argument (r0) is pulParam[ 0 ]. */\r
 285         ucSVCNumber = ( ( uint8_t * ) pulParam[ portOFFSET_TO_PC ] )[ -2 ];\r
 286         switch( ucSVCNumber )\r
 287         {\r
 288                 case portSVC_START_SCHEDULER    :       *(portNVIC_SYSPRI1) |= portNVIC_SVC_PRI;\r
 289                                                                                         prvRestoreContextOfFirstTask();\r
 290                                                                                         break;\r
 291 \r
 292                 case portSVC_YIELD                              :       *(portNVIC_INT_CTRL) = portNVIC_PENDSVSET;\r
 293                                                                                         /* Barriers are normally not required\r
 294                                                                                         but do ensure the code is completely\r
 295                                                                                         within the specified behaviour for the\r
 296                                                                                         architecture. */\r
 297                                                                                         __asm volatile( "dsb" );\r
 298                                                                                         __asm volatile( "isb" );\r
 299 \r
 300                                                                                         break;\r
 301 \r
 302                 case portSVC_RAISE_PRIVILEGE    :       __asm volatile\r
 303                                                                                         (\r
 304                                                                                                 "       mrs r1, control         \n" /* Obtain current control value. */\r
 305                                                                                                 "       bic r1, #1                      \n" /* Set privilege bit. */\r
 306                                                                                                 "       msr control, r1         \n" /* Write back new control value. */\r
 307                                                                                                 :::"r1"\r
 308                                                                                         );\r
 309                                                                                         break;\r
 310 \r
 311                 default                                                 :       /* Unknown SVC call. */\r
 312                                                                                         break;\r
 313         }\r
 314 }\r
 315 /*-----------------------------------------------------------*/\r
 316 \r
 317 static void prvRestoreContextOfFirstTask( void )\r
 318 {\r
 319         __asm volatile\r
 320         (\r
 321                 "       ldr r0, =0xE000ED08                             \n" /* Use the NVIC offset register to locate the stack. */\r
 322                 "       ldr r0, [r0]                                    \n"\r
 323                 "       ldr r0, [r0]                                    \n"\r
 324                 "       msr msp, r0                                             \n" /* Set the msp back to the start of the stack. */\r
 325                 "       ldr     r3, pxCurrentTCBConst2          \n" /* Restore the context. */\r
 326                 "       ldr r1, [r3]                                    \n"\r
 327                 "       ldr r0, [r1]                                    \n" /* The first item in the TCB is the task top of stack. */\r
 328                 "       add r1, r1, #4                                  \n" /* Move onto the second item in the TCB... */\r
 329                 "       ldr r2, =0xe000ed9c                             \n" /* Region Base Address register. */\r
 330                 "       ldmia r1!, {r4-r11}                             \n" /* Read 4 sets of MPU registers. */\r
 331                 "       stmia r2!, {r4-r11}                             \n" /* Write 4 sets of MPU registers. */\r
 332                 "       ldmia r0!, {r3, r4-r11}                 \n" /* Pop the registers that are not automatically saved on exception entry. */\r
 333                 "       msr control, r3                                 \n"\r
 334                 "       msr psp, r0                                             \n" /* Restore the task stack pointer. */\r
 335                 "       mov r0, #0                                              \n"\r
 336                 "       msr     basepri, r0                                     \n"\r
 337                 "       ldr r14, =0xfffffffd                    \n" /* Load exec return code. */\r
 338                 "       bx r14                                                  \n"\r
 339                 "                                                                       \n"\r
 340                 "       .align 4                                                \n"\r
 341                 "pxCurrentTCBConst2: .word pxCurrentTCB \n"\r
 342         );\r
 343 }\r
 344 /*-----------------------------------------------------------*/\r
 345 \r
 346 /*\r
 347  * See header file for description.\r
 348  */\r
 349 BaseType_t xPortStartScheduler( void )\r
 350 {\r
 351         /* configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0.  See\r
 352         http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */\r
 353         configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) );\r
 354 \r
 355         /* Make PendSV and SysTick the same priority as the kernel. */\r
 356         *(portNVIC_SYSPRI2) |= portNVIC_PENDSV_PRI;\r
 357         *(portNVIC_SYSPRI2) |= portNVIC_SYSTICK_PRI;\r
 358 \r
 359         /* Configure the regions in the MPU that are common to all tasks. */\r
 360         prvSetupMPU();\r
 361 \r
 362         /* Start the timer that generates the tick ISR.  Interrupts are disabled\r
 363         here already. */\r
 364         prvSetupTimerInterrupt();\r
 365 \r
 366         /* Initialise the critical nesting count ready for the first task. */\r
 367         uxCriticalNesting = 0;\r
 368 \r
 369         /* Start the first task. */\r
 370         __asm volatile( "       svc %0                  \n"\r
 371                                         :: "i" (portSVC_START_SCHEDULER) );\r
 372 \r
 373         /* Should not get here! */\r
 374         return 0;\r
 375 }\r
 376 /*-----------------------------------------------------------*/\r
 377 \r
 378 void vPortEndScheduler( void )\r
 379 {\r
 380         /* Not implemented in ports where there is nothing to return to.\r
 381         Artificially force an assert. */\r
 382         configASSERT( uxCriticalNesting == 1000UL );\r
 383 }\r
 384 /*-----------------------------------------------------------*/\r
 385 \r
 386 void vPortEnterCritical( void )\r
 387 {\r
 388 BaseType_t xRunningPrivileged = prvRaisePrivilege();\r
 389 \r
 390         portDISABLE_INTERRUPTS();\r
 391         uxCriticalNesting++;\r
 392 \r
 393         portRESET_PRIVILEGE( xRunningPrivileged );\r
 394 }\r
 395 /*-----------------------------------------------------------*/\r
 396 \r
 397 void vPortExitCritical( void )\r
 398 {\r
 399 BaseType_t xRunningPrivileged = prvRaisePrivilege();\r
 400 \r
 401         configASSERT( uxCriticalNesting );\r
 402         uxCriticalNesting--;\r
 403         if( uxCriticalNesting == 0 )\r
 404         {\r
 405                 portENABLE_INTERRUPTS();\r
 406         }\r
 407         portRESET_PRIVILEGE( xRunningPrivileged );\r
 408 }\r
 409 /*-----------------------------------------------------------*/\r
 410 \r
 411 void xPortPendSVHandler( void )\r
 412 {\r
 413         /* This is a naked function. */\r
 414 \r
 415         __asm volatile\r
 416         (\r
 417                 "       mrs r0, psp                                                     \n"\r
 418                 "                                                                               \n"\r
 419                 "       ldr     r3, pxCurrentTCBConst                   \n" /* Get the location of the current TCB. */\r
 420                 "       ldr     r2, [r3]                                                \n"\r
 421                 "                                                                               \n"\r
 422                 "       mrs r1, control                                         \n"\r
 423                 "       stmdb r0!, {r1, r4-r11}                         \n" /* Save the remaining registers. */\r
 424                 "       str r0, [r2]                                            \n" /* Save the new top of stack into the first member of the TCB. */\r
 425                 "                                                                               \n"\r
 426                 "       stmdb sp!, {r3, r14}                            \n"\r
 427                 "       mov r0, %0                                                      \n"\r
 428                 "       msr basepri, r0                                         \n"\r
 429                 "       bl vTaskSwitchContext                           \n"\r
 430                 "       mov r0, #0                                                      \n"\r
 431                 "       msr basepri, r0                                         \n"\r
 432                 "       ldmia sp!, {r3, r14}                            \n"\r
 433                 "                                                                               \n"     /* Restore the context. */\r
 434                 "       ldr r1, [r3]                                            \n"\r
 435                 "       ldr r0, [r1]                                            \n" /* The first item in the TCB is the task top of stack. */\r
 436                 "       add r1, r1, #4                                          \n" /* Move onto the second item in the TCB... */\r
 437                 "       ldr r2, =0xe000ed9c                                     \n" /* Region Base Address register. */\r
 438                 "       ldmia r1!, {r4-r11}                                     \n" /* Read 4 sets of MPU registers. */\r
 439                 "       stmia r2!, {r4-r11}                                     \n" /* Write 4 sets of MPU registers. */\r
 440                 "       ldmia r0!, {r3, r4-r11}                         \n" /* Pop the registers that are not automatically saved on exception entry. */\r
 441                 "       msr control, r3                                         \n"\r
 442                 "                                                                               \n"\r
 443                 "       msr psp, r0                                                     \n"\r
 444                 "       bx r14                                                          \n"\r
 445                 "                                                                               \n"\r
 446                 "       .align 4                                                        \n"\r
 447                 "pxCurrentTCBConst: .word pxCurrentTCB  \n"\r
 448                 ::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY)\r
 449         );\r
 450 }\r
 451 /*-----------------------------------------------------------*/\r
 452 \r
 453 void xPortSysTickHandler( void )\r
 454 {\r
 455 uint32_t ulDummy;\r
 456 \r
 457         ulDummy = portSET_INTERRUPT_MASK_FROM_ISR();\r
 458         {\r
 459                 /* Increment the RTOS tick. */\r
 460                 if( xTaskIncrementTick() != pdFALSE )\r
 461                 {\r
 462                         /* Pend a context switch. */\r
 463                         *(portNVIC_INT_CTRL) = portNVIC_PENDSVSET;\r
 464                 }\r
 465         }\r
 466         portCLEAR_INTERRUPT_MASK_FROM_ISR( ulDummy );\r
 467 }\r
 468 /*-----------------------------------------------------------*/\r
 469 \r
 470 /*\r
 471  * Setup the systick timer to generate the tick interrupts at the required\r
 472  * frequency.\r
 473  */\r
 474 static void prvSetupTimerInterrupt( void )\r
 475 {\r
 476         /* Configure SysTick to interrupt at the requested rate. */\r
 477         *(portNVIC_SYSTICK_LOAD) = ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;\r
 478         *(portNVIC_SYSTICK_CTRL) = portNVIC_SYSTICK_CLK | portNVIC_SYSTICK_INT | portNVIC_SYSTICK_ENABLE;\r
 479 }\r
 480 /*-----------------------------------------------------------*/\r
 481 \r
 482 static void prvSetupMPU( void )\r
 483 {\r
 484 extern uint32_t __privileged_functions_end__[];\r
 485 extern uint32_t __FLASH_segment_start__[];\r
 486 extern uint32_t __FLASH_segment_end__[];\r
 487 extern uint32_t __privileged_data_start__[];\r
 488 extern uint32_t __privileged_data_end__[];\r
 489 \r
 490         /* Check the expected MPU is present. */\r
 491         if( *portMPU_TYPE == portEXPECTED_MPU_TYPE_VALUE )\r
 492         {\r
 493                 /* First setup the entire flash for unprivileged read only access. */\r
 494         *portMPU_REGION_BASE_ADDRESS =  ( ( uint32_t ) __FLASH_segment_start__ ) | /* Base address. */\r
 495                                                                                 ( portMPU_REGION_VALID ) |\r
 496                                                                                 ( portUNPRIVILEGED_FLASH_REGION );\r
 497 \r
 498                 *portMPU_REGION_ATTRIBUTE =             ( portMPU_REGION_READ_ONLY ) |\r
 499                                                                                 ( portMPU_REGION_CACHEABLE_BUFFERABLE ) |\r
 500                                                                                 ( prvGetMPURegionSizeSetting( ( uint32_t ) __FLASH_segment_end__ - ( uint32_t ) __FLASH_segment_start__ ) ) |\r
 501                                                                                 ( portMPU_REGION_ENABLE );\r
 502 \r
 503                 /* Setup the first 16K for privileged only access (even though less\r
 504                 than 10K is actually being used).  This is where the kernel code is\r
 505                 placed. */\r
 506         *portMPU_REGION_BASE_ADDRESS =  ( ( uint32_t ) __FLASH_segment_start__ ) | /* Base address. */\r
 507                                                                                 ( portMPU_REGION_VALID ) |\r
 508                                                                                 ( portPRIVILEGED_FLASH_REGION );\r
 509 \r
 510                 *portMPU_REGION_ATTRIBUTE =             ( portMPU_REGION_PRIVILEGED_READ_ONLY ) |\r
 511                                                                                 ( portMPU_REGION_CACHEABLE_BUFFERABLE ) |\r
 512                                                                                 ( prvGetMPURegionSizeSetting( ( uint32_t ) __privileged_functions_end__ - ( uint32_t ) __FLASH_segment_start__ ) ) |\r
 513                                                                                 ( portMPU_REGION_ENABLE );\r
 514 \r
 515                 /* Setup the privileged data RAM region.  This is where the kernel data\r
 516                 is placed. */\r
 517                 *portMPU_REGION_BASE_ADDRESS =  ( ( uint32_t ) __privileged_data_start__ ) | /* Base address. */\r
 518                                                                                 ( portMPU_REGION_VALID ) |\r
 519                                                                                 ( portPRIVILEGED_RAM_REGION );\r
 520 \r
 521                 *portMPU_REGION_ATTRIBUTE =             ( portMPU_REGION_PRIVILEGED_READ_WRITE ) |\r
 522                                                                                 ( portMPU_REGION_CACHEABLE_BUFFERABLE ) |\r
 523                                                                                 prvGetMPURegionSizeSetting( ( uint32_t ) __privileged_data_end__ - ( uint32_t ) __privileged_data_start__ ) |\r
 524                                                                                 ( portMPU_REGION_ENABLE );\r
 525 \r
 526                 /* By default allow everything to access the general peripherals.  The\r
 527                 system peripherals and registers are protected. */\r
 528                 *portMPU_REGION_BASE_ADDRESS =  ( portPERIPHERALS_START_ADDRESS ) |\r
 529                                                                                 ( portMPU_REGION_VALID ) |\r
 530                                                                                 ( portGENERAL_PERIPHERALS_REGION );\r
 531 \r
 532                 *portMPU_REGION_ATTRIBUTE =             ( portMPU_REGION_READ_WRITE | portMPU_REGION_EXECUTE_NEVER ) |\r
 533                                                                                 ( prvGetMPURegionSizeSetting( portPERIPHERALS_END_ADDRESS - portPERIPHERALS_START_ADDRESS ) ) |\r
 534                                                                                 ( portMPU_REGION_ENABLE );\r
 535 \r
 536                 /* Enable the memory fault exception. */\r
 537                 *portNVIC_SYS_CTRL_STATE |= portNVIC_MEM_FAULT_ENABLE;\r
 538 \r
 539                 /* Enable the MPU with the background region configured. */\r
 540                 *portMPU_CTRL |= ( portMPU_ENABLE | portMPU_BACKGROUND_ENABLE );\r
 541         }\r
 542 }\r
 543 /*-----------------------------------------------------------*/\r
 544 \r
 545 static uint32_t prvGetMPURegionSizeSetting( uint32_t ulActualSizeInBytes )\r
 546 {\r
 547 uint32_t ulRegionSize, ulReturnValue = 4;\r
 548 \r
 549         /* 32 is the smallest region size, 31 is the largest valid value for\r
 550         ulReturnValue. */\r
 551         for( ulRegionSize = 32UL; ulReturnValue < 31UL; ( ulRegionSize <<= 1UL ) )\r
 552         {\r
 553                 if( ulActualSizeInBytes <= ulRegionSize )\r
 554                 {\r
 555                         break;\r
 556                 }\r
 557                 else\r
 558                 {\r
 559                         ulReturnValue++;\r
 560                 }\r
 561         }\r
 562 \r
 563         /* Shift the code by one before returning so it can be written directly\r
 564         into the the correct bit position of the attribute register. */\r
 565         return ( ulReturnValue << 1UL );\r
 566 }\r
 567 /*-----------------------------------------------------------*/\r
 568 \r
 569 static BaseType_t prvRaisePrivilege( void )\r
 570 {\r
 571         __asm volatile\r
 572         (\r
 573                 "       mrs r0, control                                         \n"\r
 574                 "       tst r0, #1                                                      \n" /* Is the task running privileged? */\r
 575                 "       itte ne                                                         \n"\r
 576                 "       movne r0, #0                                            \n" /* CONTROL[0]!=0, return false. */\r
 577                 "       svcne %0                                                        \n" /* Switch to privileged. */\r
 578                 "       moveq r0, #1                                            \n" /* CONTROL[0]==0, return true. */\r
 579                 "       bx lr                                                           \n"\r
 580                 :: "i" (portSVC_RAISE_PRIVILEGE) : "r0"\r
 581         );\r
 582 \r
 583         return 0;\r
 584 }\r
 585 /*-----------------------------------------------------------*/\r
 586 \r
 587 void vPortStoreTaskMPUSettings( xMPU_SETTINGS *xMPUSettings, const struct xMEMORY_REGION * const xRegions, StackType_t *pxBottomOfStack, uint32_t ulStackDepth )\r
 588 {\r
 589 extern uint32_t __SRAM_segment_start__[];\r
 590 extern uint32_t __SRAM_segment_end__[];\r
 591 extern uint32_t __privileged_data_start__[];\r
 592 extern uint32_t __privileged_data_end__[];\r
 593 int32_t lIndex;\r
 594 uint32_t ul;\r
 595 \r
 596         if( xRegions == NULL )\r
 597         {\r
 598                 /* No MPU regions are specified so allow access to all RAM. */\r
 599         xMPUSettings->xRegion[ 0 ].ulRegionBaseAddress =\r
 600                                 ( ( uint32_t ) __SRAM_segment_start__ ) | /* Base address. */\r
 601                                 ( portMPU_REGION_VALID ) |\r
 602                                 ( portSTACK_REGION );\r
 603 \r
 604                 xMPUSettings->xRegion[ 0 ].ulRegionAttribute =\r
 605                                 ( portMPU_REGION_READ_WRITE ) |\r
 606                                 ( portMPU_REGION_CACHEABLE_BUFFERABLE ) |\r
 607                                 ( prvGetMPURegionSizeSetting( ( uint32_t ) __SRAM_segment_end__ - ( uint32_t ) __SRAM_segment_start__ ) ) |\r
 608                                 ( portMPU_REGION_ENABLE );\r
 609 \r
 610                 /* Re-instate the privileged only RAM region as xRegion[ 0 ] will have\r
 611                 just removed the privileged only parameters. */\r
 612                 xMPUSettings->xRegion[ 1 ].ulRegionBaseAddress =\r
 613                                 ( ( uint32_t ) __privileged_data_start__ ) | /* Base address. */\r
 614                                 ( portMPU_REGION_VALID ) |\r
 615                                 ( portSTACK_REGION + 1 );\r
 616 \r
 617                 xMPUSettings->xRegion[ 1 ].ulRegionAttribute =\r
 618                                 ( portMPU_REGION_PRIVILEGED_READ_WRITE ) |\r
 619                                 ( portMPU_REGION_CACHEABLE_BUFFERABLE ) |\r
 620                                 prvGetMPURegionSizeSetting( ( uint32_t ) __privileged_data_end__ - ( uint32_t ) __privileged_data_start__ ) |\r
 621                                 ( portMPU_REGION_ENABLE );\r
 622 \r
 623                 /* Invalidate all other regions. */\r
 624                 for( ul = 2; ul <= portNUM_CONFIGURABLE_REGIONS; ul++ )\r
 625                 {\r
 626                         xMPUSettings->xRegion[ ul ].ulRegionBaseAddress = ( portSTACK_REGION + ul ) | portMPU_REGION_VALID;\r
 627                         xMPUSettings->xRegion[ ul ].ulRegionAttribute = 0UL;\r
 628                 }\r
 629         }\r
 630         else\r
 631         {\r
 632                 /* This function is called automatically when the task is created - in\r
 633                 which case the stack region parameters will be valid.  At all other\r
 634                 times the stack parameters will not be valid and it is assumed that the\r
 635                 stack region has already been configured. */\r
 636                 if( ulStackDepth > 0 )\r
 637                 {\r
 638                         /* Define the region that allows access to the stack. */\r
 639                         xMPUSettings->xRegion[ 0 ].ulRegionBaseAddress =\r
 640                                         ( ( uint32_t ) pxBottomOfStack ) |\r
 641                                         ( portMPU_REGION_VALID ) |\r
 642                                         ( portSTACK_REGION ); /* Region number. */\r
 643 \r
 644                         xMPUSettings->xRegion[ 0 ].ulRegionAttribute =\r
 645                                         ( portMPU_REGION_READ_WRITE ) | /* Read and write. */\r
 646                                         ( prvGetMPURegionSizeSetting( ulStackDepth * ( uint32_t ) sizeof( StackType_t ) ) ) |\r
 647                                         ( portMPU_REGION_CACHEABLE_BUFFERABLE ) |\r
 648                                         ( portMPU_REGION_ENABLE );\r
 649                 }\r
 650 \r
 651                 lIndex = 0;\r
 652 \r
 653                 for( ul = 1; ul <= portNUM_CONFIGURABLE_REGIONS; ul++ )\r
 654                 {\r
 655                         if( ( xRegions[ lIndex ] ).ulLengthInBytes > 0UL )\r
 656                         {\r
 657                                 /* Translate the generic region definition contained in\r
 658                                 xRegions into the CM3 specific MPU settings that are then\r
 659                                 stored in xMPUSettings. */\r
 660                                 xMPUSettings->xRegion[ ul ].ulRegionBaseAddress =\r
 661                                                 ( ( uint32_t ) xRegions[ lIndex ].pvBaseAddress ) |\r
 662                                                 ( portMPU_REGION_VALID ) |\r
 663                                                 ( portSTACK_REGION + ul ); /* Region number. */\r
 664 \r
 665                                 xMPUSettings->xRegion[ ul ].ulRegionAttribute =\r
 666                                                 ( prvGetMPURegionSizeSetting( xRegions[ lIndex ].ulLengthInBytes ) ) |\r
 667                                                 ( xRegions[ lIndex ].ulParameters ) |\r
 668                                                 ( portMPU_REGION_ENABLE );\r
 669                         }\r
 670                         else\r
 671                         {\r
 672                                 /* Invalidate the region. */\r
 673                                 xMPUSettings->xRegion[ ul ].ulRegionBaseAddress = ( portSTACK_REGION + ul ) | portMPU_REGION_VALID;\r
 674                                 xMPUSettings->xRegion[ ul ].ulRegionAttribute = 0UL;\r
 675                         }\r
 676 \r
 677                         lIndex++;\r
 678                 }\r
 679         }\r
 680 }\r
 681 /*-----------------------------------------------------------*/\r
 682 \r
 683 BaseType_t MPU_xTaskCreateRestricted( const TaskParameters_t * const pxTaskDefinition, TaskHandle_t *pxCreatedTask )\r
 684 {\r
 685 BaseType_t xReturn;\r
 686 BaseType_t xRunningPrivileged = prvRaisePrivilege();\r
 687 \r
 688         xReturn = xTaskCreateRestricted( pxTaskDefinition, pxCreatedTask );\r
 689         portRESET_PRIVILEGE( xRunningPrivileged );\r
 690         return xReturn;\r
 691 }\r
 692 /*-----------------------------------------------------------*/\r
 693 \r
 694 BaseType_t MPU_xTaskCreate( TaskFunction_t pvTaskCode, const char * const pcName, uint16_t usStackDepth, void *pvParameters, UBaseType_t uxPriority, TaskHandle_t *pxCreatedTask )\r
 695 {\r
 696 BaseType_t xReturn;\r
 697 BaseType_t xRunningPrivileged = prvRaisePrivilege();\r
 698 \r
 699         xReturn = xTaskCreate( pvTaskCode, pcName, usStackDepth, pvParameters, uxPriority, pxCreatedTask );\r
 700         portRESET_PRIVILEGE( xRunningPrivileged );\r
 701         return xReturn;\r
 702 }\r
 703 /*-----------------------------------------------------------*/\r
 704 \r
 705 void MPU_vTaskAllocateMPURegions( TaskHandle_t xTask, const MemoryRegion_t * const xRegions )\r
 706 {\r
 707 BaseType_t xRunningPrivileged = prvRaisePrivilege();\r
 708 \r
 709         vTaskAllocateMPURegions( xTask, xRegions );\r
 710         portRESET_PRIVILEGE( xRunningPrivileged );\r
 711 }\r
 712 /*-----------------------------------------------------------*/\r
 713 \r
 714 #if ( INCLUDE_vTaskDelete == 1 )\r
 715         void MPU_vTaskDelete( TaskHandle_t pxTaskToDelete )\r
 716         {\r
 717     BaseType_t xRunningPrivileged = prvRaisePrivilege();\r
 718 \r
 719                 vTaskDelete( pxTaskToDelete );\r
 720         portRESET_PRIVILEGE( xRunningPrivileged );\r
 721         }\r
 722 #endif\r
 723 /*-----------------------------------------------------------*/\r
 724 \r
 725 #if ( INCLUDE_vTaskDelayUntil == 1 )\r
 726         void MPU_vTaskDelayUntil( TickType_t * const pxPreviousWakeTime, TickType_t xTimeIncrement )\r
 727         {\r
 728     BaseType_t xRunningPrivileged = prvRaisePrivilege();\r
 729 \r
 730                 vTaskDelayUntil( pxPreviousWakeTime, xTimeIncrement );\r
 731         portRESET_PRIVILEGE( xRunningPrivileged );\r
 732         }\r
 733 #endif\r
 734 /*-----------------------------------------------------------*/\r
 735 \r
 736 #if ( INCLUDE_vTaskDelay == 1 )\r
 737         void MPU_vTaskDelay( TickType_t xTicksToDelay )\r
 738         {\r
 739     BaseType_t xRunningPrivileged = prvRaisePrivilege();\r
 740 \r
 741                 vTaskDelay( xTicksToDelay );\r
 742         portRESET_PRIVILEGE( xRunningPrivileged );\r
 743         }\r
 744 #endif\r
 745 /*-----------------------------------------------------------*/\r
 746 \r
 747 #if ( INCLUDE_uxTaskPriorityGet == 1 )\r
 748         UBaseType_t MPU_uxTaskPriorityGet( TaskHandle_t pxTask )\r
 749         {\r
 750         UBaseType_t uxReturn;\r
 751     BaseType_t xRunningPrivileged = prvRaisePrivilege();\r
 752 \r
 753                 uxReturn = uxTaskPriorityGet( pxTask );\r
 754         portRESET_PRIVILEGE( xRunningPrivileged );\r
 755                 return uxReturn;\r
 756         }\r
 757 #endif\r
 758 /*-----------------------------------------------------------*/\r
 759 \r
 760 #if ( INCLUDE_vTaskPrioritySet == 1 )\r
 761         void MPU_vTaskPrioritySet( TaskHandle_t pxTask, UBaseType_t uxNewPriority )\r
 762         {\r
 763     BaseType_t xRunningPrivileged = prvRaisePrivilege();\r
 764 \r
 765                 vTaskPrioritySet( pxTask, uxNewPriority );\r
 766         portRESET_PRIVILEGE( xRunningPrivileged );\r
 767         }\r
 768 #endif\r
 769 /*-----------------------------------------------------------*/\r
 770 \r
 771 #if ( INCLUDE_eTaskGetState == 1 )\r
 772         eTaskState MPU_eTaskGetState( TaskHandle_t pxTask )\r
 773         {\r
 774     BaseType_t xRunningPrivileged = prvRaisePrivilege();\r
 775         eTaskState eReturn;\r
 776 \r
 777                 eReturn = eTaskGetState( pxTask );\r
 778         portRESET_PRIVILEGE( xRunningPrivileged );\r
 779                 return eReturn;\r
 780         }\r
 781 #endif\r
 782 /*-----------------------------------------------------------*/\r
 783 \r
 784 #if ( INCLUDE_xTaskGetIdleTaskHandle == 1 )\r
 785         TaskHandle_t MPU_xTaskGetIdleTaskHandle( void )\r
 786         {\r
 787         TaskHandle_t xReturn;\r
 788     BaseType_t xRunningPrivileged = prvRaisePrivilege();\r
 789 \r
 790                 xReturn = xTaskGetIdleTaskHandle();\r
 791         portRESET_PRIVILEGE( xRunningPrivileged );\r
 792                 return eReturn;\r
 793         }\r
 794 #endif\r
 795 /*-----------------------------------------------------------*/\r
 796 \r
 797 #if ( INCLUDE_vTaskSuspend == 1 )\r
 798         void MPU_vTaskSuspend( TaskHandle_t pxTaskToSuspend )\r
 799         {\r
 800     BaseType_t xRunningPrivileged = prvRaisePrivilege();\r
 801 \r
 802                 vTaskSuspend( pxTaskToSuspend );\r
 803         portRESET_PRIVILEGE( xRunningPrivileged );\r
 804         }\r
 805 #endif\r
 806 /*-----------------------------------------------------------*/\r
 807 \r
 808 #if ( INCLUDE_vTaskSuspend == 1 )\r
 809         void MPU_vTaskResume( TaskHandle_t pxTaskToResume )\r
 810         {\r
 811     BaseType_t xRunningPrivileged = prvRaisePrivilege();\r
 812 \r
 813                 vTaskResume( pxTaskToResume );\r
 814         portRESET_PRIVILEGE( xRunningPrivileged );\r
 815         }\r
 816 #endif\r
 817 /*-----------------------------------------------------------*/\r
 818 \r
 819 void MPU_vTaskSuspendAll( void )\r
 820 {\r
 821 BaseType_t xRunningPrivileged = prvRaisePrivilege();\r
 822 \r
 823         vTaskSuspendAll();\r
 824     portRESET_PRIVILEGE( xRunningPrivileged );\r
 825 }\r
 826 /*-----------------------------------------------------------*/\r
 827 \r
 828 BaseType_t MPU_xTaskResumeAll( void )\r
 829 {\r
 830 BaseType_t xReturn;\r
 831 BaseType_t xRunningPrivileged = prvRaisePrivilege();\r
 832 \r
 833         xReturn = xTaskResumeAll();\r
 834     portRESET_PRIVILEGE( xRunningPrivileged );\r
 835     return xReturn;\r
 836 }\r
 837 /*-----------------------------------------------------------*/\r
 838 \r
 839 TickType_t MPU_xTaskGetTickCount( void )\r
 840 {\r
 841 TickType_t xReturn;\r
 842 BaseType_t xRunningPrivileged = prvRaisePrivilege();\r
 843 \r
 844         xReturn = xTaskGetTickCount();\r
 845     portRESET_PRIVILEGE( xRunningPrivileged );\r
 846         return xReturn;\r
 847 }\r
 848 /*-----------------------------------------------------------*/\r
 849 \r
 850 UBaseType_t MPU_uxTaskGetNumberOfTasks( void )\r
 851 {\r
 852 UBaseType_t uxReturn;\r
 853 BaseType_t xRunningPrivileged = prvRaisePrivilege();\r
 854 \r
 855         uxReturn = uxTaskGetNumberOfTasks();\r
 856     portRESET_PRIVILEGE( xRunningPrivileged );\r
 857         return uxReturn;\r
 858 }\r
 859 /*-----------------------------------------------------------*/\r
 860 \r
 861 #if ( configUSE_TRACE_FACILITY == 1 )\r
 862         void MPU_vTaskList( char *pcWriteBuffer )\r
 863         {\r
 864         BaseType_t xRunningPrivileged = prvRaisePrivilege();\r
 865 \r
 866                 vTaskList( pcWriteBuffer );\r
 867                 portRESET_PRIVILEGE( xRunningPrivileged );\r
 868         }\r
 869 #endif\r
 870 /*-----------------------------------------------------------*/\r
 871 \r
 872 #if ( configGENERATE_RUN_TIME_STATS == 1 )\r
 873         void MPU_vTaskGetRunTimeStats( char *pcWriteBuffer )\r
 874         {\r
 875     BaseType_t xRunningPrivileged = prvRaisePrivilege();\r
 876 \r
 877                 vTaskGetRunTimeStats( pcWriteBuffer );\r
 878         portRESET_PRIVILEGE( xRunningPrivileged );\r
 879         }\r
 880 #endif\r
 881 /*-----------------------------------------------------------*/\r
 882 \r
 883 #if ( configUSE_APPLICATION_TASK_TAG == 1 )\r
 884         void MPU_vTaskSetApplicationTaskTag( TaskHandle_t xTask, TaskHookFunction_t pxTagValue )\r
 885         {\r
 886     BaseType_t xRunningPrivileged = prvRaisePrivilege();\r
 887 \r
 888                 vTaskSetApplicationTaskTag( xTask, pxTagValue );\r
 889         portRESET_PRIVILEGE( xRunningPrivileged );\r
 890         }\r
 891 #endif\r
 892 /*-----------------------------------------------------------*/\r
 893 \r
 894 #if ( configUSE_APPLICATION_TASK_TAG == 1 )\r
 895         TaskHookFunction_t MPU_xTaskGetApplicationTaskTag( TaskHandle_t xTask )\r
 896         {\r
 897         TaskHookFunction_t xReturn;\r
 898     BaseType_t xRunningPrivileged = prvRaisePrivilege();\r
 899 \r
 900                 xReturn = xTaskGetApplicationTaskTag( xTask );\r
 901         portRESET_PRIVILEGE( xRunningPrivileged );\r
 902                 return xReturn;\r
 903         }\r
 904 #endif\r
 905 /*-----------------------------------------------------------*/\r
 906 \r
 907 #if ( configUSE_APPLICATION_TASK_TAG == 1 )\r
 908         BaseType_t MPU_xTaskCallApplicationTaskHook( TaskHandle_t xTask, void *pvParameter )\r
 909         {\r
 910         BaseType_t xReturn;\r
 911     BaseType_t xRunningPrivileged = prvRaisePrivilege();\r
 912 \r
 913                 xReturn = xTaskCallApplicationTaskHook( xTask, pvParameter );\r
 914         portRESET_PRIVILEGE( xRunningPrivileged );\r
 915                 return xReturn;\r
 916         }\r
 917 #endif\r
 918 /*-----------------------------------------------------------*/\r
 919 \r
 920 #if ( configUSE_TRACE_FACILITY == 1 )\r
 921         UBaseType_t MPU_uxTaskGetSystemState( TaskStatus_t *pxTaskStatusArray, UBaseType_t uxArraySize, uint32_t *pulTotalRunTime )\r
 922         {\r
 923         UBaseType_t uxReturn;\r
 924         BaseType_t xRunningPrivileged = prvRaisePrivilege();\r
 925 \r
 926                 uxReturn = uxTaskGetSystemState( pxTaskStatusArray, uxArraySize, pulTotalRunTime );\r
 927                 portRESET_PRIVILEGE( xRunningPrivileged );\r
 928                 return uxReturn;\r
 929         }\r
 930 #endif\r
 931 /*-----------------------------------------------------------*/\r
 932 \r
 933 #if ( INCLUDE_uxTaskGetStackHighWaterMark == 1 )\r
 934         UBaseType_t MPU_uxTaskGetStackHighWaterMark( TaskHandle_t xTask )\r
 935         {\r
 936         UBaseType_t uxReturn;\r
 937     BaseType_t xRunningPrivileged = prvRaisePrivilege();\r
 938 \r
 939                 uxReturn = uxTaskGetStackHighWaterMark( xTask );\r
 940         portRESET_PRIVILEGE( xRunningPrivileged );\r
 941                 return uxReturn;\r
 942         }\r
 943 #endif\r
 944 /*-----------------------------------------------------------*/\r
 945 \r
 946 #if ( INCLUDE_xTaskGetCurrentTaskHandle == 1 )\r
 947         TaskHandle_t MPU_xTaskGetCurrentTaskHandle( void )\r
 948         {\r
 949         TaskHandle_t xReturn;\r
 950     BaseType_t xRunningPrivileged = prvRaisePrivilege();\r
 951 \r
 952                 xReturn = xTaskGetCurrentTaskHandle();\r
 953         portRESET_PRIVILEGE( xRunningPrivileged );\r
 954                 return xReturn;\r
 955         }\r
 956 #endif\r
 957 /*-----------------------------------------------------------*/\r
 958 \r
 959 #if ( INCLUDE_xTaskGetSchedulerState == 1 )\r
 960         BaseType_t MPU_xTaskGetSchedulerState( void )\r
 961         {\r
 962         BaseType_t xReturn;\r
 963     BaseType_t xRunningPrivileged = prvRaisePrivilege();\r
 964 \r
 965                 xReturn = xTaskGetSchedulerState();\r
 966         portRESET_PRIVILEGE( xRunningPrivileged );\r
 967                 return xReturn;\r
 968         }\r
 969 #endif\r
 970 /*-----------------------------------------------------------*/\r
 971 \r
 972 QueueHandle_t MPU_xQueueGenericCreate( UBaseType_t uxQueueLength, UBaseType_t uxItemSize, uint8_t ucQueueType )\r
 973 {\r
 974 QueueHandle_t xReturn;\r
 975 BaseType_t xRunningPrivileged = prvRaisePrivilege();\r
 976 \r
 977         xReturn = xQueueGenericCreate( uxQueueLength, uxItemSize, ucQueueType );\r
 978         portRESET_PRIVILEGE( xRunningPrivileged );\r
 979         return xReturn;\r
 980 }\r
 981 /*-----------------------------------------------------------*/\r
 982 \r
 983 BaseType_t MPU_xQueueGenericReset( QueueHandle_t pxQueue, BaseType_t xNewQueue )\r
 984 {\r
 985 BaseType_t xReturn;\r
 986 BaseType_t xRunningPrivileged = prvRaisePrivilege();\r
 987 \r
 988         xReturn = xQueueGenericReset( pxQueue, xNewQueue );\r
 989         portRESET_PRIVILEGE( xRunningPrivileged );\r
 990         return xReturn;\r
 991 }\r
 992 /*-----------------------------------------------------------*/\r
 993 \r
 994 BaseType_t MPU_xQueueGenericSend( QueueHandle_t xQueue, const void * const pvItemToQueue, TickType_t xTicksToWait, BaseType_t xCopyPosition )\r
 995 {\r
 996 BaseType_t xReturn;\r
 997 BaseType_t xRunningPrivileged = prvRaisePrivilege();\r
 998 \r
 999         xReturn = xQueueGenericSend( xQueue, pvItemToQueue, xTicksToWait, xCopyPosition );\r
1000         portRESET_PRIVILEGE( xRunningPrivileged );\r
1001         return xReturn;\r
1002 }\r
1003 /*-----------------------------------------------------------*/\r
1004 \r
1005 UBaseType_t MPU_uxQueueMessagesWaiting( const QueueHandle_t pxQueue )\r
1006 {\r
1007 BaseType_t xRunningPrivileged = prvRaisePrivilege();\r
1008 UBaseType_t uxReturn;\r
1009 \r
1010         uxReturn = uxQueueMessagesWaiting( pxQueue );\r
1011         portRESET_PRIVILEGE( xRunningPrivileged );\r
1012         return uxReturn;\r
1013 }\r
1014 /*-----------------------------------------------------------*/\r
1015 \r
1016 BaseType_t MPU_xQueueGenericReceive( QueueHandle_t pxQueue, void * const pvBuffer, TickType_t xTicksToWait, BaseType_t xJustPeeking )\r
1017 {\r
1018 BaseType_t xRunningPrivileged = prvRaisePrivilege();\r
1019 BaseType_t xReturn;\r
1020 \r
1021         xReturn = xQueueGenericReceive( pxQueue, pvBuffer, xTicksToWait, xJustPeeking );\r
1022         portRESET_PRIVILEGE( xRunningPrivileged );\r
1023         return xReturn;\r
1024 }\r
1025 /*-----------------------------------------------------------*/\r
1026 \r
1027 BaseType_t MPU_xQueuePeekFromISR( QueueHandle_t pxQueue, void * const pvBuffer )\r
1028 {\r
1029 BaseType_t xRunningPrivileged = prvRaisePrivilege();\r
1030 BaseType_t xReturn;\r
1031 \r
1032         xReturn = xQueuePeekFromISR( pxQueue, pvBuffer );\r
1033         portRESET_PRIVILEGE( xRunningPrivileged );\r
1034         return xReturn;\r
1035 }\r
1036 /*-----------------------------------------------------------*/\r
1037 \r
1038 void* MPU_xQueueGetMutexHolder( QueueHandle_t xSemaphore )\r
1039 {\r
1040 BaseType_t xRunningPrivileged = prvRaisePrivilege();\r
1041 void * xReturn;\r
1042 \r
1043         xReturn = ( void * ) xQueueGetMutexHolder( xSemaphore );\r
1044         portRESET_PRIVILEGE( xRunningPrivileged );\r
1045         return xReturn;\r
1046 }\r
1047 /*-----------------------------------------------------------*/\r
1048 \r
1049 #if ( configUSE_MUTEXES == 1 )\r
1050         QueueHandle_t MPU_xQueueCreateMutex( void )\r
1051         {\r
1052     QueueHandle_t xReturn;\r
1053         BaseType_t xRunningPrivileged = prvRaisePrivilege();\r
1054 \r
1055                 xReturn = xQueueCreateMutex( queueQUEUE_TYPE_MUTEX );\r
1056                 portRESET_PRIVILEGE( xRunningPrivileged );\r
1057                 return xReturn;\r
1058         }\r
1059 #endif\r
1060 /*-----------------------------------------------------------*/\r
1061 \r
1062 #if configUSE_COUNTING_SEMAPHORES == 1\r
1063         QueueHandle_t MPU_xQueueCreateCountingSemaphore( UBaseType_t uxCountValue, UBaseType_t uxInitialCount )\r
1064         {\r
1065     QueueHandle_t xReturn;\r
1066         BaseType_t xRunningPrivileged = prvRaisePrivilege();\r
1067 \r
1068                 xReturn = xQueueCreateCountingSemaphore( uxCountValue, uxInitialCount );\r
1069                 portRESET_PRIVILEGE( xRunningPrivileged );\r
1070                 return xReturn;\r
1071         }\r
1072 #endif\r
1073 /*-----------------------------------------------------------*/\r
1074 \r
1075 #if ( configUSE_MUTEXES == 1 )\r
1076         BaseType_t MPU_xQueueTakeMutexRecursive( QueueHandle_t xMutex, TickType_t xBlockTime )\r
1077         {\r
1078         BaseType_t xReturn;\r
1079         BaseType_t xRunningPrivileged = prvRaisePrivilege();\r
1080 \r
1081                 xReturn = xQueueTakeMutexRecursive( xMutex, xBlockTime );\r
1082                 portRESET_PRIVILEGE( xRunningPrivileged );\r
1083                 return xReturn;\r
1084         }\r
1085 #endif\r
1086 /*-----------------------------------------------------------*/\r
1087 \r
1088 #if ( configUSE_MUTEXES == 1 )\r
1089         BaseType_t MPU_xQueueGiveMutexRecursive( QueueHandle_t xMutex )\r
1090         {\r
1091         BaseType_t xReturn;\r
1092         BaseType_t xRunningPrivileged = prvRaisePrivilege();\r
1093 \r
1094                 xReturn = xQueueGiveMutexRecursive( xMutex );\r
1095                 portRESET_PRIVILEGE( xRunningPrivileged );\r
1096                 return xReturn;\r
1097         }\r
1098 #endif\r
1099 /*-----------------------------------------------------------*/\r
1100 \r
1101 #if ( configUSE_QUEUE_SETS == 1 )\r
1102         QueueSetHandle_t MPU_xQueueCreateSet( UBaseType_t uxEventQueueLength )\r
1103         {\r
1104         QueueSetHandle_t xReturn;\r
1105         BaseType_t xRunningPrivileged = prvRaisePrivilege();\r
1106 \r
1107                 xReturn = xQueueCreateSet( uxEventQueueLength );\r
1108                 portRESET_PRIVILEGE( xRunningPrivileged );\r
1109                 return xReturn;\r
1110         }\r
1111 #endif\r
1112 /*-----------------------------------------------------------*/\r
1113 \r
1114 #if ( configUSE_QUEUE_SETS == 1 )\r
1115         QueueSetMemberHandle_t MPU_xQueueSelectFromSet( QueueSetHandle_t xQueueSet, TickType_t xBlockTimeTicks )\r
1116         {\r
1117         QueueSetMemberHandle_t xReturn;\r
1118         BaseType_t xRunningPrivileged = prvRaisePrivilege();\r
1119 \r
1120                 xReturn = xQueueSelectFromSet( xQueueSet, xBlockTimeTicks );\r
1121                 portRESET_PRIVILEGE( xRunningPrivileged );\r
1122                 return xReturn;\r
1123         }\r
1124 #endif\r
1125 /*-----------------------------------------------------------*/\r
1126 \r
1127 #if ( configUSE_QUEUE_SETS == 1 )\r
1128         BaseType_t MPU_xQueueAddToSet( QueueSetMemberHandle_t xQueueOrSemaphore, QueueSetHandle_t xQueueSet )\r
1129         {\r
1130         BaseType_t xReturn;\r
1131         BaseType_t xRunningPrivileged = prvRaisePrivilege();\r
1132 \r
1133                 xReturn = xQueueAddToSet( xQueueOrSemaphore, xQueueSet );\r
1134                 portRESET_PRIVILEGE( xRunningPrivileged );\r
1135                 return xReturn;\r
1136         }\r
1137 #endif\r
1138 /*-----------------------------------------------------------*/\r
1139 \r
1140 #if ( configUSE_QUEUE_SETS == 1 )\r
1141         BaseType_t MPU_xQueueRemoveFromSet( QueueSetMemberHandle_t xQueueOrSemaphore, QueueSetHandle_t xQueueSet )\r
1142         {\r
1143         BaseType_t xReturn;\r
1144         BaseType_t xRunningPrivileged = prvRaisePrivilege();\r
1145 \r
1146                 xReturn = xQueueRemoveFromSet( xQueueOrSemaphore, xQueueSet );\r
1147                 portRESET_PRIVILEGE( xRunningPrivileged );\r
1148                 return xReturn;\r
1149         }\r
1150 #endif\r
1151 /*-----------------------------------------------------------*/\r
1152 \r
1153 #if configQUEUE_REGISTRY_SIZE > 0\r
1154         void MPU_vQueueAddToRegistry( QueueHandle_t xQueue, char *pcName )\r
1155         {\r
1156         BaseType_t xRunningPrivileged = prvRaisePrivilege();\r
1157 \r
1158                 vQueueAddToRegistry( xQueue, pcName );\r
1159 \r
1160                 portRESET_PRIVILEGE( xRunningPrivileged );\r
1161         }\r
1162 #endif\r
1163 /*-----------------------------------------------------------*/\r
1164 \r
1165 void MPU_vQueueDelete( QueueHandle_t xQueue )\r
1166 {\r
1167 BaseType_t xRunningPrivileged = prvRaisePrivilege();\r
1168 \r
1169         vQueueDelete( xQueue );\r
1170 \r
1171         portRESET_PRIVILEGE( xRunningPrivileged );\r
1172 }\r
1173 /*-----------------------------------------------------------*/\r
1174 \r
1175 #if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )\r
1176 \r
1177         void *MPU_pvPortMalloc( size_t xSize )\r
1178         {\r
1179         void *pvReturn;\r
1180         BaseType_t xRunningPrivileged = prvRaisePrivilege();\r
1181 \r
1182                 pvReturn = pvPortMalloc( xSize );\r
1183 \r
1184                 portRESET_PRIVILEGE( xRunningPrivileged );\r
1185 \r
1186                 return pvReturn;\r
1187         }\r
1188 \r
1189 #endif /* configSUPPORT_DYNAMIC_ALLOCATION */\r
1190 /*-----------------------------------------------------------*/\r
1191 \r
1192 #if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )\r
1193 \r
1194         void MPU_vPortFree( void *pv )\r
1195         {\r
1196         BaseType_t xRunningPrivileged = prvRaisePrivilege();\r
1197 \r
1198                 vPortFree( pv );\r
1199 \r
1200                 portRESET_PRIVILEGE( xRunningPrivileged );\r
1201         }\r
1202 \r
1203 #endif /* configSUPPORT_DYNAMIC_ALLOCATION */\r
1204 /*-----------------------------------------------------------*/\r
1205 \r
1206 void MPU_vPortInitialiseBlocks( void )\r
1207 {\r
1208 BaseType_t xRunningPrivileged = prvRaisePrivilege();\r
1209 \r
1210         vPortInitialiseBlocks();\r
1211 \r
1212         portRESET_PRIVILEGE( xRunningPrivileged );\r
1213 }\r
1214 /*-----------------------------------------------------------*/\r
1215 \r
1216 size_t MPU_xPortGetFreeHeapSize( void )\r
1217 {\r
1218 size_t xReturn;\r
1219 BaseType_t xRunningPrivileged = prvRaisePrivilege();\r
1220 \r
1221         xReturn = xPortGetFreeHeapSize();\r
1222 \r
1223         portRESET_PRIVILEGE( xRunningPrivileged );\r
1224 \r
1225         return xReturn;\r
1226 }\r
1227 \r
1228 /* Functions that the application writer wants to execute in privileged mode\r
1229 can be defined in application_defined_privileged_functions.h.  The functions\r
1230 must take the same format as those above whereby the privilege state on exit\r
1231 equals the privilege state on entry.  For example:\r
1232 \r
1233 void MPU_FunctionName( [parameters ] )\r
1234 {\r
1235 BaseType_t xRunningPrivileged = prvRaisePrivilege();\r
1236 \r
1237         FunctionName( [parameters ] );\r
1238 \r
1239         portRESET_PRIVILEGE( xRunningPrivileged );\r
1240 }\r
1241 */\r
1242 \r
1243 #if configINCLUDE_APPLICATION_DEFINED_PRIVILEGED_FUNCTIONS == 1\r
1244         #include "application_defined_privileged_functions.h"\r
1245 #endif\r
1246 \r