2 * FreeRTOS Kernel V10.1.0
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3 * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved.
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5 * Permission is hereby granted, free of charge, to any person obtaining a copy of
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6 * this software and associated documentation files (the "Software"), to deal in
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7 * the Software without restriction, including without limitation the rights to
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8 * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
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9 * the Software, and to permit persons to whom the Software is furnished to do so,
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10 * subject to the following conditions:
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12 * The above copyright notice and this permission notice shall be included in all
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13 * copies or substantial portions of the Software.
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15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
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17 * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
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18 * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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19 * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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20 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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22 * http://www.FreeRTOS.org
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23 * http://aws.amazon.com/freertos
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25 * 1 tab == 4 spaces!
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28 /*-----------------------------------------------------------
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29 * Implementation of functions defined in portable.h for the ARM CM3 port.
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30 *----------------------------------------------------------*/
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32 /* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
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33 all the API functions to use the MPU wrappers. That should only be done when
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34 task.h is included from an application file. */
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35 #define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
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37 /* Scheduler includes. */
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38 #include "FreeRTOS.h"
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41 #undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
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43 #ifndef configSYSTICK_CLOCK_HZ
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44 #define configSYSTICK_CLOCK_HZ configCPU_CLOCK_HZ
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45 /* Ensure the SysTick is clocked at the same frequency as the core. */
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46 #define portNVIC_SYSTICK_CLK ( 1UL << 2UL )
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48 /* The way the SysTick is clocked is not modified in case it is not the same
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50 #define portNVIC_SYSTICK_CLK ( 0 )
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53 /* Constants required to access and manipulate the NVIC. */
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54 #define portNVIC_SYSTICK_CTRL_REG ( * ( ( volatile uint32_t * ) 0xe000e010 ) )
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55 #define portNVIC_SYSTICK_LOAD_REG ( * ( ( volatile uint32_t * ) 0xe000e014 ) )
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56 #define portNVIC_SYSTICK_CURRENT_VALUE_REG ( * ( ( volatile uint32_t * ) 0xe000e018 ) )
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57 #define portNVIC_SYSPRI2_REG ( * ( ( volatile uint32_t * ) 0xe000ed20 ) )
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58 #define portNVIC_SYSPRI1_REG ( * ( ( volatile uint32_t * ) 0xe000ed1c ) )
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59 #define portNVIC_SYS_CTRL_STATE_REG ( * ( ( volatile uint32_t * ) 0xe000ed24 ) )
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60 #define portNVIC_MEM_FAULT_ENABLE ( 1UL << 16UL )
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62 /* Constants required to access and manipulate the MPU. */
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63 #define portMPU_TYPE_REG ( * ( ( volatile uint32_t * ) 0xe000ed90 ) )
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64 #define portMPU_REGION_BASE_ADDRESS_REG ( * ( ( volatile uint32_t * ) 0xe000ed9C ) )
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65 #define portMPU_REGION_ATTRIBUTE_REG ( * ( ( volatile uint32_t * ) 0xe000edA0 ) )
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66 #define portMPU_CTRL_REG ( * ( ( volatile uint32_t * ) 0xe000ed94 ) )
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67 #define portEXPECTED_MPU_TYPE_VALUE ( 8UL << 8UL ) /* 8 regions, unified. */
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68 #define portMPU_ENABLE ( 0x01UL )
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69 #define portMPU_BACKGROUND_ENABLE ( 1UL << 2UL )
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70 #define portPRIVILEGED_EXECUTION_START_ADDRESS ( 0UL )
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71 #define portMPU_REGION_VALID ( 0x10UL )
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72 #define portMPU_REGION_ENABLE ( 0x01UL )
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73 #define portPERIPHERALS_START_ADDRESS 0x40000000UL
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74 #define portPERIPHERALS_END_ADDRESS 0x5FFFFFFFUL
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76 /* Constants required to access and manipulate the SysTick. */
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77 #define portNVIC_SYSTICK_INT ( 0x00000002UL )
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78 #define portNVIC_SYSTICK_ENABLE ( 0x00000001UL )
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79 #define portNVIC_PENDSV_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL )
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80 #define portNVIC_SYSTICK_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL )
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81 #define portNVIC_SVC_PRI ( ( ( uint32_t ) configMAX_SYSCALL_INTERRUPT_PRIORITY - 1UL ) << 24UL )
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83 /* Constants required to set up the initial stack. */
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84 #define portINITIAL_XPSR ( 0x01000000 )
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85 #define portINITIAL_CONTROL_IF_UNPRIVILEGED ( 0x03 )
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86 #define portINITIAL_CONTROL_IF_PRIVILEGED ( 0x02 )
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88 /* Constants required to check the validity of an interrupt priority. */
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89 #define portFIRST_USER_INTERRUPT_NUMBER ( 16 )
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90 #define portNVIC_IP_REGISTERS_OFFSET_16 ( 0xE000E3F0 )
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91 #define portAIRCR_REG ( * ( ( volatile uint32_t * ) 0xE000ED0C ) )
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92 #define portMAX_8_BIT_VALUE ( ( uint8_t ) 0xff )
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93 #define portTOP_BIT_OF_BYTE ( ( uint8_t ) 0x80 )
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94 #define portMAX_PRIGROUP_BITS ( ( uint8_t ) 7 )
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95 #define portPRIORITY_GROUP_MASK ( 0x07UL << 8UL )
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96 #define portPRIGROUP_SHIFT ( 8UL )
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98 /* Offsets in the stack to the parameters when inside the SVC handler. */
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99 #define portOFFSET_TO_PC ( 6 )
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101 /* For strict compliance with the Cortex-M spec the task start address should
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102 have bit-0 clear, as it is loaded into the PC on exit from an ISR. */
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103 #define portSTART_ADDRESS_MASK ( ( StackType_t ) 0xfffffffeUL )
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106 * Configure a number of standard MPU regions that are used by all tasks.
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108 static void prvSetupMPU( void ) PRIVILEGED_FUNCTION;
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111 * Return the smallest MPU region size that a given number of bytes will fit
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112 * into. The region size is returned as the value that should be programmed
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113 * into the region attribute register for that region.
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115 static uint32_t prvGetMPURegionSizeSetting( uint32_t ulActualSizeInBytes ) PRIVILEGED_FUNCTION;
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118 * Checks to see if being called from the context of an unprivileged task, and
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119 * if so raises the privilege level and returns false - otherwise does nothing
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120 * other than return true.
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122 BaseType_t xPortRaisePrivilege( void ) __attribute__(( naked ));
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125 * Setup the timer to generate the tick interrupts. The implementation in this
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126 * file is weak to allow application writers to change the timer used to
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127 * generate the tick interrupt.
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129 void vPortSetupTimerInterrupt( void );
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132 * Standard FreeRTOS exception handlers.
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134 void xPortPendSVHandler( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
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135 void xPortSysTickHandler( void ) __attribute__ ((optimize("3"))) PRIVILEGED_FUNCTION;
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136 void vPortSVCHandler( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
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139 * Starts the scheduler by restoring the context of the first task to run.
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141 static void prvRestoreContextOfFirstTask( void ) __attribute__(( naked )) PRIVILEGED_FUNCTION;
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144 * C portion of the SVC handler. The SVC handler is split between an asm entry
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145 * and a C wrapper for simplicity of coding and maintenance.
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147 static void prvSVCHandler( uint32_t *pulRegisters ) __attribute__(( noinline )) PRIVILEGED_FUNCTION;
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149 /*-----------------------------------------------------------*/
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151 /* Each task maintains its own interrupt status in the critical nesting
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152 variable. Note this is not saved as part of the task context as context
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153 switches can only occur when uxCriticalNesting is zero. */
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154 static UBaseType_t uxCriticalNesting = 0xaaaaaaaa;
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157 * Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure
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158 * FreeRTOS API functions are not called from interrupts that have been assigned
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159 * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY.
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161 #if ( configASSERT_DEFINED == 1 )
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162 static uint8_t ucMaxSysCallPriority = 0;
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163 static uint32_t ulMaxPRIGROUPValue = 0;
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164 static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const volatile uint8_t * const ) portNVIC_IP_REGISTERS_OFFSET_16;
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165 #endif /* configASSERT_DEFINED */
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167 /*-----------------------------------------------------------*/
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170 * See header file for description.
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172 StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters, BaseType_t xRunPrivileged )
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174 /* Simulate the stack frame as it would be created by a context switch
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176 pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
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177 *pxTopOfStack = portINITIAL_XPSR; /* xPSR */
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179 *pxTopOfStack = ( ( StackType_t ) pxCode ) & portSTART_ADDRESS_MASK; /* PC */
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181 *pxTopOfStack = 0; /* LR */
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182 pxTopOfStack -= 5; /* R12, R3, R2 and R1. */
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183 *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
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184 pxTopOfStack -= 9; /* R11, R10, R9, R8, R7, R6, R5 and R4. */
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186 if( xRunPrivileged == pdTRUE )
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188 *pxTopOfStack = portINITIAL_CONTROL_IF_PRIVILEGED;
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192 *pxTopOfStack = portINITIAL_CONTROL_IF_UNPRIVILEGED;
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195 return pxTopOfStack;
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197 /*-----------------------------------------------------------*/
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199 void vPortSVCHandler( void )
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201 /* Assumes psp was in use. */
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204 #ifndef USE_PROCESS_STACK /* Code should not be required if a main() is using the process stack. */
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207 " mrseq r0, msp \n"
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208 " mrsne r0, psp \n"
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213 ::"i"(prvSVCHandler):"r0", "memory"
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216 /*-----------------------------------------------------------*/
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218 static void prvSVCHandler( uint32_t *pulParam )
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220 uint8_t ucSVCNumber;
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222 /* The stack contains: r0, r1, r2, r3, r12, r14, the return address and
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223 xPSR. The first argument (r0) is pulParam[ 0 ]. */
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224 ucSVCNumber = ( ( uint8_t * ) pulParam[ portOFFSET_TO_PC ] )[ -2 ];
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225 switch( ucSVCNumber )
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227 case portSVC_START_SCHEDULER : portNVIC_SYSPRI1_REG |= portNVIC_SVC_PRI;
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228 prvRestoreContextOfFirstTask();
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231 case portSVC_YIELD : portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
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232 /* Barriers are normally not required
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233 but do ensure the code is completely
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234 within the specified behaviour for the
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236 __asm volatile( "dsb" ::: "memory" );
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237 __asm volatile( "isb" );
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241 case portSVC_RAISE_PRIVILEGE : __asm volatile
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243 " mrs r1, control \n" /* Obtain current control value. */
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244 " bic r1, #1 \n" /* Set privilege bit. */
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245 " msr control, r1 \n" /* Write back new control value. */
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250 default : /* Unknown SVC call. */
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254 /*-----------------------------------------------------------*/
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256 static void prvRestoreContextOfFirstTask( void )
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260 " ldr r0, =0xE000ED08 \n" /* Use the NVIC offset register to locate the stack. */
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263 " msr msp, r0 \n" /* Set the msp back to the start of the stack. */
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264 " ldr r3, pxCurrentTCBConst2 \n" /* Restore the context. */
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266 " ldr r0, [r1] \n" /* The first item in the TCB is the task top of stack. */
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267 " add r1, r1, #4 \n" /* Move onto the second item in the TCB... */
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268 " ldr r2, =0xe000ed9c \n" /* Region Base Address register. */
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269 " ldmia r1!, {r4-r11} \n" /* Read 4 sets of MPU registers. */
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270 " stmia r2!, {r4-r11} \n" /* Write 4 sets of MPU registers. */
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271 " ldmia r0!, {r3, r4-r11} \n" /* Pop the registers that are not automatically saved on exception entry. */
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272 " msr control, r3 \n"
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273 " msr psp, r0 \n" /* Restore the task stack pointer. */
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275 " msr basepri, r0 \n"
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276 " ldr r14, =0xfffffffd \n" /* Load exec return code. */
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280 "pxCurrentTCBConst2: .word pxCurrentTCB \n"
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283 /*-----------------------------------------------------------*/
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286 * See header file for description.
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288 BaseType_t xPortStartScheduler( void )
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290 /* configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0. See
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291 http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
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292 configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) );
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294 #if( configASSERT_DEFINED == 1 )
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296 volatile uint32_t ulOriginalPriority;
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297 volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER );
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298 volatile uint8_t ucMaxPriorityValue;
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300 /* Determine the maximum priority from which ISR safe FreeRTOS API
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301 functions can be called. ISR safe functions are those that end in
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302 "FromISR". FreeRTOS maintains separate thread and ISR API functions to
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303 ensure interrupt entry is as fast and simple as possible.
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305 Save the interrupt priority value that is about to be clobbered. */
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306 ulOriginalPriority = *pucFirstUserPriorityRegister;
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308 /* Determine the number of priority bits available. First write to all
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310 *pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;
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312 /* Read the value back to see how many bits stuck. */
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313 ucMaxPriorityValue = *pucFirstUserPriorityRegister;
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315 /* Use the same mask on the maximum system call priority. */
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316 ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;
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318 /* Calculate the maximum acceptable priority group value for the number
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319 of bits read back. */
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320 ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;
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321 while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
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323 ulMaxPRIGROUPValue--;
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324 ucMaxPriorityValue <<= ( uint8_t ) 0x01;
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327 #ifdef __NVIC_PRIO_BITS
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329 /* Check the CMSIS configuration that defines the number of
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330 priority bits matches the number of priority bits actually queried
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331 from the hardware. */
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332 configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == __NVIC_PRIO_BITS );
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336 #ifdef configPRIO_BITS
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338 /* Check the FreeRTOS configuration that defines the number of
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339 priority bits matches the number of priority bits actually queried
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340 from the hardware. */
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341 configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == configPRIO_BITS );
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345 /* Shift the priority group value back to its position within the AIRCR
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347 ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;
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348 ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;
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350 /* Restore the clobbered interrupt priority register to its original
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352 *pucFirstUserPriorityRegister = ulOriginalPriority;
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354 #endif /* conifgASSERT_DEFINED */
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356 /* Make PendSV and SysTick the same priority as the kernel, and the SVC
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357 handler higher priority so it can be used to exit a critical section (where
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358 lower priorities are masked). */
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359 portNVIC_SYSPRI2_REG |= portNVIC_PENDSV_PRI;
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360 portNVIC_SYSPRI2_REG |= portNVIC_SYSTICK_PRI;
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362 /* Configure the regions in the MPU that are common to all tasks. */
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365 /* Start the timer that generates the tick ISR. Interrupts are disabled
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367 vPortSetupTimerInterrupt();
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369 /* Initialise the critical nesting count ready for the first task. */
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370 uxCriticalNesting = 0;
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372 /* Start the first task. */
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374 " ldr r0, =0xE000ED08 \n" /* Use the NVIC offset register to locate the stack. */
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377 " msr msp, r0 \n" /* Set the msp back to the start of the stack. */
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378 " cpsie i \n" /* Globally enable interrupts. */
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382 " svc %0 \n" /* System call to start first task. */
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384 :: "i" (portSVC_START_SCHEDULER) : "memory" );
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386 /* Should not get here! */
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389 /*-----------------------------------------------------------*/
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391 void vPortEndScheduler( void )
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393 /* Not implemented in ports where there is nothing to return to.
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394 Artificially force an assert. */
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395 configASSERT( uxCriticalNesting == 1000UL );
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397 /*-----------------------------------------------------------*/
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399 void vPortEnterCritical( void )
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401 BaseType_t xRunningPrivileged = xPortRaisePrivilege();
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403 portDISABLE_INTERRUPTS();
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404 uxCriticalNesting++;
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406 vPortResetPrivilege( xRunningPrivileged );
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408 /*-----------------------------------------------------------*/
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410 void vPortExitCritical( void )
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412 BaseType_t xRunningPrivileged = xPortRaisePrivilege();
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414 configASSERT( uxCriticalNesting );
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415 uxCriticalNesting--;
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416 if( uxCriticalNesting == 0 )
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418 portENABLE_INTERRUPTS();
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420 vPortResetPrivilege( xRunningPrivileged );
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422 /*-----------------------------------------------------------*/
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424 void xPortPendSVHandler( void )
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426 /* This is a naked function. */
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432 " ldr r3, pxCurrentTCBConst \n" /* Get the location of the current TCB. */
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435 " mrs r1, control \n"
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436 " stmdb r0!, {r1, r4-r11} \n" /* Save the remaining registers. */
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437 " str r0, [r2] \n" /* Save the new top of stack into the first member of the TCB. */
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439 " stmdb sp!, {r3, r14} \n"
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441 " msr basepri, r0 \n"
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444 " bl vTaskSwitchContext \n"
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446 " msr basepri, r0 \n"
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447 " ldmia sp!, {r3, r14} \n"
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448 " \n" /* Restore the context. */
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450 " ldr r0, [r1] \n" /* The first item in the TCB is the task top of stack. */
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451 " add r1, r1, #4 \n" /* Move onto the second item in the TCB... */
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452 " ldr r2, =0xe000ed9c \n" /* Region Base Address register. */
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453 " ldmia r1!, {r4-r11} \n" /* Read 4 sets of MPU registers. */
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454 " stmia r2!, {r4-r11} \n" /* Write 4 sets of MPU registers. */
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455 " ldmia r0!, {r3, r4-r11} \n" /* Pop the registers that are not automatically saved on exception entry. */
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456 " msr control, r3 \n"
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462 "pxCurrentTCBConst: .word pxCurrentTCB \n"
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463 ::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY)
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466 /*-----------------------------------------------------------*/
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468 void xPortSysTickHandler( void )
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472 ulDummy = portSET_INTERRUPT_MASK_FROM_ISR();
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474 /* Increment the RTOS tick. */
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475 if( xTaskIncrementTick() != pdFALSE )
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477 /* Pend a context switch. */
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478 portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
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481 portCLEAR_INTERRUPT_MASK_FROM_ISR( ulDummy );
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483 /*-----------------------------------------------------------*/
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486 * Setup the systick timer to generate the tick interrupts at the required
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489 __attribute__(( weak )) void vPortSetupTimerInterrupt( void )
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491 /* Stop and clear the SysTick. */
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492 portNVIC_SYSTICK_CTRL_REG = 0UL;
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493 portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
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495 /* Configure SysTick to interrupt at the requested rate. */
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496 portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
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497 portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK | portNVIC_SYSTICK_INT | portNVIC_SYSTICK_ENABLE );
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499 /*-----------------------------------------------------------*/
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501 static void prvSetupMPU( void )
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503 extern uint32_t __privileged_functions_end__[];
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504 extern uint32_t __FLASH_segment_start__[];
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505 extern uint32_t __FLASH_segment_end__[];
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506 extern uint32_t __privileged_data_start__[];
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507 extern uint32_t __privileged_data_end__[];
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509 /* Check the expected MPU is present. */
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510 if( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE )
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512 /* First setup the entire flash for unprivileged read only access. */
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513 portMPU_REGION_BASE_ADDRESS_REG = ( ( uint32_t ) __FLASH_segment_start__ ) | /* Base address. */
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514 ( portMPU_REGION_VALID ) |
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515 ( portUNPRIVILEGED_FLASH_REGION );
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517 portMPU_REGION_ATTRIBUTE_REG = ( portMPU_REGION_READ_ONLY ) |
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518 ( portMPU_REGION_CACHEABLE_BUFFERABLE ) |
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519 ( prvGetMPURegionSizeSetting( ( uint32_t ) __FLASH_segment_end__ - ( uint32_t ) __FLASH_segment_start__ ) ) |
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520 ( portMPU_REGION_ENABLE );
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522 /* Setup the first 16K for privileged only access (even though less
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523 than 10K is actually being used). This is where the kernel code is
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525 portMPU_REGION_BASE_ADDRESS_REG = ( ( uint32_t ) __FLASH_segment_start__ ) | /* Base address. */
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526 ( portMPU_REGION_VALID ) |
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527 ( portPRIVILEGED_FLASH_REGION );
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529 portMPU_REGION_ATTRIBUTE_REG = ( portMPU_REGION_PRIVILEGED_READ_ONLY ) |
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530 ( portMPU_REGION_CACHEABLE_BUFFERABLE ) |
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531 ( prvGetMPURegionSizeSetting( ( uint32_t ) __privileged_functions_end__ - ( uint32_t ) __FLASH_segment_start__ ) ) |
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532 ( portMPU_REGION_ENABLE );
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534 /* Setup the privileged data RAM region. This is where the kernel data
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536 portMPU_REGION_BASE_ADDRESS_REG = ( ( uint32_t ) __privileged_data_start__ ) | /* Base address. */
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537 ( portMPU_REGION_VALID ) |
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538 ( portPRIVILEGED_RAM_REGION );
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540 portMPU_REGION_ATTRIBUTE_REG = ( portMPU_REGION_PRIVILEGED_READ_WRITE ) |
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541 ( portMPU_REGION_CACHEABLE_BUFFERABLE ) |
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542 prvGetMPURegionSizeSetting( ( uint32_t ) __privileged_data_end__ - ( uint32_t ) __privileged_data_start__ ) |
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543 ( portMPU_REGION_ENABLE );
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545 /* By default allow everything to access the general peripherals. The
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546 system peripherals and registers are protected. */
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547 portMPU_REGION_BASE_ADDRESS_REG = ( portPERIPHERALS_START_ADDRESS ) |
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548 ( portMPU_REGION_VALID ) |
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549 ( portGENERAL_PERIPHERALS_REGION );
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551 portMPU_REGION_ATTRIBUTE_REG = ( portMPU_REGION_READ_WRITE | portMPU_REGION_EXECUTE_NEVER ) |
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552 ( prvGetMPURegionSizeSetting( portPERIPHERALS_END_ADDRESS - portPERIPHERALS_START_ADDRESS ) ) |
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553 ( portMPU_REGION_ENABLE );
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555 /* Enable the memory fault exception. */
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556 portNVIC_SYS_CTRL_STATE_REG |= portNVIC_MEM_FAULT_ENABLE;
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558 /* Enable the MPU with the background region configured. */
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559 portMPU_CTRL_REG |= ( portMPU_ENABLE | portMPU_BACKGROUND_ENABLE );
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562 /*-----------------------------------------------------------*/
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564 static uint32_t prvGetMPURegionSizeSetting( uint32_t ulActualSizeInBytes )
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566 uint32_t ulRegionSize, ulReturnValue = 4;
\r
568 /* 32 is the smallest region size, 31 is the largest valid value for
\r
570 for( ulRegionSize = 32UL; ulReturnValue < 31UL; ( ulRegionSize <<= 1UL ) )
\r
572 if( ulActualSizeInBytes <= ulRegionSize )
\r
582 /* Shift the code by one before returning so it can be written directly
\r
583 into the the correct bit position of the attribute register. */
\r
584 return ( ulReturnValue << 1UL );
\r
586 /*-----------------------------------------------------------*/
\r
588 BaseType_t xPortRaisePrivilege( void )
\r
592 " mrs r0, control \n"
\r
593 " tst r0, #1 \n" /* Is the task running privileged? */
\r
595 " movne r0, #0 \n" /* CONTROL[0]!=0, return false. */
\r
596 " svcne %0 \n" /* Switch to privileged. */
\r
597 " moveq r0, #1 \n" /* CONTROL[0]==0, return true. */
\r
599 :: "i" (portSVC_RAISE_PRIVILEGE) : "r0", "memory"
\r
604 /*-----------------------------------------------------------*/
\r
606 void vPortStoreTaskMPUSettings( xMPU_SETTINGS *xMPUSettings, const struct xMEMORY_REGION * const xRegions, StackType_t *pxBottomOfStack, uint32_t ulStackDepth )
\r
608 extern uint32_t __SRAM_segment_start__[];
\r
609 extern uint32_t __SRAM_segment_end__[];
\r
610 extern uint32_t __privileged_data_start__[];
\r
611 extern uint32_t __privileged_data_end__[];
\r
615 if( xRegions == NULL )
\r
617 /* No MPU regions are specified so allow access to all RAM. */
\r
618 xMPUSettings->xRegion[ 0 ].ulRegionBaseAddress =
\r
619 ( ( uint32_t ) __SRAM_segment_start__ ) | /* Base address. */
\r
620 ( portMPU_REGION_VALID ) |
\r
621 ( portSTACK_REGION );
\r
623 xMPUSettings->xRegion[ 0 ].ulRegionAttribute =
\r
624 ( portMPU_REGION_READ_WRITE ) |
\r
625 ( portMPU_REGION_CACHEABLE_BUFFERABLE ) |
\r
626 ( prvGetMPURegionSizeSetting( ( uint32_t ) __SRAM_segment_end__ - ( uint32_t ) __SRAM_segment_start__ ) ) |
\r
627 ( portMPU_REGION_ENABLE );
\r
629 /* Re-instate the privileged only RAM region as xRegion[ 0 ] will have
\r
630 just removed the privileged only parameters. */
\r
631 xMPUSettings->xRegion[ 1 ].ulRegionBaseAddress =
\r
632 ( ( uint32_t ) __privileged_data_start__ ) | /* Base address. */
\r
633 ( portMPU_REGION_VALID ) |
\r
634 ( portSTACK_REGION + 1 );
\r
636 xMPUSettings->xRegion[ 1 ].ulRegionAttribute =
\r
637 ( portMPU_REGION_PRIVILEGED_READ_WRITE ) |
\r
638 ( portMPU_REGION_CACHEABLE_BUFFERABLE ) |
\r
639 prvGetMPURegionSizeSetting( ( uint32_t ) __privileged_data_end__ - ( uint32_t ) __privileged_data_start__ ) |
\r
640 ( portMPU_REGION_ENABLE );
\r
642 /* Invalidate all other regions. */
\r
643 for( ul = 2; ul <= portNUM_CONFIGURABLE_REGIONS; ul++ )
\r
645 xMPUSettings->xRegion[ ul ].ulRegionBaseAddress = ( portSTACK_REGION + ul ) | portMPU_REGION_VALID;
\r
646 xMPUSettings->xRegion[ ul ].ulRegionAttribute = 0UL;
\r
651 /* This function is called automatically when the task is created - in
\r
652 which case the stack region parameters will be valid. At all other
\r
653 times the stack parameters will not be valid and it is assumed that the
\r
654 stack region has already been configured. */
\r
655 if( ulStackDepth > 0 )
\r
657 /* Define the region that allows access to the stack. */
\r
658 xMPUSettings->xRegion[ 0 ].ulRegionBaseAddress =
\r
659 ( ( uint32_t ) pxBottomOfStack ) |
\r
660 ( portMPU_REGION_VALID ) |
\r
661 ( portSTACK_REGION ); /* Region number. */
\r
663 xMPUSettings->xRegion[ 0 ].ulRegionAttribute =
\r
664 ( portMPU_REGION_READ_WRITE ) | /* Read and write. */
\r
665 ( prvGetMPURegionSizeSetting( ulStackDepth * ( uint32_t ) sizeof( StackType_t ) ) ) |
\r
666 ( portMPU_REGION_CACHEABLE_BUFFERABLE ) |
\r
667 ( portMPU_REGION_ENABLE );
\r
672 for( ul = 1; ul <= portNUM_CONFIGURABLE_REGIONS; ul++ )
\r
674 if( ( xRegions[ lIndex ] ).ulLengthInBytes > 0UL )
\r
676 /* Translate the generic region definition contained in
\r
677 xRegions into the CM3 specific MPU settings that are then
\r
678 stored in xMPUSettings. */
\r
679 xMPUSettings->xRegion[ ul ].ulRegionBaseAddress =
\r
680 ( ( uint32_t ) xRegions[ lIndex ].pvBaseAddress ) |
\r
681 ( portMPU_REGION_VALID ) |
\r
682 ( portSTACK_REGION + ul ); /* Region number. */
\r
684 xMPUSettings->xRegion[ ul ].ulRegionAttribute =
\r
685 ( prvGetMPURegionSizeSetting( xRegions[ lIndex ].ulLengthInBytes ) ) |
\r
686 ( xRegions[ lIndex ].ulParameters ) |
\r
687 ( portMPU_REGION_ENABLE );
\r
691 /* Invalidate the region. */
\r
692 xMPUSettings->xRegion[ ul ].ulRegionBaseAddress = ( portSTACK_REGION + ul ) | portMPU_REGION_VALID;
\r
693 xMPUSettings->xRegion[ ul ].ulRegionAttribute = 0UL;
\r
700 /*-----------------------------------------------------------*/
\r
702 #if( configASSERT_DEFINED == 1 )
\r
704 void vPortValidateInterruptPriority( void )
\r
706 uint32_t ulCurrentInterrupt;
\r
707 uint8_t ucCurrentPriority;
\r
709 /* Obtain the number of the currently executing interrupt. */
\r
710 __asm volatile( "mrs %0, ipsr" : "=r"( ulCurrentInterrupt ) :: "memory" );
\r
712 /* Is the interrupt number a user defined interrupt? */
\r
713 if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER )
\r
715 /* Look up the interrupt's priority. */
\r
716 ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ];
\r
718 /* The following assertion will fail if a service routine (ISR) for
\r
719 an interrupt that has been assigned a priority above
\r
720 configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API
\r
721 function. ISR safe FreeRTOS API functions must *only* be called
\r
722 from interrupts that have been assigned a priority at or below
\r
723 configMAX_SYSCALL_INTERRUPT_PRIORITY.
\r
725 Numerically low interrupt priority numbers represent logically high
\r
726 interrupt priorities, therefore the priority of the interrupt must
\r
727 be set to a value equal to or numerically *higher* than
\r
728 configMAX_SYSCALL_INTERRUPT_PRIORITY.
\r
730 Interrupts that use the FreeRTOS API must not be left at their
\r
731 default priority of zero as that is the highest possible priority,
\r
732 which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY,
\r
733 and therefore also guaranteed to be invalid.
\r
735 FreeRTOS maintains separate thread and ISR API functions to ensure
\r
736 interrupt entry is as fast and simple as possible.
\r
738 The following links provide detailed information:
\r
739 http://www.freertos.org/RTOS-Cortex-M3-M4.html
\r
740 http://www.freertos.org/FAQHelp.html */
\r
741 configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );
\r
744 /* Priority grouping: The interrupt controller (NVIC) allows the bits
\r
745 that define each interrupt's priority to be split between bits that
\r
746 define the interrupt's pre-emption priority bits and bits that define
\r
747 the interrupt's sub-priority. For simplicity all bits must be defined
\r
748 to be pre-emption priority bits. The following assertion will fail if
\r
749 this is not the case (if some bits represent a sub-priority).
\r
751 If the application only uses CMSIS libraries for interrupt
\r
752 configuration then the correct setting can be achieved on all Cortex-M
\r
753 devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the
\r
754 scheduler. Note however that some vendor specific peripheral libraries
\r
755 assume a non-zero priority group setting, in which cases using a value
\r
756 of zero will result in unpredicable behaviour. */
\r
757 configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );
\r
760 #endif /* configASSERT_DEFINED */
\r
761 /*-----------------------------------------------------------*/
\r
projects / freertos / blob