git.sur5r.net Git - freertos/blob - FreeRTOS/Source/portable/GCC/ARM_CM3_MPU/port.c

   1 /*\r
   2     FreeRTOS V9.0.0rc2 - Copyright (C) 2016 Real Time Engineers Ltd.\r
   3     All rights reserved\r
   4 \r
   5     VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
   6 \r
   7     This file is part of the FreeRTOS distribution.\r
   8 \r
   9     FreeRTOS is free software; you can redistribute it and/or modify it under\r
  10     the terms of the GNU General Public License (version 2) as published by the\r
  11     Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception.\r
  12 \r
  13     ***************************************************************************\r
  14     >>!   NOTE: The modification to the GPL is included to allow you to     !<<\r
  15     >>!   distribute a combined work that includes FreeRTOS without being   !<<\r
  16     >>!   obliged to provide the source code for proprietary components     !<<\r
  17     >>!   outside of the FreeRTOS kernel.                                   !<<\r
  18     ***************************************************************************\r
  19 \r
  20     FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
  21     WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
  22     FOR A PARTICULAR PURPOSE.  Full license text is available on the following\r
  23     link: http://www.freertos.org/a00114.html\r
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  37     ***************************************************************************\r
  38 \r
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  40     the FAQ page "My application does not run, what could be wrong?".  Have you\r
  41     defined configASSERT()?\r
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  63     http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
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  66 \r
  67     1 tab == 4 spaces!\r
  68 */\r
  69 \r
  70 /*-----------------------------------------------------------\r
  71  * Implementation of functions defined in portable.h for the ARM CM3 port.\r
  72  *----------------------------------------------------------*/\r
  73 \r
  74 #error This port is not supported in this V9.0.0 pre-release revision, but will be supported in the final release.  For now use V8.2.3 instead.\r
  75  \r
  76 /* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining\r
  77 all the API functions to use the MPU wrappers.  That should only be done when\r
  78 task.h is included from an application file. */\r
  79 #define MPU_WRAPPERS_INCLUDED_FROM_API_FILE\r
  80 \r
  81 /* Scheduler includes. */\r
  82 #include "FreeRTOS.h"\r
  83 #include "task.h"\r
  84 #include "queue.h"\r
  85 \r
  86 #undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE\r
  87 \r
  88 /* Constants required to access and manipulate the NVIC. */\r
  89 #define portNVIC_SYSTICK_CTRL                                   ( ( volatile uint32_t * ) 0xe000e010 )\r
  90 #define portNVIC_SYSTICK_LOAD                                   ( ( volatile uint32_t * ) 0xe000e014 )\r
  91 #define portNVIC_SYSPRI2                                                ( ( volatile uint32_t * ) 0xe000ed20 )\r
  92 #define portNVIC_SYSPRI1                                                ( ( volatile uint32_t * ) 0xe000ed1c )\r
  93 #define portNVIC_SYS_CTRL_STATE                                 ( ( volatile uint32_t * ) 0xe000ed24 )\r
  94 #define portNVIC_MEM_FAULT_ENABLE                               ( 1UL << 16UL )\r
  95 \r
  96 /* Constants required to access and manipulate the MPU. */\r
  97 #define portMPU_TYPE                                                    ( ( volatile uint32_t * ) 0xe000ed90 )\r
  98 #define portMPU_REGION_BASE_ADDRESS                             ( ( volatile uint32_t * ) 0xe000ed9C )\r
  99 #define portMPU_REGION_ATTRIBUTE                                ( ( volatile uint32_t * ) 0xe000edA0 )\r
 100 #define portMPU_CTRL                                                    ( ( volatile uint32_t * ) 0xe000ed94 )\r
 101 #define portEXPECTED_MPU_TYPE_VALUE                             ( 8UL << 8UL ) /* 8 regions, unified. */\r
 102 #define portMPU_ENABLE                                                  ( 0x01UL )\r
 103 #define portMPU_BACKGROUND_ENABLE                               ( 1UL << 2UL )\r
 104 #define portPRIVILEGED_EXECUTION_START_ADDRESS  ( 0UL )\r
 105 #define portMPU_REGION_VALID                                    ( 0x10UL )\r
 106 #define portMPU_REGION_ENABLE                                   ( 0x01UL )\r
 107 #define portPERIPHERALS_START_ADDRESS                   0x40000000UL\r
 108 #define portPERIPHERALS_END_ADDRESS                             0x5FFFFFFFUL\r
 109 \r
 110 /* Constants required to access and manipulate the SysTick. */\r
 111 #define portNVIC_SYSTICK_CLK                                    ( 0x00000004UL )\r
 112 #define portNVIC_SYSTICK_INT                                    ( 0x00000002UL )\r
 113 #define portNVIC_SYSTICK_ENABLE                                 ( 0x00000001UL )\r
 114 #define portNVIC_PENDSV_PRI                                             ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL )\r
 115 #define portNVIC_SYSTICK_PRI                                    ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL )\r
 116 #define portNVIC_SVC_PRI                                                ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL )\r
 117 \r
 118 /* Constants required to set up the initial stack. */\r
 119 #define portINITIAL_XPSR                                                ( 0x01000000 )\r
 120 #define portINITIAL_CONTROL_IF_UNPRIVILEGED             ( 0x03 )\r
 121 #define portINITIAL_CONTROL_IF_PRIVILEGED               ( 0x02 )\r
 122 \r
 123 /* Offsets in the stack to the parameters when inside the SVC handler. */\r
 124 #define portOFFSET_TO_PC                                                ( 6 )\r
 125 \r
 126 /* Set the privilege level to user mode if xRunningPrivileged is false. */\r
 127 #define portRESET_PRIVILEGE( xRunningPrivileged ) if( xRunningPrivileged != pdTRUE ) __asm volatile ( " mrs r0, control \n orr r0, #1 \n msr control, r0" :::"r0" )\r
 128 \r
 129 /* Each task maintains its own interrupt status in the critical nesting\r
 130 variable.  Note this is not saved as part of the task context as context\r
 131 switches can only occur when uxCriticalNesting is zero. */\r
 132 static UBaseType_t uxCriticalNesting = 0xaaaaaaaa;\r
 133 \r
 134 /*\r
 135  * Setup the timer to generate the tick interrupts.\r
 136  */\r
 137 static void prvSetupTimerInterrupt( void ) PRIVILEGED_FUNCTION;\r
 138 \r
 139 /*\r
 140  * Configure a number of standard MPU regions that are used by all tasks.\r
 141  */\r
 142 static void prvSetupMPU( void ) PRIVILEGED_FUNCTION;\r
 143 \r
 144 /*\r
 145  * Return the smallest MPU region size that a given number of bytes will fit\r
 146  * into.  The region size is returned as the value that should be programmed\r
 147  * into the region attribute register for that region.\r
 148  */\r
 149 static uint32_t prvGetMPURegionSizeSetting( uint32_t ulActualSizeInBytes ) PRIVILEGED_FUNCTION;\r
 150 \r
 151 /*\r
 152  * Checks to see if being called from the context of an unprivileged task, and\r
 153  * if so raises the privilege level and returns false - otherwise does nothing\r
 154  * other than return true.\r
 155  */\r
 156 static BaseType_t prvRaisePrivilege( void ) __attribute__(( naked ));\r
 157 \r
 158 /*\r
 159  * Standard FreeRTOS exception handlers.\r
 160  */\r
 161 void xPortPendSVHandler( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;\r
 162 void xPortSysTickHandler( void )  __attribute__ ((optimize("3"))) PRIVILEGED_FUNCTION;\r
 163 void vPortSVCHandler( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;\r
 164 \r
 165 /*\r
 166  * Starts the scheduler by restoring the context of the first task to run.\r
 167  */\r
 168 static void prvRestoreContextOfFirstTask( void ) __attribute__(( naked )) PRIVILEGED_FUNCTION;\r
 169 \r
 170 /*\r
 171  * C portion of the SVC handler.  The SVC handler is split between an asm entry\r
 172  * and a C wrapper for simplicity of coding and maintenance.\r
 173  */\r
 174 static void prvSVCHandler( uint32_t *pulRegisters ) __attribute__(( noinline )) PRIVILEGED_FUNCTION;\r
 175 \r
 176 /*\r
 177  * Prototypes for all the MPU wrappers.\r
 178  */\r
 179 BaseType_t MPU_xTaskGenericCreate( TaskFunction_t pvTaskCode, const char * const pcName, uint16_t usStackDepth, void *pvParameters, UBaseType_t uxPriority, TaskHandle_t *pxCreatedTask, StackType_t *puxStackBuffer, const MemoryRegion_t * const xRegions );\r
 180 void MPU_vTaskAllocateMPURegions( TaskHandle_t xTask, const MemoryRegion_t * const xRegions );\r
 181 void MPU_vTaskDelete( TaskHandle_t pxTaskToDelete );\r
 182 void MPU_vTaskDelayUntil( TickType_t * const pxPreviousWakeTime, TickType_t xTimeIncrement );\r
 183 void MPU_vTaskDelay( TickType_t xTicksToDelay );\r
 184 UBaseType_t MPU_uxTaskPriorityGet( TaskHandle_t pxTask );\r
 185 void MPU_vTaskPrioritySet( TaskHandle_t pxTask, UBaseType_t uxNewPriority );\r
 186 eTaskState MPU_eTaskGetState( TaskHandle_t pxTask );\r
 187 void MPU_vTaskSuspend( TaskHandle_t pxTaskToSuspend );\r
 188 void MPU_vTaskResume( TaskHandle_t pxTaskToResume );\r
 189 void MPU_vTaskSuspendAll( void );\r
 190 BaseType_t MPU_xTaskResumeAll( void );\r
 191 TickType_t MPU_xTaskGetTickCount( void );\r
 192 UBaseType_t MPU_uxTaskGetNumberOfTasks( void );\r
 193 void MPU_vTaskList( char *pcWriteBuffer );\r
 194 void MPU_vTaskGetRunTimeStats( char *pcWriteBuffer );\r
 195 void MPU_vTaskSetApplicationTaskTag( TaskHandle_t xTask, TaskHookFunction_t pxTagValue );\r
 196 TaskHookFunction_t MPU_xTaskGetApplicationTaskTag( TaskHandle_t xTask );\r
 197 BaseType_t MPU_xTaskCallApplicationTaskHook( TaskHandle_t xTask, void *pvParameter );\r
 198 UBaseType_t MPU_uxTaskGetStackHighWaterMark( TaskHandle_t xTask );\r
 199 TaskHandle_t MPU_xTaskGetCurrentTaskHandle( void );\r
 200 BaseType_t MPU_xTaskGetSchedulerState( void );\r
 201 TaskHandle_t MPU_xTaskGetIdleTaskHandle( void );\r
 202 UBaseType_t MPU_uxTaskGetSystemState( TaskStatus_t *pxTaskStatusArray, UBaseType_t uxArraySize, uint32_t *pulTotalRunTime );\r
 203 QueueHandle_t MPU_xQueueGenericCreate( UBaseType_t uxQueueLength, UBaseType_t uxItemSize, uint8_t ucQueueType );\r
 204 BaseType_t MPU_xQueueGenericSend( QueueHandle_t xQueue, const void * const pvItemToQueue, TickType_t xTicksToWait, BaseType_t xCopyPosition );\r
 205 BaseType_t MPU_xQueueGenericReset( QueueHandle_t pxQueue, BaseType_t xNewQueue );\r
 206 UBaseType_t MPU_uxQueueMessagesWaiting( const QueueHandle_t pxQueue );\r
 207 BaseType_t MPU_xQueueGenericReceive( QueueHandle_t pxQueue, void * const pvBuffer, TickType_t xTicksToWait, BaseType_t xJustPeeking );\r
 208 QueueHandle_t MPU_xQueueCreateMutex( void );\r
 209 QueueHandle_t MPU_xQueueCreateCountingSemaphore( UBaseType_t uxCountValue, UBaseType_t uxInitialCount );\r
 210 BaseType_t MPU_xQueueTakeMutexRecursive( QueueHandle_t xMutex, TickType_t xBlockTime );\r
 211 BaseType_t MPU_xQueueGiveMutexRecursive( QueueHandle_t xMutex );\r
 212 void MPU_vQueueAddToRegistry( QueueHandle_t xQueue, char *pcName );\r
 213 void MPU_vQueueDelete( QueueHandle_t xQueue );\r
 214 void *MPU_pvPortMalloc( size_t xSize );\r
 215 void MPU_vPortFree( void *pv );\r
 216 void MPU_vPortInitialiseBlocks( void );\r
 217 size_t MPU_xPortGetFreeHeapSize( void );\r
 218 QueueSetHandle_t MPU_xQueueCreateSet( UBaseType_t uxEventQueueLength );\r
 219 QueueSetMemberHandle_t MPU_xQueueSelectFromSet( QueueSetHandle_t xQueueSet, TickType_t xBlockTimeTicks );\r
 220 BaseType_t MPU_xQueueAddToSet( QueueSetMemberHandle_t xQueueOrSemaphore, QueueSetHandle_t xQueueSet );\r
 221 BaseType_t MPU_xQueueRemoveFromSet( QueueSetMemberHandle_t xQueueOrSemaphore, QueueSetHandle_t xQueueSet );\r
 222 BaseType_t MPU_xQueuePeekFromISR( QueueHandle_t xQueue, void * const pvBuffer );\r
 223 void* MPU_xQueueGetMutexHolder( QueueHandle_t xSemaphore );\r
 224 \r
 225 /*-----------------------------------------------------------*/\r
 226 \r
 227 /*\r
 228  * See header file for description.\r
 229  */\r
 230 StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters, BaseType_t xRunPrivileged )\r
 231 {\r
 232         /* Simulate the stack frame as it would be created by a context switch\r
 233         interrupt. */\r
 234         pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */\r
 235         *pxTopOfStack = portINITIAL_XPSR;       /* xPSR */\r
 236         pxTopOfStack--;\r
 237         *pxTopOfStack = ( StackType_t ) pxCode; /* PC */\r
 238         pxTopOfStack--;\r
 239         *pxTopOfStack = 0;      /* LR */\r
 240         pxTopOfStack -= 5;      /* R12, R3, R2 and R1. */\r
 241         *pxTopOfStack = ( StackType_t ) pvParameters;   /* R0 */\r
 242         pxTopOfStack -= 9;      /* R11, R10, R9, R8, R7, R6, R5 and R4. */\r
 243 \r
 244         if( xRunPrivileged == pdTRUE )\r
 245         {\r
 246                 *pxTopOfStack = portINITIAL_CONTROL_IF_PRIVILEGED;\r
 247         }\r
 248         else\r
 249         {\r
 250                 *pxTopOfStack = portINITIAL_CONTROL_IF_UNPRIVILEGED;\r
 251         }\r
 252 \r
 253         return pxTopOfStack;\r
 254 }\r
 255 /*-----------------------------------------------------------*/\r
 256 \r
 257 void vPortSVCHandler( void )\r
 258 {\r
 259         /* Assumes psp was in use. */\r
 260         __asm volatile\r
 261         (\r
 262                 #ifndef USE_PROCESS_STACK       /* Code should not be required if a main() is using the process stack. */\r
 263                         "       tst lr, #4                                              \n"\r
 264                         "       ite eq                                                  \n"\r
 265                         "       mrseq r0, msp                                   \n"\r
 266                         "       mrsne r0, psp                                   \n"\r
 267                 #else\r
 268                         "       mrs r0, psp                                             \n"\r
 269                 #endif\r
 270                         "       b %0                                                    \n"\r
 271                         ::"i"(prvSVCHandler):"r0"\r
 272         );\r
 273 }\r
 274 /*-----------------------------------------------------------*/\r
 275 \r
 276 static void prvSVCHandler(      uint32_t *pulParam )\r
 277 {\r
 278 uint8_t ucSVCNumber;\r
 279 \r
 280         /* The stack contains: r0, r1, r2, r3, r12, r14, the return address and\r
 281         xPSR.  The first argument (r0) is pulParam[ 0 ]. */\r
 282         ucSVCNumber = ( ( uint8_t * ) pulParam[ portOFFSET_TO_PC ] )[ -2 ];\r
 283         switch( ucSVCNumber )\r
 284         {\r
 285                 case portSVC_START_SCHEDULER    :       *(portNVIC_SYSPRI1) |= portNVIC_SVC_PRI;\r
 286                                                                                         prvRestoreContextOfFirstTask();\r
 287                                                                                         break;\r
 288 \r
 289                 case portSVC_YIELD                              :       *(portNVIC_INT_CTRL) = portNVIC_PENDSVSET;\r
 290                                                                                         /* Barriers are normally not required\r
 291                                                                                         but do ensure the code is completely\r
 292                                                                                         within the specified behaviour for the\r
 293                                                                                         architecture. */\r
 294                                                                                         __asm volatile( "dsb" );\r
 295                                                                                         __asm volatile( "isb" );\r
 296 \r
 297                                                                                         break;\r
 298 \r
 299                 case portSVC_RAISE_PRIVILEGE    :       __asm volatile\r
 300                                                                                         (\r
 301                                                                                                 "       mrs r1, control         \n" /* Obtain current control value. */\r
 302                                                                                                 "       bic r1, #1                      \n" /* Set privilege bit. */\r
 303                                                                                                 "       msr control, r1         \n" /* Write back new control value. */\r
 304                                                                                                 :::"r1"\r
 305                                                                                         );\r
 306                                                                                         break;\r
 307 \r
 308                 default                                                 :       /* Unknown SVC call. */\r
 309                                                                                         break;\r
 310         }\r
 311 }\r
 312 /*-----------------------------------------------------------*/\r
 313 \r
 314 static void prvRestoreContextOfFirstTask( void )\r
 315 {\r
 316         __asm volatile\r
 317         (\r
 318                 "       ldr r0, =0xE000ED08                             \n" /* Use the NVIC offset register to locate the stack. */\r
 319                 "       ldr r0, [r0]                                    \n"\r
 320                 "       ldr r0, [r0]                                    \n"\r
 321                 "       msr msp, r0                                             \n" /* Set the msp back to the start of the stack. */\r
 322                 "       ldr     r3, pxCurrentTCBConst2          \n" /* Restore the context. */\r
 323                 "       ldr r1, [r3]                                    \n"\r
 324                 "       ldr r0, [r1]                                    \n" /* The first item in the TCB is the task top of stack. */\r
 325                 "       add r1, r1, #4                                  \n" /* Move onto the second item in the TCB... */\r
 326                 "       ldr r2, =0xe000ed9c                             \n" /* Region Base Address register. */\r
 327                 "       ldmia r1!, {r4-r11}                             \n" /* Read 4 sets of MPU registers. */\r
 328                 "       stmia r2!, {r4-r11}                             \n" /* Write 4 sets of MPU registers. */\r
 329                 "       ldmia r0!, {r3, r4-r11}                 \n" /* Pop the registers that are not automatically saved on exception entry. */\r
 330                 "       msr control, r3                                 \n"\r
 331                 "       msr psp, r0                                             \n" /* Restore the task stack pointer. */\r
 332                 "       mov r0, #0                                              \n"\r
 333                 "       msr     basepri, r0                                     \n"\r
 334                 "       ldr r14, =0xfffffffd                    \n" /* Load exec return code. */\r
 335                 "       bx r14                                                  \n"\r
 336                 "                                                                       \n"\r
 337                 "       .align 4                                                \n"\r
 338                 "pxCurrentTCBConst2: .word pxCurrentTCB \n"\r
 339         );\r
 340 }\r
 341 /*-----------------------------------------------------------*/\r
 342 \r
 343 /*\r
 344  * See header file for description.\r
 345  */\r
 346 BaseType_t xPortStartScheduler( void )\r
 347 {\r
 348         /* configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0.  See\r
 349         http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */\r
 350         configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) );\r
 351 \r
 352         /* Make PendSV and SysTick the same priority as the kernel. */\r
 353         *(portNVIC_SYSPRI2) |= portNVIC_PENDSV_PRI;\r
 354         *(portNVIC_SYSPRI2) |= portNVIC_SYSTICK_PRI;\r
 355 \r
 356         /* Configure the regions in the MPU that are common to all tasks. */\r
 357         prvSetupMPU();\r
 358 \r
 359         /* Start the timer that generates the tick ISR.  Interrupts are disabled\r
 360         here already. */\r
 361         prvSetupTimerInterrupt();\r
 362 \r
 363         /* Initialise the critical nesting count ready for the first task. */\r
 364         uxCriticalNesting = 0;\r
 365 \r
 366         /* Start the first task. */\r
 367         __asm volatile( "       svc %0                  \n"\r
 368                                         :: "i" (portSVC_START_SCHEDULER) );\r
 369 \r
 370         /* Should not get here! */\r
 371         return 0;\r
 372 }\r
 373 /*-----------------------------------------------------------*/\r
 374 \r
 375 void vPortEndScheduler( void )\r
 376 {\r
 377         /* Not implemented in ports where there is nothing to return to.\r
 378         Artificially force an assert. */\r
 379         configASSERT( uxCriticalNesting == 1000UL );\r
 380 }\r
 381 /*-----------------------------------------------------------*/\r
 382 \r
 383 void vPortEnterCritical( void )\r
 384 {\r
 385 BaseType_t xRunningPrivileged = prvRaisePrivilege();\r
 386 \r
 387         portDISABLE_INTERRUPTS();\r
 388         uxCriticalNesting++;\r
 389 \r
 390         portRESET_PRIVILEGE( xRunningPrivileged );\r
 391 }\r
 392 /*-----------------------------------------------------------*/\r
 393 \r
 394 void vPortExitCritical( void )\r
 395 {\r
 396 BaseType_t xRunningPrivileged = prvRaisePrivilege();\r
 397 \r
 398         configASSERT( uxCriticalNesting );\r
 399         uxCriticalNesting--;\r
 400         if( uxCriticalNesting == 0 )\r
 401         {\r
 402                 portENABLE_INTERRUPTS();\r
 403         }\r
 404         portRESET_PRIVILEGE( xRunningPrivileged );\r
 405 }\r
 406 /*-----------------------------------------------------------*/\r
 407 \r
 408 void xPortPendSVHandler( void )\r
 409 {\r
 410         /* This is a naked function. */\r
 411 \r
 412         __asm volatile\r
 413         (\r
 414                 "       mrs r0, psp                                                     \n"\r
 415                 "                                                                               \n"\r
 416                 "       ldr     r3, pxCurrentTCBConst                   \n" /* Get the location of the current TCB. */\r
 417                 "       ldr     r2, [r3]                                                \n"\r
 418                 "                                                                               \n"\r
 419                 "       mrs r1, control                                         \n"\r
 420                 "       stmdb r0!, {r1, r4-r11}                         \n" /* Save the remaining registers. */\r
 421                 "       str r0, [r2]                                            \n" /* Save the new top of stack into the first member of the TCB. */\r
 422                 "                                                                               \n"\r
 423                 "       stmdb sp!, {r3, r14}                            \n"\r
 424                 "       mov r0, %0                                                      \n"\r
 425                 "       msr basepri, r0                                         \n"\r
 426                 "       bl vTaskSwitchContext                           \n"\r
 427                 "       mov r0, #0                                                      \n"\r
 428                 "       msr basepri, r0                                         \n"\r
 429                 "       ldmia sp!, {r3, r14}                            \n"\r
 430                 "                                                                               \n"     /* Restore the context. */\r
 431                 "       ldr r1, [r3]                                            \n"\r
 432                 "       ldr r0, [r1]                                            \n" /* The first item in the TCB is the task top of stack. */\r
 433                 "       add r1, r1, #4                                          \n" /* Move onto the second item in the TCB... */\r
 434                 "       ldr r2, =0xe000ed9c                                     \n" /* Region Base Address register. */\r
 435                 "       ldmia r1!, {r4-r11}                                     \n" /* Read 4 sets of MPU registers. */\r
 436                 "       stmia r2!, {r4-r11}                                     \n" /* Write 4 sets of MPU registers. */\r
 437                 "       ldmia r0!, {r3, r4-r11}                         \n" /* Pop the registers that are not automatically saved on exception entry. */\r
 438                 "       msr control, r3                                         \n"\r
 439                 "                                                                               \n"\r
 440                 "       msr psp, r0                                                     \n"\r
 441                 "       bx r14                                                          \n"\r
 442                 "                                                                               \n"\r
 443                 "       .align 4                                                        \n"\r
 444                 "pxCurrentTCBConst: .word pxCurrentTCB  \n"\r
 445                 ::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY)\r
 446         );\r
 447 }\r
 448 /*-----------------------------------------------------------*/\r
 449 \r
 450 void xPortSysTickHandler( void )\r
 451 {\r
 452 uint32_t ulDummy;\r
 453 \r
 454         ulDummy = portSET_INTERRUPT_MASK_FROM_ISR();\r
 455         {\r
 456                 /* Increment the RTOS tick. */\r
 457                 if( xTaskIncrementTick() != pdFALSE )\r
 458                 {\r
 459                         /* Pend a context switch. */\r
 460                         *(portNVIC_INT_CTRL) = portNVIC_PENDSVSET;\r
 461                 }\r
 462         }\r
 463         portCLEAR_INTERRUPT_MASK_FROM_ISR( ulDummy );\r
 464 }\r
 465 /*-----------------------------------------------------------*/\r
 466 \r
 467 /*\r
 468  * Setup the systick timer to generate the tick interrupts at the required\r
 469  * frequency.\r
 470  */\r
 471 static void prvSetupTimerInterrupt( void )\r
 472 {\r
 473         /* Configure SysTick to interrupt at the requested rate. */\r
 474         *(portNVIC_SYSTICK_LOAD) = ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;\r
 475         *(portNVIC_SYSTICK_CTRL) = portNVIC_SYSTICK_CLK | portNVIC_SYSTICK_INT | portNVIC_SYSTICK_ENABLE;\r
 476 }\r
 477 /*-----------------------------------------------------------*/\r
 478 \r
 479 static void prvSetupMPU( void )\r
 480 {\r
 481 extern uint32_t __privileged_functions_end__[];\r
 482 extern uint32_t __FLASH_segment_start__[];\r
 483 extern uint32_t __FLASH_segment_end__[];\r
 484 extern uint32_t __privileged_data_start__[];\r
 485 extern uint32_t __privileged_data_end__[];\r
 486 \r
 487         /* Check the expected MPU is present. */\r
 488         if( *portMPU_TYPE == portEXPECTED_MPU_TYPE_VALUE )\r
 489         {\r
 490                 /* First setup the entire flash for unprivileged read only access. */\r
 491         *portMPU_REGION_BASE_ADDRESS =  ( ( uint32_t ) __FLASH_segment_start__ ) | /* Base address. */\r
 492                                                                                 ( portMPU_REGION_VALID ) |\r
 493                                                                                 ( portUNPRIVILEGED_FLASH_REGION );\r
 494 \r
 495                 *portMPU_REGION_ATTRIBUTE =             ( portMPU_REGION_READ_ONLY ) |\r
 496                                                                                 ( portMPU_REGION_CACHEABLE_BUFFERABLE ) |\r
 497                                                                                 ( prvGetMPURegionSizeSetting( ( uint32_t ) __FLASH_segment_end__ - ( uint32_t ) __FLASH_segment_start__ ) ) |\r
 498                                                                                 ( portMPU_REGION_ENABLE );\r
 499 \r
 500                 /* Setup the first 16K for privileged only access (even though less\r
 501                 than 10K is actually being used).  This is where the kernel code is\r
 502                 placed. */\r
 503         *portMPU_REGION_BASE_ADDRESS =  ( ( uint32_t ) __FLASH_segment_start__ ) | /* Base address. */\r
 504                                                                                 ( portMPU_REGION_VALID ) |\r
 505                                                                                 ( portPRIVILEGED_FLASH_REGION );\r
 506 \r
 507                 *portMPU_REGION_ATTRIBUTE =             ( portMPU_REGION_PRIVILEGED_READ_ONLY ) |\r
 508                                                                                 ( portMPU_REGION_CACHEABLE_BUFFERABLE ) |\r
 509                                                                                 ( prvGetMPURegionSizeSetting( ( uint32_t ) __privileged_functions_end__ - ( uint32_t ) __FLASH_segment_start__ ) ) |\r
 510                                                                                 ( portMPU_REGION_ENABLE );\r
 511 \r
 512                 /* Setup the privileged data RAM region.  This is where the kernel data\r
 513                 is placed. */\r
 514                 *portMPU_REGION_BASE_ADDRESS =  ( ( uint32_t ) __privileged_data_start__ ) | /* Base address. */\r
 515                                                                                 ( portMPU_REGION_VALID ) |\r
 516                                                                                 ( portPRIVILEGED_RAM_REGION );\r
 517 \r
 518                 *portMPU_REGION_ATTRIBUTE =             ( portMPU_REGION_PRIVILEGED_READ_WRITE ) |\r
 519                                                                                 ( portMPU_REGION_CACHEABLE_BUFFERABLE ) |\r
 520                                                                                 prvGetMPURegionSizeSetting( ( uint32_t ) __privileged_data_end__ - ( uint32_t ) __privileged_data_start__ ) |\r
 521                                                                                 ( portMPU_REGION_ENABLE );\r
 522 \r
 523                 /* By default allow everything to access the general peripherals.  The\r
 524                 system peripherals and registers are protected. */\r
 525                 *portMPU_REGION_BASE_ADDRESS =  ( portPERIPHERALS_START_ADDRESS ) |\r
 526                                                                                 ( portMPU_REGION_VALID ) |\r
 527                                                                                 ( portGENERAL_PERIPHERALS_REGION );\r
 528 \r
 529                 *portMPU_REGION_ATTRIBUTE =             ( portMPU_REGION_READ_WRITE | portMPU_REGION_EXECUTE_NEVER ) |\r
 530                                                                                 ( prvGetMPURegionSizeSetting( portPERIPHERALS_END_ADDRESS - portPERIPHERALS_START_ADDRESS ) ) |\r
 531                                                                                 ( portMPU_REGION_ENABLE );\r
 532 \r
 533                 /* Enable the memory fault exception. */\r
 534                 *portNVIC_SYS_CTRL_STATE |= portNVIC_MEM_FAULT_ENABLE;\r
 535 \r
 536                 /* Enable the MPU with the background region configured. */\r
 537                 *portMPU_CTRL |= ( portMPU_ENABLE | portMPU_BACKGROUND_ENABLE );\r
 538         }\r
 539 }\r
 540 /*-----------------------------------------------------------*/\r
 541 \r
 542 static uint32_t prvGetMPURegionSizeSetting( uint32_t ulActualSizeInBytes )\r
 543 {\r
 544 uint32_t ulRegionSize, ulReturnValue = 4;\r
 545 \r
 546         /* 32 is the smallest region size, 31 is the largest valid value for\r
 547         ulReturnValue. */\r
 548         for( ulRegionSize = 32UL; ulReturnValue < 31UL; ( ulRegionSize <<= 1UL ) )\r
 549         {\r
 550                 if( ulActualSizeInBytes <= ulRegionSize )\r
 551                 {\r
 552                         break;\r
 553                 }\r
 554                 else\r
 555                 {\r
 556                         ulReturnValue++;\r
 557                 }\r
 558         }\r
 559 \r
 560         /* Shift the code by one before returning so it can be written directly\r
 561         into the the correct bit position of the attribute register. */\r
 562         return ( ulReturnValue << 1UL );\r
 563 }\r
 564 /*-----------------------------------------------------------*/\r
 565 \r
 566 static BaseType_t prvRaisePrivilege( void )\r
 567 {\r
 568         __asm volatile\r
 569         (\r
 570                 "       mrs r0, control                                         \n"\r
 571                 "       tst r0, #1                                                      \n" /* Is the task running privileged? */\r
 572                 "       itte ne                                                         \n"\r
 573                 "       movne r0, #0                                            \n" /* CONTROL[0]!=0, return false. */\r
 574                 "       svcne %0                                                        \n" /* Switch to privileged. */\r
 575                 "       moveq r0, #1                                            \n" /* CONTROL[0]==0, return true. */\r
 576                 "       bx lr                                                           \n"\r
 577                 :: "i" (portSVC_RAISE_PRIVILEGE) : "r0"\r
 578         );\r
 579 \r
 580         return 0;\r
 581 }\r
 582 /*-----------------------------------------------------------*/\r
 583 \r
 584 void vPortStoreTaskMPUSettings( xMPU_SETTINGS *xMPUSettings, const struct xMEMORY_REGION * const xRegions, StackType_t *pxBottomOfStack, uint16_t usStackDepth )\r
 585 {\r
 586 extern uint32_t __SRAM_segment_start__[];\r
 587 extern uint32_t __SRAM_segment_end__[];\r
 588 extern uint32_t __privileged_data_start__[];\r
 589 extern uint32_t __privileged_data_end__[];\r
 590 int32_t lIndex;\r
 591 uint32_t ul;\r
 592 \r
 593         if( xRegions == NULL )\r
 594         {\r
 595                 /* No MPU regions are specified so allow access to all RAM. */\r
 596         xMPUSettings->xRegion[ 0 ].ulRegionBaseAddress =\r
 597                                 ( ( uint32_t ) __SRAM_segment_start__ ) | /* Base address. */\r
 598                                 ( portMPU_REGION_VALID ) |\r
 599                                 ( portSTACK_REGION );\r
 600 \r
 601                 xMPUSettings->xRegion[ 0 ].ulRegionAttribute =\r
 602                                 ( portMPU_REGION_READ_WRITE ) |\r
 603                                 ( portMPU_REGION_CACHEABLE_BUFFERABLE ) |\r
 604                                 ( prvGetMPURegionSizeSetting( ( uint32_t ) __SRAM_segment_end__ - ( uint32_t ) __SRAM_segment_start__ ) ) |\r
 605                                 ( portMPU_REGION_ENABLE );\r
 606 \r
 607                 /* Re-instate the privileged only RAM region as xRegion[ 0 ] will have\r
 608                 just removed the privileged only parameters. */\r
 609                 xMPUSettings->xRegion[ 1 ].ulRegionBaseAddress =\r
 610                                 ( ( uint32_t ) __privileged_data_start__ ) | /* Base address. */\r
 611                                 ( portMPU_REGION_VALID ) |\r
 612                                 ( portSTACK_REGION + 1 );\r
 613 \r
 614                 xMPUSettings->xRegion[ 1 ].ulRegionAttribute =\r
 615                                 ( portMPU_REGION_PRIVILEGED_READ_WRITE ) |\r
 616                                 ( portMPU_REGION_CACHEABLE_BUFFERABLE ) |\r
 617                                 prvGetMPURegionSizeSetting( ( uint32_t ) __privileged_data_end__ - ( uint32_t ) __privileged_data_start__ ) |\r
 618                                 ( portMPU_REGION_ENABLE );\r
 619 \r
 620                 /* Invalidate all other regions. */\r
 621                 for( ul = 2; ul <= portNUM_CONFIGURABLE_REGIONS; ul++ )\r
 622                 {\r
 623                         xMPUSettings->xRegion[ ul ].ulRegionBaseAddress = ( portSTACK_REGION + ul ) | portMPU_REGION_VALID;\r
 624                         xMPUSettings->xRegion[ ul ].ulRegionAttribute = 0UL;\r
 625                 }\r
 626         }\r
 627         else\r
 628         {\r
 629                 /* This function is called automatically when the task is created - in\r
 630                 which case the stack region parameters will be valid.  At all other\r
 631                 times the stack parameters will not be valid and it is assumed that the\r
 632                 stack region has already been configured. */\r
 633                 if( usStackDepth > 0 )\r
 634                 {\r
 635                         /* Define the region that allows access to the stack. */\r
 636                         xMPUSettings->xRegion[ 0 ].ulRegionBaseAddress =\r
 637                                         ( ( uint32_t ) pxBottomOfStack ) |\r
 638                                         ( portMPU_REGION_VALID ) |\r
 639                                         ( portSTACK_REGION ); /* Region number. */\r
 640 \r
 641                         xMPUSettings->xRegion[ 0 ].ulRegionAttribute =\r
 642                                         ( portMPU_REGION_READ_WRITE ) | /* Read and write. */\r
 643                                         ( prvGetMPURegionSizeSetting( ( uint32_t ) usStackDepth * ( uint32_t ) sizeof( StackType_t ) ) ) |\r
 644                                         ( portMPU_REGION_CACHEABLE_BUFFERABLE ) |\r
 645                                         ( portMPU_REGION_ENABLE );\r
 646                 }\r
 647 \r
 648                 lIndex = 0;\r
 649 \r
 650                 for( ul = 1; ul <= portNUM_CONFIGURABLE_REGIONS; ul++ )\r
 651                 {\r
 652                         if( ( xRegions[ lIndex ] ).ulLengthInBytes > 0UL )\r
 653                         {\r
 654                                 /* Translate the generic region definition contained in\r
 655                                 xRegions into the CM3 specific MPU settings that are then\r
 656                                 stored in xMPUSettings. */\r
 657                                 xMPUSettings->xRegion[ ul ].ulRegionBaseAddress =\r
 658                                                 ( ( uint32_t ) xRegions[ lIndex ].pvBaseAddress ) |\r
 659                                                 ( portMPU_REGION_VALID ) |\r
 660                                                 ( portSTACK_REGION + ul ); /* Region number. */\r
 661 \r
 662                                 xMPUSettings->xRegion[ ul ].ulRegionAttribute =\r
 663                                                 ( prvGetMPURegionSizeSetting( xRegions[ lIndex ].ulLengthInBytes ) ) |\r
 664                                                 ( xRegions[ lIndex ].ulParameters ) |\r
 665                                                 ( portMPU_REGION_ENABLE );\r
 666                         }\r
 667                         else\r
 668                         {\r
 669                                 /* Invalidate the region. */\r
 670                                 xMPUSettings->xRegion[ ul ].ulRegionBaseAddress = ( portSTACK_REGION + ul ) | portMPU_REGION_VALID;\r
 671                                 xMPUSettings->xRegion[ ul ].ulRegionAttribute = 0UL;\r
 672                         }\r
 673 \r
 674                         lIndex++;\r
 675                 }\r
 676         }\r
 677 }\r
 678 /*-----------------------------------------------------------*/\r
 679 \r
 680 BaseType_t MPU_xTaskGenericCreate( TaskFunction_t pvTaskCode, const char * const pcName, uint16_t usStackDepth, void *pvParameters, UBaseType_t uxPriority, TaskHandle_t *pxCreatedTask, StackType_t *puxStackBuffer, const MemoryRegion_t * const xRegions )\r
 681 {\r
 682 BaseType_t xReturn;\r
 683 BaseType_t xRunningPrivileged = prvRaisePrivilege();\r
 684 \r
 685         xReturn = xTaskGenericCreate( pvTaskCode, pcName, usStackDepth, pvParameters, uxPriority, pxCreatedTask, puxStackBuffer, xRegions );\r
 686         portRESET_PRIVILEGE( xRunningPrivileged );\r
 687         return xReturn;\r
 688 }\r
 689 /*-----------------------------------------------------------*/\r
 690 \r
 691 void MPU_vTaskAllocateMPURegions( TaskHandle_t xTask, const MemoryRegion_t * const xRegions )\r
 692 {\r
 693 BaseType_t xRunningPrivileged = prvRaisePrivilege();\r
 694 \r
 695         vTaskAllocateMPURegions( xTask, xRegions );\r
 696         portRESET_PRIVILEGE( xRunningPrivileged );\r
 697 }\r
 698 /*-----------------------------------------------------------*/\r
 699 \r
 700 #if ( INCLUDE_vTaskDelete == 1 )\r
 701         void MPU_vTaskDelete( TaskHandle_t pxTaskToDelete )\r
 702         {\r
 703     BaseType_t xRunningPrivileged = prvRaisePrivilege();\r
 704 \r
 705                 vTaskDelete( pxTaskToDelete );\r
 706         portRESET_PRIVILEGE( xRunningPrivileged );\r
 707         }\r
 708 #endif\r
 709 /*-----------------------------------------------------------*/\r
 710 \r
 711 #if ( INCLUDE_vTaskDelayUntil == 1 )\r
 712         void MPU_vTaskDelayUntil( TickType_t * const pxPreviousWakeTime, TickType_t xTimeIncrement )\r
 713         {\r
 714     BaseType_t xRunningPrivileged = prvRaisePrivilege();\r
 715 \r
 716                 vTaskDelayUntil( pxPreviousWakeTime, xTimeIncrement );\r
 717         portRESET_PRIVILEGE( xRunningPrivileged );\r
 718         }\r
 719 #endif\r
 720 /*-----------------------------------------------------------*/\r
 721 \r
 722 #if ( INCLUDE_vTaskDelay == 1 )\r
 723         void MPU_vTaskDelay( TickType_t xTicksToDelay )\r
 724         {\r
 725     BaseType_t xRunningPrivileged = prvRaisePrivilege();\r
 726 \r
 727                 vTaskDelay( xTicksToDelay );\r
 728         portRESET_PRIVILEGE( xRunningPrivileged );\r
 729         }\r
 730 #endif\r
 731 /*-----------------------------------------------------------*/\r
 732 \r
 733 #if ( INCLUDE_uxTaskPriorityGet == 1 )\r
 734         UBaseType_t MPU_uxTaskPriorityGet( TaskHandle_t pxTask )\r
 735         {\r
 736         UBaseType_t uxReturn;\r
 737     BaseType_t xRunningPrivileged = prvRaisePrivilege();\r
 738 \r
 739                 uxReturn = uxTaskPriorityGet( pxTask );\r
 740         portRESET_PRIVILEGE( xRunningPrivileged );\r
 741                 return uxReturn;\r
 742         }\r
 743 #endif\r
 744 /*-----------------------------------------------------------*/\r
 745 \r
 746 #if ( INCLUDE_vTaskPrioritySet == 1 )\r
 747         void MPU_vTaskPrioritySet( TaskHandle_t pxTask, UBaseType_t uxNewPriority )\r
 748         {\r
 749     BaseType_t xRunningPrivileged = prvRaisePrivilege();\r
 750 \r
 751                 vTaskPrioritySet( pxTask, uxNewPriority );\r
 752         portRESET_PRIVILEGE( xRunningPrivileged );\r
 753         }\r
 754 #endif\r
 755 /*-----------------------------------------------------------*/\r
 756 \r
 757 #if ( INCLUDE_eTaskGetState == 1 )\r
 758         eTaskState MPU_eTaskGetState( TaskHandle_t pxTask )\r
 759         {\r
 760     BaseType_t xRunningPrivileged = prvRaisePrivilege();\r
 761         eTaskState eReturn;\r
 762 \r
 763                 eReturn = eTaskGetState( pxTask );\r
 764         portRESET_PRIVILEGE( xRunningPrivileged );\r
 765                 return eReturn;\r
 766         }\r
 767 #endif\r
 768 /*-----------------------------------------------------------*/\r
 769 \r
 770 #if ( INCLUDE_xTaskGetIdleTaskHandle == 1 )\r
 771         TaskHandle_t MPU_xTaskGetIdleTaskHandle( void )\r
 772         {\r
 773         TaskHandle_t xReturn;\r
 774     BaseType_t xRunningPrivileged = prvRaisePrivilege();\r
 775 \r
 776                 xReturn = xTaskGetIdleTaskHandle();\r
 777         portRESET_PRIVILEGE( xRunningPrivileged );\r
 778                 return eReturn;\r
 779         }\r
 780 #endif\r
 781 /*-----------------------------------------------------------*/\r
 782 \r
 783 #if ( INCLUDE_vTaskSuspend == 1 )\r
 784         void MPU_vTaskSuspend( TaskHandle_t pxTaskToSuspend )\r
 785         {\r
 786     BaseType_t xRunningPrivileged = prvRaisePrivilege();\r
 787 \r
 788                 vTaskSuspend( pxTaskToSuspend );\r
 789         portRESET_PRIVILEGE( xRunningPrivileged );\r
 790         }\r
 791 #endif\r
 792 /*-----------------------------------------------------------*/\r
 793 \r
 794 #if ( INCLUDE_vTaskSuspend == 1 )\r
 795         void MPU_vTaskResume( TaskHandle_t pxTaskToResume )\r
 796         {\r
 797     BaseType_t xRunningPrivileged = prvRaisePrivilege();\r
 798 \r
 799                 vTaskResume( pxTaskToResume );\r
 800         portRESET_PRIVILEGE( xRunningPrivileged );\r
 801         }\r
 802 #endif\r
 803 /*-----------------------------------------------------------*/\r
 804 \r
 805 void MPU_vTaskSuspendAll( void )\r
 806 {\r
 807 BaseType_t xRunningPrivileged = prvRaisePrivilege();\r
 808 \r
 809         vTaskSuspendAll();\r
 810     portRESET_PRIVILEGE( xRunningPrivileged );\r
 811 }\r
 812 /*-----------------------------------------------------------*/\r
 813 \r
 814 BaseType_t MPU_xTaskResumeAll( void )\r
 815 {\r
 816 BaseType_t xReturn;\r
 817 BaseType_t xRunningPrivileged = prvRaisePrivilege();\r
 818 \r
 819         xReturn = xTaskResumeAll();\r
 820     portRESET_PRIVILEGE( xRunningPrivileged );\r
 821     return xReturn;\r
 822 }\r
 823 /*-----------------------------------------------------------*/\r
 824 \r
 825 TickType_t MPU_xTaskGetTickCount( void )\r
 826 {\r
 827 TickType_t xReturn;\r
 828 BaseType_t xRunningPrivileged = prvRaisePrivilege();\r
 829 \r
 830         xReturn = xTaskGetTickCount();\r
 831     portRESET_PRIVILEGE( xRunningPrivileged );\r
 832         return xReturn;\r
 833 }\r
 834 /*-----------------------------------------------------------*/\r
 835 \r
 836 UBaseType_t MPU_uxTaskGetNumberOfTasks( void )\r
 837 {\r
 838 UBaseType_t uxReturn;\r
 839 BaseType_t xRunningPrivileged = prvRaisePrivilege();\r
 840 \r
 841         uxReturn = uxTaskGetNumberOfTasks();\r
 842     portRESET_PRIVILEGE( xRunningPrivileged );\r
 843         return uxReturn;\r
 844 }\r
 845 /*-----------------------------------------------------------*/\r
 846 \r
 847 #if ( configUSE_TRACE_FACILITY == 1 )\r
 848         void MPU_vTaskList( char *pcWriteBuffer )\r
 849         {\r
 850         BaseType_t xRunningPrivileged = prvRaisePrivilege();\r
 851 \r
 852                 vTaskList( pcWriteBuffer );\r
 853                 portRESET_PRIVILEGE( xRunningPrivileged );\r
 854         }\r
 855 #endif\r
 856 /*-----------------------------------------------------------*/\r
 857 \r
 858 #if ( configGENERATE_RUN_TIME_STATS == 1 )\r
 859         void MPU_vTaskGetRunTimeStats( char *pcWriteBuffer )\r
 860         {\r
 861     BaseType_t xRunningPrivileged = prvRaisePrivilege();\r
 862 \r
 863                 vTaskGetRunTimeStats( pcWriteBuffer );\r
 864         portRESET_PRIVILEGE( xRunningPrivileged );\r
 865         }\r
 866 #endif\r
 867 /*-----------------------------------------------------------*/\r
 868 \r
 869 #if ( configUSE_APPLICATION_TASK_TAG == 1 )\r
 870         void MPU_vTaskSetApplicationTaskTag( TaskHandle_t xTask, TaskHookFunction_t pxTagValue )\r
 871         {\r
 872     BaseType_t xRunningPrivileged = prvRaisePrivilege();\r
 873 \r
 874                 vTaskSetApplicationTaskTag( xTask, pxTagValue );\r
 875         portRESET_PRIVILEGE( xRunningPrivileged );\r
 876         }\r
 877 #endif\r
 878 /*-----------------------------------------------------------*/\r
 879 \r
 880 #if ( configUSE_APPLICATION_TASK_TAG == 1 )\r
 881         TaskHookFunction_t MPU_xTaskGetApplicationTaskTag( TaskHandle_t xTask )\r
 882         {\r
 883         TaskHookFunction_t xReturn;\r
 884     BaseType_t xRunningPrivileged = prvRaisePrivilege();\r
 885 \r
 886                 xReturn = xTaskGetApplicationTaskTag( xTask );\r
 887         portRESET_PRIVILEGE( xRunningPrivileged );\r
 888                 return xReturn;\r
 889         }\r
 890 #endif\r
 891 /*-----------------------------------------------------------*/\r
 892 \r
 893 #if ( configUSE_APPLICATION_TASK_TAG == 1 )\r
 894         BaseType_t MPU_xTaskCallApplicationTaskHook( TaskHandle_t xTask, void *pvParameter )\r
 895         {\r
 896         BaseType_t xReturn;\r
 897     BaseType_t xRunningPrivileged = prvRaisePrivilege();\r
 898 \r
 899                 xReturn = xTaskCallApplicationTaskHook( xTask, pvParameter );\r
 900         portRESET_PRIVILEGE( xRunningPrivileged );\r
 901                 return xReturn;\r
 902         }\r
 903 #endif\r
 904 /*-----------------------------------------------------------*/\r
 905 \r
 906 #if ( configUSE_TRACE_FACILITY == 1 )\r
 907         UBaseType_t MPU_uxTaskGetSystemState( TaskStatus_t *pxTaskStatusArray, UBaseType_t uxArraySize, uint32_t *pulTotalRunTime )\r
 908         {\r
 909         UBaseType_t uxReturn;\r
 910         BaseType_t xRunningPrivileged = prvRaisePrivilege();\r
 911 \r
 912                 uxReturn = uxTaskGetSystemState( pxTaskStatusArray, uxArraySize, pulTotalRunTime );\r
 913                 portRESET_PRIVILEGE( xRunningPrivileged );\r
 914                 return uxReturn;\r
 915         }\r
 916 #endif\r
 917 /*-----------------------------------------------------------*/\r
 918 \r
 919 #if ( INCLUDE_uxTaskGetStackHighWaterMark == 1 )\r
 920         UBaseType_t MPU_uxTaskGetStackHighWaterMark( TaskHandle_t xTask )\r
 921         {\r
 922         UBaseType_t uxReturn;\r
 923     BaseType_t xRunningPrivileged = prvRaisePrivilege();\r
 924 \r
 925                 uxReturn = uxTaskGetStackHighWaterMark( xTask );\r
 926         portRESET_PRIVILEGE( xRunningPrivileged );\r
 927                 return uxReturn;\r
 928         }\r
 929 #endif\r
 930 /*-----------------------------------------------------------*/\r
 931 \r
 932 #if ( INCLUDE_xTaskGetCurrentTaskHandle == 1 )\r
 933         TaskHandle_t MPU_xTaskGetCurrentTaskHandle( void )\r
 934         {\r
 935         TaskHandle_t xReturn;\r
 936     BaseType_t xRunningPrivileged = prvRaisePrivilege();\r
 937 \r
 938                 xReturn = xTaskGetCurrentTaskHandle();\r
 939         portRESET_PRIVILEGE( xRunningPrivileged );\r
 940                 return xReturn;\r
 941         }\r
 942 #endif\r
 943 /*-----------------------------------------------------------*/\r
 944 \r
 945 #if ( INCLUDE_xTaskGetSchedulerState == 1 )\r
 946         BaseType_t MPU_xTaskGetSchedulerState( void )\r
 947         {\r
 948         BaseType_t xReturn;\r
 949     BaseType_t xRunningPrivileged = prvRaisePrivilege();\r
 950 \r
 951                 xReturn = xTaskGetSchedulerState();\r
 952         portRESET_PRIVILEGE( xRunningPrivileged );\r
 953                 return xReturn;\r
 954         }\r
 955 #endif\r
 956 /*-----------------------------------------------------------*/\r
 957 \r
 958 QueueHandle_t MPU_xQueueGenericCreate( UBaseType_t uxQueueLength, UBaseType_t uxItemSize, uint8_t ucQueueType )\r
 959 {\r
 960 QueueHandle_t xReturn;\r
 961 BaseType_t xRunningPrivileged = prvRaisePrivilege();\r
 962 \r
 963         xReturn = xQueueGenericCreate( uxQueueLength, uxItemSize, ucQueueType );\r
 964         portRESET_PRIVILEGE( xRunningPrivileged );\r
 965         return xReturn;\r
 966 }\r
 967 /*-----------------------------------------------------------*/\r
 968 \r
 969 BaseType_t MPU_xQueueGenericReset( QueueHandle_t pxQueue, BaseType_t xNewQueue )\r
 970 {\r
 971 BaseType_t xReturn;\r
 972 BaseType_t xRunningPrivileged = prvRaisePrivilege();\r
 973 \r
 974         xReturn = xQueueGenericReset( pxQueue, xNewQueue );\r
 975         portRESET_PRIVILEGE( xRunningPrivileged );\r
 976         return xReturn;\r
 977 }\r
 978 /*-----------------------------------------------------------*/\r
 979 \r
 980 BaseType_t MPU_xQueueGenericSend( QueueHandle_t xQueue, const void * const pvItemToQueue, TickType_t xTicksToWait, BaseType_t xCopyPosition )\r
 981 {\r
 982 BaseType_t xReturn;\r
 983 BaseType_t xRunningPrivileged = prvRaisePrivilege();\r
 984 \r
 985         xReturn = xQueueGenericSend( xQueue, pvItemToQueue, xTicksToWait, xCopyPosition );\r
 986         portRESET_PRIVILEGE( xRunningPrivileged );\r
 987         return xReturn;\r
 988 }\r
 989 /*-----------------------------------------------------------*/\r
 990 \r
 991 UBaseType_t MPU_uxQueueMessagesWaiting( const QueueHandle_t pxQueue )\r
 992 {\r
 993 BaseType_t xRunningPrivileged = prvRaisePrivilege();\r
 994 UBaseType_t uxReturn;\r
 995 \r
 996         uxReturn = uxQueueMessagesWaiting( pxQueue );\r
 997         portRESET_PRIVILEGE( xRunningPrivileged );\r
 998         return uxReturn;\r
 999 }\r
1000 /*-----------------------------------------------------------*/\r
1001 \r
1002 BaseType_t MPU_xQueueGenericReceive( QueueHandle_t pxQueue, void * const pvBuffer, TickType_t xTicksToWait, BaseType_t xJustPeeking )\r
1003 {\r
1004 BaseType_t xRunningPrivileged = prvRaisePrivilege();\r
1005 BaseType_t xReturn;\r
1006 \r
1007         xReturn = xQueueGenericReceive( pxQueue, pvBuffer, xTicksToWait, xJustPeeking );\r
1008         portRESET_PRIVILEGE( xRunningPrivileged );\r
1009         return xReturn;\r
1010 }\r
1011 /*-----------------------------------------------------------*/\r
1012 \r
1013 BaseType_t MPU_xQueuePeekFromISR( QueueHandle_t pxQueue, void * const pvBuffer )\r
1014 {\r
1015 BaseType_t xRunningPrivileged = prvRaisePrivilege();\r
1016 BaseType_t xReturn;\r
1017 \r
1018         xReturn = xQueuePeekFromISR( pxQueue, pvBuffer );\r
1019         portRESET_PRIVILEGE( xRunningPrivileged );\r
1020         return xReturn;\r
1021 }\r
1022 /*-----------------------------------------------------------*/\r
1023 \r
1024 void* MPU_xQueueGetMutexHolder( QueueHandle_t xSemaphore )\r
1025 {\r
1026 BaseType_t xRunningPrivileged = prvRaisePrivilege();\r
1027 void * xReturn;\r
1028 \r
1029         xReturn = ( void * ) xQueueGetMutexHolder( xSemaphore );\r
1030         portRESET_PRIVILEGE( xRunningPrivileged );\r
1031         return xReturn;\r
1032 }\r
1033 /*-----------------------------------------------------------*/\r
1034 \r
1035 #if ( configUSE_MUTEXES == 1 )\r
1036         QueueHandle_t MPU_xQueueCreateMutex( void )\r
1037         {\r
1038     QueueHandle_t xReturn;\r
1039         BaseType_t xRunningPrivileged = prvRaisePrivilege();\r
1040 \r
1041                 xReturn = xQueueCreateMutex( queueQUEUE_TYPE_MUTEX );\r
1042                 portRESET_PRIVILEGE( xRunningPrivileged );\r
1043                 return xReturn;\r
1044         }\r
1045 #endif\r
1046 /*-----------------------------------------------------------*/\r
1047 \r
1048 #if configUSE_COUNTING_SEMAPHORES == 1\r
1049         QueueHandle_t MPU_xQueueCreateCountingSemaphore( UBaseType_t uxCountValue, UBaseType_t uxInitialCount )\r
1050         {\r
1051     QueueHandle_t xReturn;\r
1052         BaseType_t xRunningPrivileged = prvRaisePrivilege();\r
1053 \r
1054                 xReturn = xQueueCreateCountingSemaphore( uxCountValue, uxInitialCount );\r
1055                 portRESET_PRIVILEGE( xRunningPrivileged );\r
1056                 return xReturn;\r
1057         }\r
1058 #endif\r
1059 /*-----------------------------------------------------------*/\r
1060 \r
1061 #if ( configUSE_MUTEXES == 1 )\r
1062         BaseType_t MPU_xQueueTakeMutexRecursive( QueueHandle_t xMutex, TickType_t xBlockTime )\r
1063         {\r
1064         BaseType_t xReturn;\r
1065         BaseType_t xRunningPrivileged = prvRaisePrivilege();\r
1066 \r
1067                 xReturn = xQueueTakeMutexRecursive( xMutex, xBlockTime );\r
1068                 portRESET_PRIVILEGE( xRunningPrivileged );\r
1069                 return xReturn;\r
1070         }\r
1071 #endif\r
1072 /*-----------------------------------------------------------*/\r
1073 \r
1074 #if ( configUSE_MUTEXES == 1 )\r
1075         BaseType_t MPU_xQueueGiveMutexRecursive( QueueHandle_t xMutex )\r
1076         {\r
1077         BaseType_t xReturn;\r
1078         BaseType_t xRunningPrivileged = prvRaisePrivilege();\r
1079 \r
1080                 xReturn = xQueueGiveMutexRecursive( xMutex );\r
1081                 portRESET_PRIVILEGE( xRunningPrivileged );\r
1082                 return xReturn;\r
1083         }\r
1084 #endif\r
1085 /*-----------------------------------------------------------*/\r
1086 \r
1087 #if ( configUSE_QUEUE_SETS == 1 )\r
1088         QueueSetHandle_t MPU_xQueueCreateSet( UBaseType_t uxEventQueueLength )\r
1089         {\r
1090         QueueSetHandle_t xReturn;\r
1091         BaseType_t xRunningPrivileged = prvRaisePrivilege();\r
1092 \r
1093                 xReturn = xQueueCreateSet( uxEventQueueLength );\r
1094                 portRESET_PRIVILEGE( xRunningPrivileged );\r
1095                 return xReturn;\r
1096         }\r
1097 #endif\r
1098 /*-----------------------------------------------------------*/\r
1099 \r
1100 #if ( configUSE_QUEUE_SETS == 1 )\r
1101         QueueSetMemberHandle_t MPU_xQueueSelectFromSet( QueueSetHandle_t xQueueSet, TickType_t xBlockTimeTicks )\r
1102         {\r
1103         QueueSetMemberHandle_t xReturn;\r
1104         BaseType_t xRunningPrivileged = prvRaisePrivilege();\r
1105 \r
1106                 xReturn = xQueueSelectFromSet( xQueueSet, xBlockTimeTicks );\r
1107                 portRESET_PRIVILEGE( xRunningPrivileged );\r
1108                 return xReturn;\r
1109         }\r
1110 #endif\r
1111 /*-----------------------------------------------------------*/\r
1112 \r
1113 #if ( configUSE_QUEUE_SETS == 1 )\r
1114         BaseType_t MPU_xQueueAddToSet( QueueSetMemberHandle_t xQueueOrSemaphore, QueueSetHandle_t xQueueSet )\r
1115         {\r
1116         BaseType_t xReturn;\r
1117         BaseType_t xRunningPrivileged = prvRaisePrivilege();\r
1118 \r
1119                 xReturn = xQueueAddToSet( xQueueOrSemaphore, xQueueSet );\r
1120                 portRESET_PRIVILEGE( xRunningPrivileged );\r
1121                 return xReturn;\r
1122         }\r
1123 #endif\r
1124 /*-----------------------------------------------------------*/\r
1125 \r
1126 #if ( configUSE_QUEUE_SETS == 1 )\r
1127         BaseType_t MPU_xQueueRemoveFromSet( QueueSetMemberHandle_t xQueueOrSemaphore, QueueSetHandle_t xQueueSet )\r
1128         {\r
1129         BaseType_t xReturn;\r
1130         BaseType_t xRunningPrivileged = prvRaisePrivilege();\r
1131 \r
1132                 xReturn = xQueueRemoveFromSet( xQueueOrSemaphore, xQueueSet );\r
1133                 portRESET_PRIVILEGE( xRunningPrivileged );\r
1134                 return xReturn;\r
1135         }\r
1136 #endif\r
1137 /*-----------------------------------------------------------*/\r
1138 \r
1139 #if configQUEUE_REGISTRY_SIZE > 0\r
1140         void MPU_vQueueAddToRegistry( QueueHandle_t xQueue, char *pcName )\r
1141         {\r
1142         BaseType_t xRunningPrivileged = prvRaisePrivilege();\r
1143 \r
1144                 vQueueAddToRegistry( xQueue, pcName );\r
1145 \r
1146                 portRESET_PRIVILEGE( xRunningPrivileged );\r
1147         }\r
1148 #endif\r
1149 /*-----------------------------------------------------------*/\r
1150 \r
1151 void MPU_vQueueDelete( QueueHandle_t xQueue )\r
1152 {\r
1153 BaseType_t xRunningPrivileged = prvRaisePrivilege();\r
1154 \r
1155         vQueueDelete( xQueue );\r
1156 \r
1157         portRESET_PRIVILEGE( xRunningPrivileged );\r
1158 }\r
1159 /*-----------------------------------------------------------*/\r
1160 \r
1161 #if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )\r
1162         \r
1163         void *MPU_pvPortMalloc( size_t xSize )\r
1164         {\r
1165         void *pvReturn;\r
1166         BaseType_t xRunningPrivileged = prvRaisePrivilege();\r
1167 \r
1168                 pvReturn = pvPortMalloc( xSize );\r
1169 \r
1170                 portRESET_PRIVILEGE( xRunningPrivileged );\r
1171 \r
1172                 return pvReturn;\r
1173         }\r
1174         \r
1175 #endif /* configSUPPORT_DYNAMIC_ALLOCATION */\r
1176 /*-----------------------------------------------------------*/\r
1177 \r
1178 #if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )\r
1179 \r
1180         void MPU_vPortFree( void *pv )\r
1181         {\r
1182         BaseType_t xRunningPrivileged = prvRaisePrivilege();\r
1183 \r
1184                 vPortFree( pv );\r
1185 \r
1186                 portRESET_PRIVILEGE( xRunningPrivileged );\r
1187         }\r
1188         \r
1189 #endif /* configSUPPORT_DYNAMIC_ALLOCATION */\r
1190 /*-----------------------------------------------------------*/\r
1191 \r
1192 void MPU_vPortInitialiseBlocks( void )\r
1193 {\r
1194 BaseType_t xRunningPrivileged = prvRaisePrivilege();\r
1195 \r
1196         vPortInitialiseBlocks();\r
1197 \r
1198         portRESET_PRIVILEGE( xRunningPrivileged );\r
1199 }\r
1200 /*-----------------------------------------------------------*/\r
1201 \r
1202 size_t MPU_xPortGetFreeHeapSize( void )\r
1203 {\r
1204 size_t xReturn;\r
1205 BaseType_t xRunningPrivileged = prvRaisePrivilege();\r
1206 \r
1207         xReturn = xPortGetFreeHeapSize();\r
1208 \r
1209         portRESET_PRIVILEGE( xRunningPrivileged );\r
1210 \r
1211         return xReturn;\r
1212 }\r
1213 \r
1214 /* Functions that the application writer wants to execute in privileged mode\r
1215 can be defined in application_defined_privileged_functions.h.  The functions\r
1216 must take the same format as those above whereby the privilege state on exit\r
1217 equals the privilege state on entry.  For example:\r
1218 \r
1219 void MPU_FunctionName( [parameters ] )\r
1220 {\r
1221 BaseType_t xRunningPrivileged = prvRaisePrivilege();\r
1222 \r
1223         FunctionName( [parameters ] );\r
1224 \r
1225         portRESET_PRIVILEGE( xRunningPrivileged );\r
1226 }\r
1227 */\r
1228 \r
1229 #if configINCLUDE_APPLICATION_DEFINED_PRIVILEGED_FUNCTIONS == 1\r
1230         #include "application_defined_privileged_functions.h"\r
1231 #endif\r
1232 \r