2 FreeRTOS V7.5.1 - Copyright (C) 2013 Real Time Engineers Ltd.
\r
4 VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
\r
6 ***************************************************************************
\r
8 * FreeRTOS provides completely free yet professionally developed, *
\r
9 * robust, strictly quality controlled, supported, and cross *
\r
10 * platform software that has become a de facto standard. *
\r
12 * Help yourself get started quickly and support the FreeRTOS *
\r
13 * project by purchasing a FreeRTOS tutorial book, reference *
\r
14 * manual, or both from: http://www.FreeRTOS.org/Documentation *
\r
18 ***************************************************************************
\r
20 This file is part of the FreeRTOS distribution.
\r
22 FreeRTOS is free software; you can redistribute it and/or modify it under
\r
23 the terms of the GNU General Public License (version 2) as published by the
\r
24 Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.
\r
26 >>! NOTE: The modification to the GPL is included to allow you to distribute
\r
27 >>! a combined work that includes FreeRTOS without being obliged to provide
\r
28 >>! the source code for proprietary components outside of the FreeRTOS
\r
31 FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
\r
32 WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
\r
33 FOR A PARTICULAR PURPOSE. Full license text is available from the following
\r
34 link: http://www.freertos.org/a00114.html
\r
38 ***************************************************************************
\r
40 * Having a problem? Start by reading the FAQ "My application does *
\r
41 * not run, what could be wrong?" *
\r
43 * http://www.FreeRTOS.org/FAQHelp.html *
\r
45 ***************************************************************************
\r
47 http://www.FreeRTOS.org - Documentation, books, training, latest versions,
\r
48 license and Real Time Engineers Ltd. contact details.
\r
50 http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
\r
51 including FreeRTOS+Trace - an indispensable productivity tool, a DOS
\r
52 compatible FAT file system, and our tiny thread aware UDP/IP stack.
\r
54 http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High
\r
55 Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS
\r
56 licenses offer ticketed support, indemnification and middleware.
\r
58 http://www.SafeRTOS.com - High Integrity Systems also provide a safety
\r
59 engineered and independently SIL3 certified version for use in safety and
\r
60 mission critical applications that require provable dependability.
\r
65 /*-----------------------------------------------------------
\r
66 * Implementation of functions defined in portable.h for the ARM CM4F port.
\r
67 *----------------------------------------------------------*/
\r
69 /* Scheduler includes. */
\r
70 #include "FreeRTOS.h"
\r
74 #error This port can only be used when the project options are configured to enable hardware floating point support.
\r
77 #ifndef configSYSTICK_CLOCK_HZ
\r
78 #define configSYSTICK_CLOCK_HZ configCPU_CLOCK_HZ
\r
81 /* Constants required to manipulate the core. Registers first... */
\r
82 #define portNVIC_SYSTICK_CTRL_REG ( * ( ( volatile unsigned long * ) 0xe000e010 ) )
\r
83 #define portNVIC_SYSTICK_LOAD_REG ( * ( ( volatile unsigned long * ) 0xe000e014 ) )
\r
84 #define portNVIC_SYSTICK_CURRENT_VALUE_REG ( * ( ( volatile unsigned long * ) 0xe000e018 ) )
\r
85 #define portNVIC_SYSPRI2_REG ( * ( ( volatile unsigned long * ) 0xe000ed20 ) )
\r
86 /* ...then bits in the registers. */
\r
87 #define portNVIC_SYSTICK_CLK_BIT ( 1UL << 2UL )
\r
88 #define portNVIC_SYSTICK_INT_BIT ( 1UL << 1UL )
\r
89 #define portNVIC_SYSTICK_ENABLE_BIT ( 1UL << 0UL )
\r
90 #define portNVIC_SYSTICK_COUNT_FLAG_BIT ( 1UL << 16UL )
\r
91 #define portNVIC_PENDSVCLEAR_BIT ( 1UL << 27UL )
\r
92 #define portNVIC_PEND_SYSTICK_CLEAR_BIT ( 1UL << 25UL )
\r
94 #define portNVIC_PENDSV_PRI ( ( ( unsigned long ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL )
\r
95 #define portNVIC_SYSTICK_PRI ( ( ( unsigned long ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL )
\r
97 /* Constants required to check the validity of an interrupt priority. */
\r
98 #define portFIRST_USER_INTERRUPT_NUMBER ( 16 )
\r
99 #define portNVIC_IP_REGISTERS_OFFSET_16 ( 0xE000E3F0 )
\r
100 #define portAIRCR_REG ( * ( ( volatile unsigned long * ) 0xE000ED0C ) )
\r
101 #define portMAX_8_BIT_VALUE ( ( unsigned char ) 0xff )
\r
102 #define portTOP_BIT_OF_BYTE ( ( unsigned char ) 0x80 )
\r
103 #define portMAX_PRIGROUP_BITS ( ( unsigned char ) 7 )
\r
104 #define portPRIORITY_GROUP_MASK ( 0x07UL << 8UL )
\r
105 #define portPRIGROUP_SHIFT ( 8UL )
\r
107 /* Constants required to manipulate the VFP. */
\r
108 #define portFPCCR ( ( volatile unsigned long * ) 0xe000ef34 ) /* Floating point context control register. */
\r
109 #define portASPEN_AND_LSPEN_BITS ( 0x3UL << 30UL )
\r
111 /* Constants required to set up the initial stack. */
\r
112 #define portINITIAL_XPSR ( 0x01000000 )
\r
113 #define portINITIAL_EXEC_RETURN ( 0xfffffffd )
\r
115 /* The systick is a 24-bit counter. */
\r
116 #define portMAX_24_BIT_NUMBER ( 0xffffffUL )
\r
118 /* A fiddle factor to estimate the number of SysTick counts that would have
\r
119 occurred while the SysTick counter is stopped during tickless idle
\r
121 #define portMISSED_COUNTS_FACTOR ( 45UL )
\r
123 /* Each task maintains its own interrupt status in the critical nesting
\r
125 static unsigned portBASE_TYPE uxCriticalNesting = 0xaaaaaaaa;
\r
128 * Setup the timer to generate the tick interrupts. The implementation in this
\r
129 * file is weak to allow application writers to change the timer used to
\r
130 * generate the tick interrupt.
\r
132 void vPortSetupTimerInterrupt( void );
\r
135 * Exception handlers.
\r
137 void xPortPendSVHandler( void ) __attribute__ (( naked ));
\r
138 void xPortSysTickHandler( void );
\r
139 void vPortSVCHandler( void ) __attribute__ (( naked ));
\r
142 * Start first task is a separate function so it can be tested in isolation.
\r
144 static void prvPortStartFirstTask( void ) __attribute__ (( naked ));
\r
147 * Function to enable the VFP.
\r
149 static void vPortEnableVFP( void ) __attribute__ (( naked ));
\r
151 /*-----------------------------------------------------------*/
\r
154 * The number of SysTick increments that make up one tick period.
\r
156 #if configUSE_TICKLESS_IDLE == 1
\r
157 static unsigned long ulTimerCountsForOneTick = 0;
\r
158 #endif /* configUSE_TICKLESS_IDLE */
\r
161 * The maximum number of tick periods that can be suppressed is limited by the
\r
162 * 24 bit resolution of the SysTick timer.
\r
164 #if configUSE_TICKLESS_IDLE == 1
\r
165 static unsigned long xMaximumPossibleSuppressedTicks = 0;
\r
166 #endif /* configUSE_TICKLESS_IDLE */
\r
169 * Compensate for the CPU cycles that pass while the SysTick is stopped (low
\r
170 * power functionality only.
\r
172 #if configUSE_TICKLESS_IDLE == 1
\r
173 static unsigned long ulStoppedTimerCompensation = 0;
\r
174 #endif /* configUSE_TICKLESS_IDLE */
\r
177 * Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure
\r
178 * FreeRTOS API functions are not called from interrupts that have been assigned
\r
179 * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY.
\r
181 #if ( configASSERT_DEFINED == 1 )
\r
182 static unsigned char ucMaxSysCallPriority = 0;
\r
183 static unsigned long ulMaxPRIGROUPValue = 0;
\r
184 static const volatile unsigned char * const pcInterruptPriorityRegisters = ( const volatile unsigned char * const ) portNVIC_IP_REGISTERS_OFFSET_16;
\r
185 #endif /* configASSERT_DEFINED */
\r
187 /*-----------------------------------------------------------*/
\r
190 * See header file for description.
\r
192 portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters )
\r
194 /* Simulate the stack frame as it would be created by a context switch
\r
197 /* Offset added to account for the way the MCU uses the stack on entry/exit
\r
198 of interrupts, and to ensure alignment. */
\r
201 *pxTopOfStack = portINITIAL_XPSR; /* xPSR */
\r
203 *pxTopOfStack = ( portSTACK_TYPE ) pxCode; /* PC */
\r
205 *pxTopOfStack = 0; /* LR */
\r
207 /* Save code space by skipping register initialisation. */
\r
208 pxTopOfStack -= 5; /* R12, R3, R2 and R1. */
\r
209 *pxTopOfStack = ( portSTACK_TYPE ) pvParameters; /* R0 */
\r
211 /* A save method is being used that requires each task to maintain its
\r
212 own exec return value. */
\r
214 *pxTopOfStack = portINITIAL_EXEC_RETURN;
\r
216 pxTopOfStack -= 8; /* R11, R10, R9, R8, R7, R6, R5 and R4. */
\r
218 return pxTopOfStack;
\r
220 /*-----------------------------------------------------------*/
\r
222 void vPortSVCHandler( void )
\r
225 " ldr r3, pxCurrentTCBConst2 \n" /* Restore the context. */
\r
226 " ldr r1, [r3] \n" /* Use pxCurrentTCBConst to get the pxCurrentTCB address. */
\r
227 " ldr r0, [r1] \n" /* The first item in pxCurrentTCB is the task top of stack. */
\r
228 " ldmia r0!, {r4-r11, r14} \n" /* Pop the registers that are not automatically saved on exception entry and the critical nesting count. */
\r
229 " msr psp, r0 \n" /* Restore the task stack pointer. */
\r
231 " msr basepri, r0 \n"
\r
235 "pxCurrentTCBConst2: .word pxCurrentTCB \n"
\r
238 /*-----------------------------------------------------------*/
\r
240 static void prvPortStartFirstTask( void )
\r
243 " ldr r0, =0xE000ED08 \n" /* Use the NVIC offset register to locate the stack. */
\r
246 " msr msp, r0 \n" /* Set the msp back to the start of the stack. */
\r
247 " cpsie i \n" /* Globally enable interrupts. */
\r
248 " svc 0 \n" /* System call to start first task. */
\r
252 /*-----------------------------------------------------------*/
\r
255 * See header file for description.
\r
257 portBASE_TYPE xPortStartScheduler( void )
\r
259 /* configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0.
\r
260 See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
\r
261 configASSERT( configMAX_SYSCALL_INTERRUPT_PRIORITY );
\r
263 #if( configASSERT_DEFINED == 1 )
\r
265 volatile unsigned long ulOriginalPriority;
\r
266 volatile char * const pcFirstUserPriorityRegister = ( volatile char * const ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER );
\r
267 volatile unsigned char ucMaxPriorityValue;
\r
269 /* Determine the maximum priority from which ISR safe FreeRTOS API
\r
270 functions can be called. ISR safe functions are those that end in
\r
271 "FromISR". FreeRTOS maintains separate thread and ISR API functions to
\r
272 ensure interrupt entry is as fast and simple as possible.
\r
274 Save the interrupt priority value that is about to be clobbered. */
\r
275 ulOriginalPriority = *pcFirstUserPriorityRegister;
\r
277 /* Determine the number of priority bits available. First write to all
\r
279 *pcFirstUserPriorityRegister = portMAX_8_BIT_VALUE;
\r
281 /* Read the value back to see how many bits stuck. */
\r
282 ucMaxPriorityValue = *pcFirstUserPriorityRegister;
\r
284 /* Use the same mask on the maximum system call priority. */
\r
285 ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;
\r
287 /* Calculate the maximum acceptable priority group value for the number
\r
288 of bits read back. */
\r
289 ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;
\r
290 while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
\r
292 ulMaxPRIGROUPValue--;
\r
293 ucMaxPriorityValue <<= ( unsigned char ) 0x01;
\r
296 /* Shift the priority group value back to its position within the AIRCR
\r
298 ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;
\r
299 ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;
\r
301 /* Restore the clobbered interrupt priority register to its original
\r
303 *pcFirstUserPriorityRegister = ulOriginalPriority;
\r
305 #endif /* conifgASSERT_DEFINED */
\r
307 /* Make PendSV and SysTick the lowest priority interrupts. */
\r
308 portNVIC_SYSPRI2_REG |= portNVIC_PENDSV_PRI;
\r
309 portNVIC_SYSPRI2_REG |= portNVIC_SYSTICK_PRI;
\r
311 /* Start the timer that generates the tick ISR. Interrupts are disabled
\r
313 vPortSetupTimerInterrupt();
\r
315 /* Initialise the critical nesting count ready for the first task. */
\r
316 uxCriticalNesting = 0;
\r
318 /* Ensure the VFP is enabled - it should be anyway. */
\r
321 /* Lazy save always. */
\r
322 *( portFPCCR ) |= portASPEN_AND_LSPEN_BITS;
\r
324 /* Start the first task. */
\r
325 prvPortStartFirstTask();
\r
327 /* Should not get here! */
\r
330 /*-----------------------------------------------------------*/
\r
332 void vPortEndScheduler( void )
\r
334 /* It is unlikely that the CM4F port will require this function as there
\r
335 is nothing to return to. */
\r
337 /*-----------------------------------------------------------*/
\r
339 void vPortYield( void )
\r
341 /* Set a PendSV to request a context switch. */
\r
342 portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
\r
344 /* Barriers are normally not required but do ensure the code is completely
\r
345 within the specified behaviour for the architecture. */
\r
346 __asm volatile( "dsb" );
\r
347 __asm volatile( "isb" );
\r
349 /*-----------------------------------------------------------*/
\r
351 void vPortEnterCritical( void )
\r
353 portDISABLE_INTERRUPTS();
\r
354 uxCriticalNesting++;
\r
355 __asm volatile( "dsb" );
\r
356 __asm volatile( "isb" );
\r
358 /*-----------------------------------------------------------*/
\r
360 void vPortExitCritical( void )
\r
362 uxCriticalNesting--;
\r
363 if( uxCriticalNesting == 0 )
\r
365 portENABLE_INTERRUPTS();
\r
368 /*-----------------------------------------------------------*/
\r
370 __attribute__(( naked )) unsigned long ulPortSetInterruptMask( void )
\r
374 " mrs r0, basepri \n" \
\r
376 " msr basepri, r1 \n" \
\r
378 :: "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "r0", "r1" \
\r
381 /* This return will not be reached but is necessary to prevent compiler
\r
385 /*-----------------------------------------------------------*/
\r
387 __attribute__(( naked )) void vPortClearInterruptMask( unsigned long ulNewMaskValue )
\r
391 " msr basepri, r0 \n" \
\r
396 /* Just to avoid compiler warnings. */
\r
397 ( void ) ulNewMaskValue;
\r
399 /*-----------------------------------------------------------*/
\r
401 void xPortPendSVHandler( void )
\r
403 /* This is a naked function. */
\r
409 " ldr r3, pxCurrentTCBConst \n" /* Get the location of the current TCB. */
\r
412 " tst r14, #0x10 \n" /* Is the task using the FPU context? If so, push high vfp registers. */
\r
414 " vstmdbeq r0!, {s16-s31} \n"
\r
416 " stmdb r0!, {r4-r11, r14} \n" /* Save the core registers. */
\r
418 " str r0, [r2] \n" /* Save the new top of stack into the first member of the TCB. */
\r
420 " stmdb sp!, {r3, r14} \n"
\r
422 " msr basepri, r0 \n"
\r
423 " bl vTaskSwitchContext \n"
\r
425 " msr basepri, r0 \n"
\r
426 " ldmia sp!, {r3, r14} \n"
\r
428 " ldr r1, [r3] \n" /* The first item in pxCurrentTCB is the task top of stack. */
\r
431 " ldmia r0!, {r4-r11, r14} \n" /* Pop the core registers. */
\r
433 " tst r14, #0x10 \n" /* Is the task using the FPU context? If so, pop the high vfp registers too. */
\r
435 " vldmiaeq r0!, {s16-s31} \n"
\r
441 "pxCurrentTCBConst: .word pxCurrentTCB \n"
\r
442 ::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY)
\r
445 /*-----------------------------------------------------------*/
\r
447 void xPortSysTickHandler( void )
\r
449 /* The SysTick runs at the lowest interrupt priority, so when this interrupt
\r
450 executes all interrupts must be unmasked. There is therefore no need to
\r
451 save and then restore the interrupt mask value as its value is already
\r
453 ( void ) portSET_INTERRUPT_MASK_FROM_ISR();
\r
455 /* Increment the RTOS tick. */
\r
456 if( xTaskIncrementTick() != pdFALSE )
\r
458 /* A context switch is required. Context switching is performed in
\r
459 the PendSV interrupt. Pend the PendSV interrupt. */
\r
460 portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
\r
463 portCLEAR_INTERRUPT_MASK_FROM_ISR( 0 );
\r
465 /*-----------------------------------------------------------*/
\r
467 #if configUSE_TICKLESS_IDLE == 1
\r
469 __attribute__((weak)) void vPortSuppressTicksAndSleep( portTickType xExpectedIdleTime )
\r
471 unsigned long ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements;
\r
472 portTickType xModifiableIdleTime;
\r
474 /* Make sure the SysTick reload value does not overflow the counter. */
\r
475 if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks )
\r
477 xExpectedIdleTime = xMaximumPossibleSuppressedTicks;
\r
480 /* Stop the SysTick momentarily. The time the SysTick is stopped for
\r
481 is accounted for as best it can be, but using the tickless mode will
\r
482 inevitably result in some tiny drift of the time maintained by the
\r
483 kernel with respect to calendar time. */
\r
484 portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT;
\r
486 /* Calculate the reload value required to wait xExpectedIdleTime
\r
487 tick periods. -1 is used because this code will execute part way
\r
488 through one of the tick periods. */
\r
489 ulReloadValue = portNVIC_SYSTICK_CURRENT_VALUE_REG + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) );
\r
490 if( ulReloadValue > ulStoppedTimerCompensation )
\r
492 ulReloadValue -= ulStoppedTimerCompensation;
\r
495 /* Enter a critical section but don't use the taskENTER_CRITICAL()
\r
496 method as that will mask interrupts that should exit sleep mode. */
\r
497 __asm volatile( "cpsid i" );
\r
499 /* If a context switch is pending or a task is waiting for the scheduler
\r
500 to be unsuspended then abandon the low power entry. */
\r
501 if( eTaskConfirmSleepModeStatus() == eAbortSleep )
\r
503 /* Restart SysTick. */
\r
504 portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;
\r
506 /* Re-enable interrupts - see comments above the cpsid instruction()
\r
508 __asm volatile( "cpsie i" );
\r
512 /* Set the new reload value. */
\r
513 portNVIC_SYSTICK_LOAD_REG = ulReloadValue;
\r
515 /* Clear the SysTick count flag and set the count value back to
\r
517 portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
\r
519 /* Restart SysTick. */
\r
520 portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;
\r
522 /* Sleep until something happens. configPRE_SLEEP_PROCESSING() can
\r
523 set its parameter to 0 to indicate that its implementation contains
\r
524 its own wait for interrupt or wait for event instruction, and so wfi
\r
525 should not be executed again. However, the original expected idle
\r
526 time variable must remain unmodified, so a copy is taken. */
\r
527 xModifiableIdleTime = xExpectedIdleTime;
\r
528 configPRE_SLEEP_PROCESSING( xModifiableIdleTime );
\r
529 if( xModifiableIdleTime > 0 )
\r
531 __asm volatile( "dsb" );
\r
532 __asm volatile( "wfi" );
\r
533 __asm volatile( "isb" );
\r
535 configPOST_SLEEP_PROCESSING( xExpectedIdleTime );
\r
537 /* Stop SysTick. Again, the time the SysTick is stopped for is
\r
538 accounted for as best it can be, but using the tickless mode will
\r
539 inevitably result in some tiny drift of the time maintained by the
\r
540 kernel with respect to calendar time. */
\r
541 portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT;
\r
543 /* Re-enable interrupts - see comments above the cpsid instruction()
\r
545 __asm volatile( "cpsie i" );
\r
547 if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )
\r
549 /* The tick interrupt has already executed, and the SysTick
\r
550 count reloaded with ulReloadValue. Reset the
\r
551 portNVIC_SYSTICK_LOAD_REG with whatever remains of this tick
\r
553 portNVIC_SYSTICK_LOAD_REG = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG );
\r
555 /* The tick interrupt handler will already have pended the tick
\r
556 processing in the kernel. As the pending tick will be
\r
557 processed as soon as this function exits, the tick value
\r
558 maintained by the tick is stepped forward by one less than the
\r
559 time spent waiting. */
\r
560 ulCompleteTickPeriods = xExpectedIdleTime - 1UL;
\r
564 /* Something other than the tick interrupt ended the sleep.
\r
565 Work out how long the sleep lasted rounded to complete tick
\r
566 periods (not the ulReload value which accounted for part
\r
568 ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - portNVIC_SYSTICK_CURRENT_VALUE_REG;
\r
570 /* How many complete tick periods passed while the processor
\r
572 ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick;
\r
574 /* The reload value is set to whatever fraction of a single tick
\r
576 portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1 ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements;
\r
579 /* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG
\r
580 again, then set portNVIC_SYSTICK_LOAD_REG back to its standard
\r
582 portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
\r
583 portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;
\r
585 vTaskStepTick( ulCompleteTickPeriods );
\r
587 /* The counter must start by the time the reload value is reset. */
\r
588 configASSERT( portNVIC_SYSTICK_CURRENT_VALUE_REG );
\r
589 portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
\r
593 #endif /* #if configUSE_TICKLESS_IDLE */
\r
594 /*-----------------------------------------------------------*/
\r
597 * Setup the systick timer to generate the tick interrupts at the required
\r
600 __attribute__(( weak )) void vPortSetupTimerInterrupt( void )
\r
602 /* Calculate the constants required to configure the tick interrupt. */
\r
603 #if configUSE_TICKLESS_IDLE == 1
\r
605 ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ );
\r
606 xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick;
\r
607 ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ );
\r
609 #endif /* configUSE_TICKLESS_IDLE */
\r
611 /* Configure SysTick to interrupt at the requested rate. */
\r
612 portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;;
\r
613 portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;
\r
615 /*-----------------------------------------------------------*/
\r
617 /* This is a naked function. */
\r
618 static void vPortEnableVFP( void )
\r
622 " ldr.w r0, =0xE000ED88 \n" /* The FPU enable bits are in the CPACR. */
\r
625 " orr r1, r1, #( 0xf << 20 ) \n" /* Enable CP10 and CP11 coprocessors, then save back. */
\r
630 /*-----------------------------------------------------------*/
\r
632 #if( configASSERT_DEFINED == 1 )
\r
634 void vPortValidateInterruptPriority( void )
\r
636 unsigned long ulCurrentInterrupt;
\r
637 unsigned char ucCurrentPriority;
\r
639 /* Obtain the number of the currently executing interrupt. */
\r
640 __asm volatile( "mrs %0, ipsr" : "=r"( ulCurrentInterrupt ) );
\r
642 /* Is the interrupt number a user defined interrupt? */
\r
643 if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER )
\r
645 /* Look up the interrupt's priority. */
\r
646 ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ];
\r
648 /* The following assertion will fail if a service routine (ISR) for
\r
649 an interrupt that has been assigned a priority above
\r
650 configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API
\r
651 function. ISR safe FreeRTOS API functions must *only* be called
\r
652 from interrupts that have been assigned a priority at or below
\r
653 configMAX_SYSCALL_INTERRUPT_PRIORITY.
\r
655 Numerically low interrupt priority numbers represent logically high
\r
656 interrupt priorities, therefore the priority of the interrupt must
\r
657 be set to a value equal to or numerically *higher* than
\r
658 configMAX_SYSCALL_INTERRUPT_PRIORITY.
\r
660 Interrupts that use the FreeRTOS API must not be left at their
\r
661 default priority of zero as that is the highest possible priority,
\r
662 which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY,
\r
663 and therefore also guaranteed to be invalid.
\r
665 FreeRTOS maintains separate thread and ISR API functions to ensure
\r
666 interrupt entry is as fast and simple as possible.
\r
668 The following links provide detailed information:
\r
669 http://www.freertos.org/RTOS-Cortex-M3-M4.html
\r
670 http://www.freertos.org/FAQHelp.html */
\r
671 configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );
\r
674 /* Priority grouping: The interrupt controller (NVIC) allows the bits
\r
675 that define each interrupt's priority to be split between bits that
\r
676 define the interrupt's pre-emption priority bits and bits that define
\r
677 the interrupt's sub-priority. For simplicity all bits must be defined
\r
678 to be pre-emption priority bits. The following assertion will fail if
\r
679 this is not the case (if some bits represent a sub-priority).
\r
681 If the application only uses CMSIS libraries for interrupt
\r
682 configuration then the correct setting can be achieved on all Cortex-M
\r
683 devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the
\r
684 scheduler. Note however that some vendor specific peripheral libraries
\r
685 assume a non-zero priority group setting, in which cases using a value
\r
686 of zero will result in unpredicable behaviour. */
\r
687 configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );
\r
690 #endif /* configASSERT_DEFINED */
\r
projects / freertos / blob