2 FreeRTOS V9.0.1 - Copyright (C) 2017 Real Time Engineers Ltd.
\r
5 VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
\r
7 This file is part of the FreeRTOS distribution.
\r
9 FreeRTOS is free software; you can redistribute it and/or modify it under
\r
10 the terms of the GNU General Public License (version 2) as published by the
\r
11 Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception.
\r
13 ***************************************************************************
\r
14 >>! NOTE: The modification to the GPL is included to allow you to !<<
\r
15 >>! distribute a combined work that includes FreeRTOS without being !<<
\r
16 >>! obliged to provide the source code for proprietary components !<<
\r
17 >>! outside of the FreeRTOS kernel. !<<
\r
18 ***************************************************************************
\r
20 FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
\r
21 WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
\r
22 FOR A PARTICULAR PURPOSE. Full license text is available on the following
\r
23 link: http://www.freertos.org/a00114.html
\r
25 ***************************************************************************
\r
27 * FreeRTOS provides completely free yet professionally developed, *
\r
28 * robust, strictly quality controlled, supported, and cross *
\r
29 * platform software that is more than just the market leader, it *
\r
30 * is the industry's de facto standard. *
\r
32 * Help yourself get started quickly while simultaneously helping *
\r
33 * to support the FreeRTOS project by purchasing a FreeRTOS *
\r
34 * tutorial book, reference manual, or both: *
\r
35 * http://www.FreeRTOS.org/Documentation *
\r
37 ***************************************************************************
\r
39 http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading
\r
40 the FAQ page "My application does not run, what could be wrong?". Have you
\r
41 defined configASSERT()?
\r
43 http://www.FreeRTOS.org/support - In return for receiving this top quality
\r
44 embedded software for free we request you assist our global community by
\r
45 participating in the support forum.
\r
47 http://www.FreeRTOS.org/training - Investing in training allows your team to
\r
48 be as productive as possible as early as possible. Now you can receive
\r
49 FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers
\r
50 Ltd, and the world's leading authority on the world's leading RTOS.
\r
52 http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
\r
53 including FreeRTOS+Trace - an indispensable productivity tool, a DOS
\r
54 compatible FAT file system, and our tiny thread aware UDP/IP stack.
\r
56 http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.
\r
57 Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.
\r
59 http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High
\r
60 Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS
\r
61 licenses offer ticketed support, indemnification and commercial middleware.
\r
63 http://www.SafeRTOS.com - High Integrity Systems also provide a safety
\r
64 engineered and independently SIL3 certified version for use in safety and
\r
65 mission critical applications that require provable dependability.
\r
70 /*-----------------------------------------------------------
\r
71 * Implementation of functions defined in portable.h for the ARM CM4F port.
\r
72 *----------------------------------------------------------*/
\r
74 /* Scheduler includes. */
\r
75 #include "FreeRTOS.h"
\r
79 #error This port can only be used when the project options are configured to enable hardware floating point support.
\r
82 #ifndef configSYSTICK_CLOCK_HZ
\r
83 #define configSYSTICK_CLOCK_HZ configCPU_CLOCK_HZ
\r
84 /* Ensure the SysTick is clocked at the same frequency as the core. */
\r
85 #define portNVIC_SYSTICK_CLK_BIT ( 1UL << 2UL )
\r
87 /* The way the SysTick is clocked is not modified in case it is not the same
\r
89 #define portNVIC_SYSTICK_CLK_BIT ( 0 )
\r
92 /* Constants required to manipulate the core. Registers first... */
\r
93 #define portNVIC_SYSTICK_CTRL_REG ( * ( ( volatile uint32_t * ) 0xe000e010 ) )
\r
94 #define portNVIC_SYSTICK_LOAD_REG ( * ( ( volatile uint32_t * ) 0xe000e014 ) )
\r
95 #define portNVIC_SYSTICK_CURRENT_VALUE_REG ( * ( ( volatile uint32_t * ) 0xe000e018 ) )
\r
96 #define portNVIC_SYSPRI2_REG ( * ( ( volatile uint32_t * ) 0xe000ed20 ) )
\r
97 /* ...then bits in the registers. */
\r
98 #define portNVIC_SYSTICK_INT_BIT ( 1UL << 1UL )
\r
99 #define portNVIC_SYSTICK_ENABLE_BIT ( 1UL << 0UL )
\r
100 #define portNVIC_SYSTICK_COUNT_FLAG_BIT ( 1UL << 16UL )
\r
101 #define portNVIC_PENDSVCLEAR_BIT ( 1UL << 27UL )
\r
102 #define portNVIC_PEND_SYSTICK_CLEAR_BIT ( 1UL << 25UL )
\r
104 /* Constants used to detect a Cortex-M7 r0p1 core, which should use the ARM_CM7
\r
106 #define portCPUID ( * ( ( volatile uint32_t * ) 0xE000ed00 ) )
\r
107 #define portCORTEX_M7_r0p1_ID ( 0x410FC271UL )
\r
108 #define portCORTEX_M7_r0p0_ID ( 0x410FC270UL )
\r
110 #define portNVIC_PENDSV_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL )
\r
111 #define portNVIC_SYSTICK_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL )
\r
113 /* Constants required to check the validity of an interrupt priority. */
\r
114 #define portFIRST_USER_INTERRUPT_NUMBER ( 16 )
\r
115 #define portNVIC_IP_REGISTERS_OFFSET_16 ( 0xE000E3F0 )
\r
116 #define portAIRCR_REG ( * ( ( volatile uint32_t * ) 0xE000ED0C ) )
\r
117 #define portMAX_8_BIT_VALUE ( ( uint8_t ) 0xff )
\r
118 #define portTOP_BIT_OF_BYTE ( ( uint8_t ) 0x80 )
\r
119 #define portMAX_PRIGROUP_BITS ( ( uint8_t ) 7 )
\r
120 #define portPRIORITY_GROUP_MASK ( 0x07UL << 8UL )
\r
121 #define portPRIGROUP_SHIFT ( 8UL )
\r
123 /* Masks off all bits but the VECTACTIVE bits in the ICSR register. */
\r
124 #define portVECTACTIVE_MASK ( 0xFFUL )
\r
126 /* Constants required to manipulate the VFP. */
\r
127 #define portFPCCR ( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating point context control register. */
\r
128 #define portASPEN_AND_LSPEN_BITS ( 0x3UL << 30UL )
\r
130 /* Constants required to set up the initial stack. */
\r
131 #define portINITIAL_XPSR ( 0x01000000 )
\r
132 #define portINITIAL_EXEC_RETURN ( 0xfffffffd )
\r
134 /* The systick is a 24-bit counter. */
\r
135 #define portMAX_24_BIT_NUMBER ( 0xffffffUL )
\r
137 /* For strict compliance with the Cortex-M spec the task start address should
\r
138 have bit-0 clear, as it is loaded into the PC on exit from an ISR. */
\r
139 #define portSTART_ADDRESS_MASK ( ( StackType_t ) 0xfffffffeUL )
\r
141 /* A fiddle factor to estimate the number of SysTick counts that would have
\r
142 occurred while the SysTick counter is stopped during tickless idle
\r
144 #define portMISSED_COUNTS_FACTOR ( 45UL )
\r
146 /* Let the user override the pre-loading of the initial LR with the address of
\r
147 prvTaskExitError() in case it messes up unwinding of the stack in the
\r
149 #ifdef configTASK_RETURN_ADDRESS
\r
150 #define portTASK_RETURN_ADDRESS configTASK_RETURN_ADDRESS
\r
152 #define portTASK_RETURN_ADDRESS prvTaskExitError
\r
156 * Setup the timer to generate the tick interrupts. The implementation in this
\r
157 * file is weak to allow application writers to change the timer used to
\r
158 * generate the tick interrupt.
\r
160 void vPortSetupTimerInterrupt( void );
\r
163 * Exception handlers.
\r
165 void xPortPendSVHandler( void ) __attribute__ (( naked ));
\r
166 void xPortSysTickHandler( void );
\r
167 void vPortSVCHandler( void ) __attribute__ (( naked ));
\r
170 * Start first task is a separate function so it can be tested in isolation.
\r
172 static void prvPortStartFirstTask( void ) __attribute__ (( naked ));
\r
175 * Function to enable the VFP.
\r
177 static void vPortEnableVFP( void ) __attribute__ (( naked ));
\r
180 * Used to catch tasks that attempt to return from their implementing function.
\r
182 static void prvTaskExitError( void );
\r
184 /*-----------------------------------------------------------*/
\r
186 /* Each task maintains its own interrupt status in the critical nesting
\r
188 static UBaseType_t uxCriticalNesting = 0xaaaaaaaa;
\r
191 * The number of SysTick increments that make up one tick period.
\r
193 #if( configUSE_TICKLESS_IDLE == 1 )
\r
194 static uint32_t ulTimerCountsForOneTick = 0;
\r
195 #endif /* configUSE_TICKLESS_IDLE */
\r
198 * The maximum number of tick periods that can be suppressed is limited by the
\r
199 * 24 bit resolution of the SysTick timer.
\r
201 #if( configUSE_TICKLESS_IDLE == 1 )
\r
202 static uint32_t xMaximumPossibleSuppressedTicks = 0;
\r
203 #endif /* configUSE_TICKLESS_IDLE */
\r
206 * Compensate for the CPU cycles that pass while the SysTick is stopped (low
\r
207 * power functionality only.
\r
209 #if( configUSE_TICKLESS_IDLE == 1 )
\r
210 static uint32_t ulStoppedTimerCompensation = 0;
\r
211 #endif /* configUSE_TICKLESS_IDLE */
\r
214 * Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure
\r
215 * FreeRTOS API functions are not called from interrupts that have been assigned
\r
216 * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY.
\r
218 #if( configASSERT_DEFINED == 1 )
\r
219 static uint8_t ucMaxSysCallPriority = 0;
\r
220 static uint32_t ulMaxPRIGROUPValue = 0;
\r
221 static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const volatile uint8_t * const ) portNVIC_IP_REGISTERS_OFFSET_16;
\r
222 #endif /* configASSERT_DEFINED */
\r
224 /*-----------------------------------------------------------*/
\r
227 * See header file for description.
\r
229 StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
\r
231 /* Simulate the stack frame as it would be created by a context switch
\r
234 /* Offset added to account for the way the MCU uses the stack on entry/exit
\r
235 of interrupts, and to ensure alignment. */
\r
238 *pxTopOfStack = portINITIAL_XPSR; /* xPSR */
\r
240 *pxTopOfStack = ( ( StackType_t ) pxCode ) & portSTART_ADDRESS_MASK; /* PC */
\r
242 *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */
\r
244 /* Save code space by skipping register initialisation. */
\r
245 pxTopOfStack -= 5; /* R12, R3, R2 and R1. */
\r
246 *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
\r
248 /* A save method is being used that requires each task to maintain its
\r
249 own exec return value. */
\r
251 *pxTopOfStack = portINITIAL_EXEC_RETURN;
\r
253 pxTopOfStack -= 8; /* R11, R10, R9, R8, R7, R6, R5 and R4. */
\r
255 return pxTopOfStack;
\r
257 /*-----------------------------------------------------------*/
\r
259 static void prvTaskExitError( void )
\r
261 /* A function that implements a task must not exit or attempt to return to
\r
262 its caller as there is nothing to return to. If a task wants to exit it
\r
263 should instead call vTaskDelete( NULL ).
\r
265 Artificially force an assert() to be triggered if configASSERT() is
\r
266 defined, then stop here so application writers can catch the error. */
\r
267 configASSERT( uxCriticalNesting == ~0UL );
\r
268 portDISABLE_INTERRUPTS();
\r
271 /*-----------------------------------------------------------*/
\r
273 void vPortSVCHandler( void )
\r
276 " ldr r3, pxCurrentTCBConst2 \n" /* Restore the context. */
\r
277 " ldr r1, [r3] \n" /* Use pxCurrentTCBConst to get the pxCurrentTCB address. */
\r
278 " ldr r0, [r1] \n" /* The first item in pxCurrentTCB is the task top of stack. */
\r
279 " ldmia r0!, {r4-r11, r14} \n" /* Pop the registers that are not automatically saved on exception entry and the critical nesting count. */
\r
280 " msr psp, r0 \n" /* Restore the task stack pointer. */
\r
283 " msr basepri, r0 \n"
\r
287 "pxCurrentTCBConst2: .word pxCurrentTCB \n"
\r
290 /*-----------------------------------------------------------*/
\r
292 static void prvPortStartFirstTask( void )
\r
294 /* Start the first task. This also clears the bit that indicates the FPU is
\r
295 in use in case the FPU was used before the scheduler was started - which
\r
296 would otherwise result in the unnecessary leaving of space in the SVC stack
\r
297 for lazy saving of FPU registers. */
\r
299 " ldr r0, =0xE000ED08 \n" /* Use the NVIC offset register to locate the stack. */
\r
302 " msr msp, r0 \n" /* Set the msp back to the start of the stack. */
\r
303 " mov r0, #0 \n" /* Clear the bit that indicates the FPU is in use, see comment above. */
\r
304 " msr control, r0 \n"
\r
305 " cpsie i \n" /* Globally enable interrupts. */
\r
309 " svc 0 \n" /* System call to start first task. */
\r
313 /*-----------------------------------------------------------*/
\r
316 * See header file for description.
\r
318 BaseType_t xPortStartScheduler( void )
\r
320 /* configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0.
\r
321 See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
\r
322 configASSERT( configMAX_SYSCALL_INTERRUPT_PRIORITY );
\r
324 /* This port can be used on all revisions of the Cortex-M7 core other than
\r
325 the r0p1 parts. r0p1 parts should use the port from the
\r
326 /source/portable/GCC/ARM_CM7/r0p1 directory. */
\r
327 configASSERT( portCPUID != portCORTEX_M7_r0p1_ID );
\r
328 configASSERT( portCPUID != portCORTEX_M7_r0p0_ID );
\r
330 #if( configASSERT_DEFINED == 1 )
\r
332 volatile uint32_t ulOriginalPriority;
\r
333 volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER );
\r
334 volatile uint8_t ucMaxPriorityValue;
\r
336 /* Determine the maximum priority from which ISR safe FreeRTOS API
\r
337 functions can be called. ISR safe functions are those that end in
\r
338 "FromISR". FreeRTOS maintains separate thread and ISR API functions to
\r
339 ensure interrupt entry is as fast and simple as possible.
\r
341 Save the interrupt priority value that is about to be clobbered. */
\r
342 ulOriginalPriority = *pucFirstUserPriorityRegister;
\r
344 /* Determine the number of priority bits available. First write to all
\r
346 *pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;
\r
348 /* Read the value back to see how many bits stuck. */
\r
349 ucMaxPriorityValue = *pucFirstUserPriorityRegister;
\r
351 /* Use the same mask on the maximum system call priority. */
\r
352 ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;
\r
354 /* Calculate the maximum acceptable priority group value for the number
\r
355 of bits read back. */
\r
356 ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;
\r
357 while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
\r
359 ulMaxPRIGROUPValue--;
\r
360 ucMaxPriorityValue <<= ( uint8_t ) 0x01;
\r
363 #ifdef __NVIC_PRIO_BITS
\r
365 /* Check the CMSIS configuration that defines the number of
\r
366 priority bits matches the number of priority bits actually queried
\r
367 from the hardware. */
\r
368 configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == __NVIC_PRIO_BITS );
\r
372 #ifdef configPRIO_BITS
\r
374 /* Check the FreeRTOS configuration that defines the number of
\r
375 priority bits matches the number of priority bits actually queried
\r
376 from the hardware. */
\r
377 configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == configPRIO_BITS );
\r
381 /* Shift the priority group value back to its position within the AIRCR
\r
383 ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;
\r
384 ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;
\r
386 /* Restore the clobbered interrupt priority register to its original
\r
388 *pucFirstUserPriorityRegister = ulOriginalPriority;
\r
390 #endif /* conifgASSERT_DEFINED */
\r
392 /* Make PendSV and SysTick the lowest priority interrupts. */
\r
393 portNVIC_SYSPRI2_REG |= portNVIC_PENDSV_PRI;
\r
394 portNVIC_SYSPRI2_REG |= portNVIC_SYSTICK_PRI;
\r
396 /* Start the timer that generates the tick ISR. Interrupts are disabled
\r
398 vPortSetupTimerInterrupt();
\r
400 /* Initialise the critical nesting count ready for the first task. */
\r
401 uxCriticalNesting = 0;
\r
403 /* Ensure the VFP is enabled - it should be anyway. */
\r
406 /* Lazy save always. */
\r
407 *( portFPCCR ) |= portASPEN_AND_LSPEN_BITS;
\r
409 /* Start the first task. */
\r
410 prvPortStartFirstTask();
\r
412 /* Should never get here as the tasks will now be executing! Call the task
\r
413 exit error function to prevent compiler warnings about a static function
\r
414 not being called in the case that the application writer overrides this
\r
415 functionality by defining configTASK_RETURN_ADDRESS. Call
\r
416 vTaskSwitchContext() so link time optimisation does not remove the
\r
418 prvTaskExitError();
\r
419 vTaskSwitchContext();
\r
421 /* Should not get here! */
\r
424 /*-----------------------------------------------------------*/
\r
426 void vPortEndScheduler( void )
\r
428 /* Not implemented in ports where there is nothing to return to.
\r
429 Artificially force an assert. */
\r
430 configASSERT( uxCriticalNesting == 1000UL );
\r
432 /*-----------------------------------------------------------*/
\r
434 void vPortEnterCritical( void )
\r
436 portDISABLE_INTERRUPTS();
\r
437 uxCriticalNesting++;
\r
439 /* This is not the interrupt safe version of the enter critical function so
\r
440 assert() if it is being called from an interrupt context. Only API
\r
441 functions that end in "FromISR" can be used in an interrupt. Only assert if
\r
442 the critical nesting count is 1 to protect against recursive calls if the
\r
443 assert function also uses a critical section. */
\r
444 if( uxCriticalNesting == 1 )
\r
446 configASSERT( ( portNVIC_INT_CTRL_REG & portVECTACTIVE_MASK ) == 0 );
\r
449 /*-----------------------------------------------------------*/
\r
451 void vPortExitCritical( void )
\r
453 configASSERT( uxCriticalNesting );
\r
454 uxCriticalNesting--;
\r
455 if( uxCriticalNesting == 0 )
\r
457 portENABLE_INTERRUPTS();
\r
460 /*-----------------------------------------------------------*/
\r
462 void xPortPendSVHandler( void )
\r
464 /* This is a naked function. */
\r
471 " ldr r3, pxCurrentTCBConst \n" /* Get the location of the current TCB. */
\r
474 " tst r14, #0x10 \n" /* Is the task using the FPU context? If so, push high vfp registers. */
\r
476 " vstmdbeq r0!, {s16-s31} \n"
\r
478 " stmdb r0!, {r4-r11, r14} \n" /* Save the core registers. */
\r
479 " str r0, [r2] \n" /* Save the new top of stack into the first member of the TCB. */
\r
481 " stmdb sp!, {r3} \n"
\r
483 " msr basepri, r0 \n"
\r
486 " bl vTaskSwitchContext \n"
\r
488 " msr basepri, r0 \n"
\r
489 " ldmia sp!, {r3} \n"
\r
491 " ldr r1, [r3] \n" /* The first item in pxCurrentTCB is the task top of stack. */
\r
494 " ldmia r0!, {r4-r11, r14} \n" /* Pop the core registers. */
\r
496 " tst r14, #0x10 \n" /* Is the task using the FPU context? If so, pop the high vfp registers too. */
\r
498 " vldmiaeq r0!, {s16-s31} \n"
\r
503 #ifdef WORKAROUND_PMU_CM001 /* XMC4000 specific errata workaround. */
\r
504 #if WORKAROUND_PMU_CM001 == 1
\r
513 "pxCurrentTCBConst: .word pxCurrentTCB \n"
\r
514 ::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY)
\r
517 /*-----------------------------------------------------------*/
\r
519 void xPortSysTickHandler( void )
\r
521 /* The SysTick runs at the lowest interrupt priority, so when this interrupt
\r
522 executes all interrupts must be unmasked. There is therefore no need to
\r
523 save and then restore the interrupt mask value as its value is already
\r
525 portDISABLE_INTERRUPTS();
\r
527 /* Increment the RTOS tick. */
\r
528 if( xTaskIncrementTick() != pdFALSE )
\r
530 /* A context switch is required. Context switching is performed in
\r
531 the PendSV interrupt. Pend the PendSV interrupt. */
\r
532 portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
\r
535 portENABLE_INTERRUPTS();
\r
537 /*-----------------------------------------------------------*/
\r
539 #if( configUSE_TICKLESS_IDLE == 1 )
\r
541 __attribute__((weak)) void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )
\r
543 uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements;
\r
544 TickType_t xModifiableIdleTime;
\r
546 /* Make sure the SysTick reload value does not overflow the counter. */
\r
547 if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks )
\r
549 xExpectedIdleTime = xMaximumPossibleSuppressedTicks;
\r
552 /* Stop the SysTick momentarily. The time the SysTick is stopped for
\r
553 is accounted for as best it can be, but using the tickless mode will
\r
554 inevitably result in some tiny drift of the time maintained by the
\r
555 kernel with respect to calendar time. */
\r
556 portNVIC_SYSTICK_CTRL_REG &= ~portNVIC_SYSTICK_ENABLE_BIT;
\r
558 /* Calculate the reload value required to wait xExpectedIdleTime
\r
559 tick periods. -1 is used because this code will execute part way
\r
560 through one of the tick periods. */
\r
561 ulReloadValue = portNVIC_SYSTICK_CURRENT_VALUE_REG + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) );
\r
562 if( ulReloadValue > ulStoppedTimerCompensation )
\r
564 ulReloadValue -= ulStoppedTimerCompensation;
\r
567 /* Enter a critical section but don't use the taskENTER_CRITICAL()
\r
568 method as that will mask interrupts that should exit sleep mode. */
\r
569 __asm volatile( "cpsid i" ::: "memory" );
\r
570 __asm volatile( "dsb" );
\r
571 __asm volatile( "isb" );
\r
573 /* If a context switch is pending or a task is waiting for the scheduler
\r
574 to be unsuspended then abandon the low power entry. */
\r
575 if( eTaskConfirmSleepModeStatus() == eAbortSleep )
\r
577 /* Restart from whatever is left in the count register to complete
\r
578 this tick period. */
\r
579 portNVIC_SYSTICK_LOAD_REG = portNVIC_SYSTICK_CURRENT_VALUE_REG;
\r
581 /* Restart SysTick. */
\r
582 portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
\r
584 /* Reset the reload register to the value required for normal tick
\r
586 portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
\r
588 /* Re-enable interrupts - see comments above the cpsid instruction()
\r
590 __asm volatile( "cpsie i" ::: "memory" );
\r
594 /* Set the new reload value. */
\r
595 portNVIC_SYSTICK_LOAD_REG = ulReloadValue;
\r
597 /* Clear the SysTick count flag and set the count value back to
\r
599 portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
\r
601 /* Restart SysTick. */
\r
602 portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
\r
604 /* Sleep until something happens. configPRE_SLEEP_PROCESSING() can
\r
605 set its parameter to 0 to indicate that its implementation contains
\r
606 its own wait for interrupt or wait for event instruction, and so wfi
\r
607 should not be executed again. However, the original expected idle
\r
608 time variable must remain unmodified, so a copy is taken. */
\r
609 xModifiableIdleTime = xExpectedIdleTime;
\r
610 configPRE_SLEEP_PROCESSING( xModifiableIdleTime );
\r
611 if( xModifiableIdleTime > 0 )
\r
613 __asm volatile( "dsb" ::: "memory" );
\r
614 __asm volatile( "wfi" );
\r
615 __asm volatile( "isb" );
\r
617 configPOST_SLEEP_PROCESSING( xExpectedIdleTime );
\r
619 /* Re-enable interrupts to allow the interrupt that brought the MCU
\r
620 out of sleep mode to execute immediately. see comments above
\r
621 __disable_interrupt() call above. */
\r
622 __asm volatile( "cpsie i" ::: "memory" );
\r
623 __asm volatile( "dsb" );
\r
624 __asm volatile( "isb" );
\r
626 /* Disable interrupts again because the clock is about to be stopped
\r
627 and interrupts that execute while the clock is stopped will increase
\r
628 any slippage between the time maintained by the RTOS and calendar
\r
630 __asm volatile( "cpsid i" ::: "memory" );
\r
631 __asm volatile( "dsb" );
\r
632 __asm volatile( "isb" );
\r
634 /* Disable the SysTick clock without reading the
\r
635 portNVIC_SYSTICK_CTRL_REG register to ensure the
\r
636 portNVIC_SYSTICK_COUNT_FLAG_BIT is not cleared if it is set. Again,
\r
637 the time the SysTick is stopped for is accounted for as best it can
\r
638 be, but using the tickless mode will inevitably result in some tiny
\r
639 drift of the time maintained by the kernel with respect to calendar
\r
641 portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT );
\r
643 /* Determine if the SysTick clock has already counted to zero and
\r
644 been set back to the current reload value (the reload back being
\r
645 correct for the entire expected idle time) or if the SysTick is yet
\r
646 to count to zero (in which case an interrupt other than the SysTick
\r
647 must have brought the system out of sleep mode). */
\r
648 if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )
\r
650 uint32_t ulCalculatedLoadValue;
\r
652 /* The tick interrupt is already pending, and the SysTick count
\r
653 reloaded with ulReloadValue. Reset the
\r
654 portNVIC_SYSTICK_LOAD_REG with whatever remains of this tick
\r
656 ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG );
\r
658 /* Don't allow a tiny value, or values that have somehow
\r
659 underflowed because the post sleep hook did something
\r
660 that took too long. */
\r
661 if( ( ulCalculatedLoadValue < ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) )
\r
663 ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL );
\r
666 portNVIC_SYSTICK_LOAD_REG = ulCalculatedLoadValue;
\r
668 /* As the pending tick will be processed as soon as this
\r
669 function exits, the tick value maintained by the tick is stepped
\r
670 forward by one less than the time spent waiting. */
\r
671 ulCompleteTickPeriods = xExpectedIdleTime - 1UL;
\r
675 /* Something other than the tick interrupt ended the sleep.
\r
676 Work out how long the sleep lasted rounded to complete tick
\r
677 periods (not the ulReload value which accounted for part
\r
679 ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - portNVIC_SYSTICK_CURRENT_VALUE_REG;
\r
681 /* How many complete tick periods passed while the processor
\r
683 ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick;
\r
685 /* The reload value is set to whatever fraction of a single tick
\r
687 portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1UL ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements;
\r
690 /* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG
\r
691 again, then set portNVIC_SYSTICK_LOAD_REG back to its standard
\r
693 portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
\r
694 portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
\r
695 vTaskStepTick( ulCompleteTickPeriods );
\r
696 portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
\r
698 /* Exit with interrpts enabled. */
\r
699 __asm volatile( "cpsie i" ::: "memory" );
\r
703 #endif /* #if configUSE_TICKLESS_IDLE */
\r
704 /*-----------------------------------------------------------*/
\r
707 * Setup the systick timer to generate the tick interrupts at the required
\r
710 __attribute__(( weak )) void vPortSetupTimerInterrupt( void )
\r
712 /* Calculate the constants required to configure the tick interrupt. */
\r
713 #if( configUSE_TICKLESS_IDLE == 1 )
\r
715 ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ );
\r
716 xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick;
\r
717 ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ );
\r
719 #endif /* configUSE_TICKLESS_IDLE */
\r
721 /* Stop and clear the SysTick. */
\r
722 portNVIC_SYSTICK_CTRL_REG = 0UL;
\r
723 portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
\r
725 /* Configure SysTick to interrupt at the requested rate. */
\r
726 portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
\r
727 portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT );
\r
729 /*-----------------------------------------------------------*/
\r
731 /* This is a naked function. */
\r
732 static void vPortEnableVFP( void )
\r
736 " ldr.w r0, =0xE000ED88 \n" /* The FPU enable bits are in the CPACR. */
\r
739 " orr r1, r1, #( 0xf << 20 ) \n" /* Enable CP10 and CP11 coprocessors, then save back. */
\r
744 /*-----------------------------------------------------------*/
\r
746 #if( configASSERT_DEFINED == 1 )
\r
748 void vPortValidateInterruptPriority( void )
\r
750 uint32_t ulCurrentInterrupt;
\r
751 uint8_t ucCurrentPriority;
\r
753 /* Obtain the number of the currently executing interrupt. */
\r
754 __asm volatile( "mrs %0, ipsr" : "=r"( ulCurrentInterrupt ) :: "memory" );
\r
756 /* Is the interrupt number a user defined interrupt? */
\r
757 if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER )
\r
759 /* Look up the interrupt's priority. */
\r
760 ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ];
\r
762 /* The following assertion will fail if a service routine (ISR) for
\r
763 an interrupt that has been assigned a priority above
\r
764 configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API
\r
765 function. ISR safe FreeRTOS API functions must *only* be called
\r
766 from interrupts that have been assigned a priority at or below
\r
767 configMAX_SYSCALL_INTERRUPT_PRIORITY.
\r
769 Numerically low interrupt priority numbers represent logically high
\r
770 interrupt priorities, therefore the priority of the interrupt must
\r
771 be set to a value equal to or numerically *higher* than
\r
772 configMAX_SYSCALL_INTERRUPT_PRIORITY.
\r
774 Interrupts that use the FreeRTOS API must not be left at their
\r
775 default priority of zero as that is the highest possible priority,
\r
776 which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY,
\r
777 and therefore also guaranteed to be invalid.
\r
779 FreeRTOS maintains separate thread and ISR API functions to ensure
\r
780 interrupt entry is as fast and simple as possible.
\r
782 The following links provide detailed information:
\r
783 http://www.freertos.org/RTOS-Cortex-M3-M4.html
\r
784 http://www.freertos.org/FAQHelp.html */
\r
785 configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );
\r
788 /* Priority grouping: The interrupt controller (NVIC) allows the bits
\r
789 that define each interrupt's priority to be split between bits that
\r
790 define the interrupt's pre-emption priority bits and bits that define
\r
791 the interrupt's sub-priority. For simplicity all bits must be defined
\r
792 to be pre-emption priority bits. The following assertion will fail if
\r
793 this is not the case (if some bits represent a sub-priority).
\r
795 If the application only uses CMSIS libraries for interrupt
\r
796 configuration then the correct setting can be achieved on all Cortex-M
\r
797 devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the
\r
798 scheduler. Note however that some vendor specific peripheral libraries
\r
799 assume a non-zero priority group setting, in which cases using a value
\r
800 of zero will result in unpredictable behaviour. */
\r
801 configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );
\r
804 #endif /* configASSERT_DEFINED */
\r
projects / freertos / blob