2 FreeRTOS V9.0.0 - Copyright (C) 2016 Real Time Engineers Ltd.
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5 VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
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7 This file is part of the FreeRTOS distribution.
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9 FreeRTOS is free software; you can redistribute it and/or modify it under
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10 the terms of the GNU General Public License (version 2) as published by the
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11 Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception.
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13 ***************************************************************************
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14 >>! NOTE: The modification to the GPL is included to allow you to !<<
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15 >>! distribute a combined work that includes FreeRTOS without being !<<
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16 >>! obliged to provide the source code for proprietary components !<<
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17 >>! outside of the FreeRTOS kernel. !<<
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18 ***************************************************************************
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20 FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
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21 WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
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22 FOR A PARTICULAR PURPOSE. Full license text is available on the following
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23 link: http://www.freertos.org/a00114.html
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25 ***************************************************************************
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27 * FreeRTOS provides completely free yet professionally developed, *
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28 * robust, strictly quality controlled, supported, and cross *
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29 * platform software that is more than just the market leader, it *
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30 * is the industry's de facto standard. *
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32 * Help yourself get started quickly while simultaneously helping *
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33 * to support the FreeRTOS project by purchasing a FreeRTOS *
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34 * tutorial book, reference manual, or both: *
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35 * http://www.FreeRTOS.org/Documentation *
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37 ***************************************************************************
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39 http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading
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40 the FAQ page "My application does not run, what could be wrong?". Have you
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41 defined configASSERT()?
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43 http://www.FreeRTOS.org/support - In return for receiving this top quality
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44 embedded software for free we request you assist our global community by
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45 participating in the support forum.
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47 http://www.FreeRTOS.org/training - Investing in training allows your team to
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48 be as productive as possible as early as possible. Now you can receive
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49 FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers
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50 Ltd, and the world's leading authority on the world's leading RTOS.
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52 http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
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53 including FreeRTOS+Trace - an indispensable productivity tool, a DOS
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54 compatible FAT file system, and our tiny thread aware UDP/IP stack.
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56 http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.
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57 Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.
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59 http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High
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60 Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS
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61 licenses offer ticketed support, indemnification and commercial middleware.
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63 http://www.SafeRTOS.com - High Integrity Systems also provide a safety
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64 engineered and independently SIL3 certified version for use in safety and
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65 mission critical applications that require provable dependability.
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70 /*-----------------------------------------------------------
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71 * Implementation of functions defined in portable.h for the ARM CM4F port.
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72 *----------------------------------------------------------*/
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74 /* Scheduler includes. */
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75 #include "FreeRTOS.h"
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79 #error This port can only be used when the project options are configured to enable hardware floating point support.
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82 #ifndef configSYSTICK_CLOCK_HZ
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83 #define configSYSTICK_CLOCK_HZ configCPU_CLOCK_HZ
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84 /* Ensure the SysTick is clocked at the same frequency as the core. */
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85 #define portNVIC_SYSTICK_CLK_BIT ( 1UL << 2UL )
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87 /* The way the SysTick is clocked is not modified in case it is not the same
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89 #define portNVIC_SYSTICK_CLK_BIT ( 0 )
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92 /* Constants required to manipulate the core. Registers first... */
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93 #define portNVIC_SYSTICK_CTRL_REG ( * ( ( volatile uint32_t * ) 0xe000e010 ) )
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94 #define portNVIC_SYSTICK_LOAD_REG ( * ( ( volatile uint32_t * ) 0xe000e014 ) )
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95 #define portNVIC_SYSTICK_CURRENT_VALUE_REG ( * ( ( volatile uint32_t * ) 0xe000e018 ) )
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96 #define portNVIC_SYSPRI2_REG ( * ( ( volatile uint32_t * ) 0xe000ed20 ) )
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97 /* ...then bits in the registers. */
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98 #define portNVIC_SYSTICK_INT_BIT ( 1UL << 1UL )
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99 #define portNVIC_SYSTICK_ENABLE_BIT ( 1UL << 0UL )
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100 #define portNVIC_SYSTICK_COUNT_FLAG_BIT ( 1UL << 16UL )
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101 #define portNVIC_PENDSVCLEAR_BIT ( 1UL << 27UL )
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102 #define portNVIC_PEND_SYSTICK_CLEAR_BIT ( 1UL << 25UL )
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104 /* Constants used to detect a Cortex-M7 r0p1 core, which should use the ARM_CM7
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106 #define portCPUID ( * ( ( volatile uint32_t * ) 0xE000ed00 ) )
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107 #define portCORTEX_M7_r0p1_ID ( 0x410FC271UL )
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108 #define portCORTEX_M7_r0p0_ID ( 0x410FC270UL )
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110 #define portNVIC_PENDSV_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL )
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111 #define portNVIC_SYSTICK_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL )
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113 /* Constants required to check the validity of an interrupt priority. */
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114 #define portFIRST_USER_INTERRUPT_NUMBER ( 16 )
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115 #define portNVIC_IP_REGISTERS_OFFSET_16 ( 0xE000E3F0 )
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116 #define portAIRCR_REG ( * ( ( volatile uint32_t * ) 0xE000ED0C ) )
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117 #define portMAX_8_BIT_VALUE ( ( uint8_t ) 0xff )
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118 #define portTOP_BIT_OF_BYTE ( ( uint8_t ) 0x80 )
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119 #define portMAX_PRIGROUP_BITS ( ( uint8_t ) 7 )
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120 #define portPRIORITY_GROUP_MASK ( 0x07UL << 8UL )
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121 #define portPRIGROUP_SHIFT ( 8UL )
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123 /* Masks off all bits but the VECTACTIVE bits in the ICSR register. */
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124 #define portVECTACTIVE_MASK ( 0xFFUL )
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126 /* Constants required to manipulate the VFP. */
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127 #define portFPCCR ( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating point context control register. */
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128 #define portASPEN_AND_LSPEN_BITS ( 0x3UL << 30UL )
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130 /* Constants required to set up the initial stack. */
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131 #define portINITIAL_XPSR ( 0x01000000 )
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132 #define portINITIAL_EXEC_RETURN ( 0xfffffffd )
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134 /* The systick is a 24-bit counter. */
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135 #define portMAX_24_BIT_NUMBER ( 0xffffffUL )
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137 /* For strict compliance with the Cortex-M spec the task start address should
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138 have bit-0 clear, as it is loaded into the PC on exit from an ISR. */
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139 #define portSTART_ADDRESS_MASK ( ( StackType_t ) 0xfffffffeUL )
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141 /* A fiddle factor to estimate the number of SysTick counts that would have
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142 occurred while the SysTick counter is stopped during tickless idle
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144 #define portMISSED_COUNTS_FACTOR ( 45UL )
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146 /* Let the user override the pre-loading of the initial LR with the address of
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147 prvTaskExitError() in case it messes up unwinding of the stack in the
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149 #ifdef configTASK_RETURN_ADDRESS
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150 #define portTASK_RETURN_ADDRESS configTASK_RETURN_ADDRESS
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152 #define portTASK_RETURN_ADDRESS prvTaskExitError
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155 /* Each task maintains its own interrupt status in the critical nesting
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157 static UBaseType_t uxCriticalNesting = 0xaaaaaaaa;
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160 * Setup the timer to generate the tick interrupts. The implementation in this
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161 * file is weak to allow application writers to change the timer used to
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162 * generate the tick interrupt.
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164 void vPortSetupTimerInterrupt( void );
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167 * Exception handlers.
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169 void xPortPendSVHandler( void ) __attribute__ (( naked ));
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170 void xPortSysTickHandler( void );
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171 void vPortSVCHandler( void ) __attribute__ (( naked ));
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174 * Start first task is a separate function so it can be tested in isolation.
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176 static void prvPortStartFirstTask( void ) __attribute__ (( naked ));
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179 * Function to enable the VFP.
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181 static void vPortEnableVFP( void ) __attribute__ (( naked ));
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184 * Used to catch tasks that attempt to return from their implementing function.
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186 static void prvTaskExitError( void );
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188 /*-----------------------------------------------------------*/
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191 * The number of SysTick increments that make up one tick period.
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193 #if configUSE_TICKLESS_IDLE == 1
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194 static uint32_t ulTimerCountsForOneTick = 0;
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195 #endif /* configUSE_TICKLESS_IDLE */
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198 * The maximum number of tick periods that can be suppressed is limited by the
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199 * 24 bit resolution of the SysTick timer.
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201 #if configUSE_TICKLESS_IDLE == 1
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202 static uint32_t xMaximumPossibleSuppressedTicks = 0;
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203 #endif /* configUSE_TICKLESS_IDLE */
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206 * Compensate for the CPU cycles that pass while the SysTick is stopped (low
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207 * power functionality only.
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209 #if configUSE_TICKLESS_IDLE == 1
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210 static uint32_t ulStoppedTimerCompensation = 0;
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211 #endif /* configUSE_TICKLESS_IDLE */
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214 * Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure
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215 * FreeRTOS API functions are not called from interrupts that have been assigned
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216 * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY.
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218 #if ( configASSERT_DEFINED == 1 )
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219 static uint8_t ucMaxSysCallPriority = 0;
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220 static uint32_t ulMaxPRIGROUPValue = 0;
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221 static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const volatile uint8_t * const ) portNVIC_IP_REGISTERS_OFFSET_16;
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222 #endif /* configASSERT_DEFINED */
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224 /*-----------------------------------------------------------*/
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227 * See header file for description.
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229 StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
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231 /* Simulate the stack frame as it would be created by a context switch
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234 /* Offset added to account for the way the MCU uses the stack on entry/exit
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235 of interrupts, and to ensure alignment. */
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238 *pxTopOfStack = portINITIAL_XPSR; /* xPSR */
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240 *pxTopOfStack = ( ( StackType_t ) pxCode ) & portSTART_ADDRESS_MASK; /* PC */
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242 *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */
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244 /* Save code space by skipping register initialisation. */
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245 pxTopOfStack -= 5; /* R12, R3, R2 and R1. */
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246 *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
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248 /* A save method is being used that requires each task to maintain its
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249 own exec return value. */
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251 *pxTopOfStack = portINITIAL_EXEC_RETURN;
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253 pxTopOfStack -= 8; /* R11, R10, R9, R8, R7, R6, R5 and R4. */
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255 return pxTopOfStack;
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257 /*-----------------------------------------------------------*/
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259 static void prvTaskExitError( void )
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261 /* A function that implements a task must not exit or attempt to return to
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262 its caller as there is nothing to return to. If a task wants to exit it
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263 should instead call vTaskDelete( NULL ).
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265 Artificially force an assert() to be triggered if configASSERT() is
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266 defined, then stop here so application writers can catch the error. */
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267 configASSERT( uxCriticalNesting == ~0UL );
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268 portDISABLE_INTERRUPTS();
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271 /*-----------------------------------------------------------*/
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273 void vPortSVCHandler( void )
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276 " ldr r3, pxCurrentTCBConst2 \n" /* Restore the context. */
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277 " ldr r1, [r3] \n" /* Use pxCurrentTCBConst to get the pxCurrentTCB address. */
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278 " ldr r0, [r1] \n" /* The first item in pxCurrentTCB is the task top of stack. */
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279 " ldmia r0!, {r4-r11, r14} \n" /* Pop the registers that are not automatically saved on exception entry and the critical nesting count. */
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280 " msr psp, r0 \n" /* Restore the task stack pointer. */
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283 " msr basepri, r0 \n"
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287 "pxCurrentTCBConst2: .word pxCurrentTCB \n"
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290 /*-----------------------------------------------------------*/
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292 static void prvPortStartFirstTask( void )
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295 " ldr r0, =0xE000ED08 \n" /* Use the NVIC offset register to locate the stack. */
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298 " msr msp, r0 \n" /* Set the msp back to the start of the stack. */
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299 " cpsie i \n" /* Globally enable interrupts. */
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303 " svc 0 \n" /* System call to start first task. */
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307 /*-----------------------------------------------------------*/
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310 * See header file for description.
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312 BaseType_t xPortStartScheduler( void )
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314 /* configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0.
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315 See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
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316 configASSERT( configMAX_SYSCALL_INTERRUPT_PRIORITY );
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318 /* This port can be used on all revisions of the Cortex-M7 core other than
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319 the r0p1 parts. r0p1 parts should use the port from the
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320 /source/portable/GCC/ARM_CM7/r0p1 directory. */
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321 configASSERT( portCPUID != portCORTEX_M7_r0p1_ID );
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322 configASSERT( portCPUID != portCORTEX_M7_r0p0_ID );
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324 #if( configASSERT_DEFINED == 1 )
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326 volatile uint32_t ulOriginalPriority;
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327 volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER );
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328 volatile uint8_t ucMaxPriorityValue;
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330 /* Determine the maximum priority from which ISR safe FreeRTOS API
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331 functions can be called. ISR safe functions are those that end in
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332 "FromISR". FreeRTOS maintains separate thread and ISR API functions to
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333 ensure interrupt entry is as fast and simple as possible.
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335 Save the interrupt priority value that is about to be clobbered. */
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336 ulOriginalPriority = *pucFirstUserPriorityRegister;
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338 /* Determine the number of priority bits available. First write to all
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340 *pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;
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342 /* Read the value back to see how many bits stuck. */
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343 ucMaxPriorityValue = *pucFirstUserPriorityRegister;
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345 /* Use the same mask on the maximum system call priority. */
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346 ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;
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348 /* Calculate the maximum acceptable priority group value for the number
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349 of bits read back. */
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350 ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;
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351 while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
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353 ulMaxPRIGROUPValue--;
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354 ucMaxPriorityValue <<= ( uint8_t ) 0x01;
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357 /* Shift the priority group value back to its position within the AIRCR
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359 ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;
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360 ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;
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362 /* Restore the clobbered interrupt priority register to its original
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364 *pucFirstUserPriorityRegister = ulOriginalPriority;
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366 #endif /* conifgASSERT_DEFINED */
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368 /* Make PendSV and SysTick the lowest priority interrupts. */
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369 portNVIC_SYSPRI2_REG |= portNVIC_PENDSV_PRI;
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370 portNVIC_SYSPRI2_REG |= portNVIC_SYSTICK_PRI;
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372 /* Start the timer that generates the tick ISR. Interrupts are disabled
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374 vPortSetupTimerInterrupt();
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376 /* Initialise the critical nesting count ready for the first task. */
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377 uxCriticalNesting = 0;
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379 /* Ensure the VFP is enabled - it should be anyway. */
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382 /* Lazy save always. */
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383 *( portFPCCR ) |= portASPEN_AND_LSPEN_BITS;
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385 /* Start the first task. */
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386 prvPortStartFirstTask();
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388 /* Should never get here as the tasks will now be executing! Call the task
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389 exit error function to prevent compiler warnings about a static function
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390 not being called in the case that the application writer overrides this
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391 functionality by defining configTASK_RETURN_ADDRESS. */
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392 prvTaskExitError();
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394 /* Should not get here! */
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397 /*-----------------------------------------------------------*/
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399 void vPortEndScheduler( void )
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401 /* Not implemented in ports where there is nothing to return to.
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402 Artificially force an assert. */
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403 configASSERT( uxCriticalNesting == 1000UL );
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405 /*-----------------------------------------------------------*/
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407 void vPortEnterCritical( void )
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409 portDISABLE_INTERRUPTS();
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410 uxCriticalNesting++;
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412 /* This is not the interrupt safe version of the enter critical function so
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413 assert() if it is being called from an interrupt context. Only API
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414 functions that end in "FromISR" can be used in an interrupt. Only assert if
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415 the critical nesting count is 1 to protect against recursive calls if the
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416 assert function also uses a critical section. */
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417 if( uxCriticalNesting == 1 )
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419 configASSERT( ( portNVIC_INT_CTRL_REG & portVECTACTIVE_MASK ) == 0 );
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422 /*-----------------------------------------------------------*/
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424 void vPortExitCritical( void )
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426 configASSERT( uxCriticalNesting );
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427 uxCriticalNesting--;
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428 if( uxCriticalNesting == 0 )
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430 portENABLE_INTERRUPTS();
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433 /*-----------------------------------------------------------*/
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435 void xPortPendSVHandler( void )
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437 /* This is a naked function. */
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444 " ldr r3, pxCurrentTCBConst \n" /* Get the location of the current TCB. */
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447 " tst r14, #0x10 \n" /* Is the task using the FPU context? If so, push high vfp registers. */
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449 " vstmdbeq r0!, {s16-s31} \n"
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451 " stmdb r0!, {r4-r11, r14} \n" /* Save the core registers. */
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452 " str r0, [r2] \n" /* Save the new top of stack into the first member of the TCB. */
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454 " stmdb sp!, {r3} \n"
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456 " msr basepri, r0 \n"
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459 " bl vTaskSwitchContext \n"
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461 " msr basepri, r0 \n"
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462 " ldmia sp!, {r3} \n"
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464 " ldr r1, [r3] \n" /* The first item in pxCurrentTCB is the task top of stack. */
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467 " ldmia r0!, {r4-r11, r14} \n" /* Pop the core registers. */
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469 " tst r14, #0x10 \n" /* Is the task using the FPU context? If so, pop the high vfp registers too. */
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471 " vldmiaeq r0!, {s16-s31} \n"
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476 #ifdef WORKAROUND_PMU_CM001 /* XMC4000 specific errata workaround. */
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477 #if WORKAROUND_PMU_CM001 == 1
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486 "pxCurrentTCBConst: .word pxCurrentTCB \n"
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487 ::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY)
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490 /*-----------------------------------------------------------*/
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492 void xPortSysTickHandler( void )
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494 /* The SysTick runs at the lowest interrupt priority, so when this interrupt
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495 executes all interrupts must be unmasked. There is therefore no need to
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496 save and then restore the interrupt mask value as its value is already
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498 portDISABLE_INTERRUPTS();
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500 /* Increment the RTOS tick. */
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501 if( xTaskIncrementTick() != pdFALSE )
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503 /* A context switch is required. Context switching is performed in
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504 the PendSV interrupt. Pend the PendSV interrupt. */
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505 portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
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508 portENABLE_INTERRUPTS();
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510 /*-----------------------------------------------------------*/
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512 #if configUSE_TICKLESS_IDLE == 1
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514 __attribute__((weak)) void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )
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516 uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements, ulSysTickCTRL;
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517 TickType_t xModifiableIdleTime;
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519 /* Make sure the SysTick reload value does not overflow the counter. */
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520 if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks )
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522 xExpectedIdleTime = xMaximumPossibleSuppressedTicks;
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525 /* Stop the SysTick momentarily. The time the SysTick is stopped for
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526 is accounted for as best it can be, but using the tickless mode will
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527 inevitably result in some tiny drift of the time maintained by the
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528 kernel with respect to calendar time. */
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529 portNVIC_SYSTICK_CTRL_REG &= ~portNVIC_SYSTICK_ENABLE_BIT;
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531 /* Calculate the reload value required to wait xExpectedIdleTime
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532 tick periods. -1 is used because this code will execute part way
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533 through one of the tick periods. */
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534 ulReloadValue = portNVIC_SYSTICK_CURRENT_VALUE_REG + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) );
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535 if( ulReloadValue > ulStoppedTimerCompensation )
\r
537 ulReloadValue -= ulStoppedTimerCompensation;
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540 /* Enter a critical section but don't use the taskENTER_CRITICAL()
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541 method as that will mask interrupts that should exit sleep mode. */
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542 __asm volatile( "cpsid i" );
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543 __asm volatile( "dsb" );
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544 __asm volatile( "isb" );
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546 /* If a context switch is pending or a task is waiting for the scheduler
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547 to be unsuspended then abandon the low power entry. */
\r
548 if( eTaskConfirmSleepModeStatus() == eAbortSleep )
\r
550 /* Restart from whatever is left in the count register to complete
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551 this tick period. */
\r
552 portNVIC_SYSTICK_LOAD_REG = portNVIC_SYSTICK_CURRENT_VALUE_REG;
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554 /* Restart SysTick. */
\r
555 portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
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557 /* Reset the reload register to the value required for normal tick
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559 portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
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561 /* Re-enable interrupts - see comments above the cpsid instruction()
\r
563 __asm volatile( "cpsie i" );
\r
567 /* Set the new reload value. */
\r
568 portNVIC_SYSTICK_LOAD_REG = ulReloadValue;
\r
570 /* Clear the SysTick count flag and set the count value back to
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572 portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
\r
574 /* Restart SysTick. */
\r
575 portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
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577 /* Sleep until something happens. configPRE_SLEEP_PROCESSING() can
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578 set its parameter to 0 to indicate that its implementation contains
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579 its own wait for interrupt or wait for event instruction, and so wfi
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580 should not be executed again. However, the original expected idle
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581 time variable must remain unmodified, so a copy is taken. */
\r
582 xModifiableIdleTime = xExpectedIdleTime;
\r
583 configPRE_SLEEP_PROCESSING( xModifiableIdleTime );
\r
584 if( xModifiableIdleTime > 0 )
\r
586 __asm volatile( "dsb" );
\r
587 __asm volatile( "wfi" );
\r
588 __asm volatile( "isb" );
\r
590 configPOST_SLEEP_PROCESSING( xExpectedIdleTime );
\r
592 /* Stop SysTick. Again, the time the SysTick is stopped for is
\r
593 accounted for as best it can be, but using the tickless mode will
\r
594 inevitably result in some tiny drift of the time maintained by the
\r
595 kernel with respect to calendar time. */
\r
596 ulSysTickCTRL = portNVIC_SYSTICK_CTRL_REG;
\r
597 portNVIC_SYSTICK_CTRL_REG = ( ulSysTickCTRL & ~portNVIC_SYSTICK_ENABLE_BIT );
\r
599 /* Re-enable interrupts - see comments above the cpsid instruction()
\r
601 __asm volatile( "cpsie i" );
\r
603 if( ( ulSysTickCTRL & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )
\r
605 uint32_t ulCalculatedLoadValue;
\r
607 /* The tick interrupt has already executed, and the SysTick
\r
608 count reloaded with ulReloadValue. Reset the
\r
609 portNVIC_SYSTICK_LOAD_REG with whatever remains of this tick
\r
611 ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG );
\r
613 /* Don't allow a tiny value, or values that have somehow
\r
614 underflowed because the post sleep hook did something
\r
615 that took too long. */
\r
616 if( ( ulCalculatedLoadValue < ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) )
\r
618 ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL );
\r
621 portNVIC_SYSTICK_LOAD_REG = ulCalculatedLoadValue;
\r
623 /* The tick interrupt handler will already have pended the tick
\r
624 processing in the kernel. As the pending tick will be
\r
625 processed as soon as this function exits, the tick value
\r
626 maintained by the tick is stepped forward by one less than the
\r
627 time spent waiting. */
\r
628 ulCompleteTickPeriods = xExpectedIdleTime - 1UL;
\r
632 /* Something other than the tick interrupt ended the sleep.
\r
633 Work out how long the sleep lasted rounded to complete tick
\r
634 periods (not the ulReload value which accounted for part
\r
636 ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - portNVIC_SYSTICK_CURRENT_VALUE_REG;
\r
638 /* How many complete tick periods passed while the processor
\r
640 ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick;
\r
642 /* The reload value is set to whatever fraction of a single tick
\r
644 portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1UL ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements;
\r
647 /* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG
\r
648 again, then set portNVIC_SYSTICK_LOAD_REG back to its standard
\r
649 value. The critical section is used to ensure the tick interrupt
\r
650 can only execute once in the case that the reload register is near
\r
652 portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
\r
653 portENTER_CRITICAL();
\r
655 portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
\r
656 vTaskStepTick( ulCompleteTickPeriods );
\r
657 portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
\r
659 portEXIT_CRITICAL();
\r
663 #endif /* #if configUSE_TICKLESS_IDLE */
\r
664 /*-----------------------------------------------------------*/
\r
667 * Setup the systick timer to generate the tick interrupts at the required
\r
670 __attribute__(( weak )) void vPortSetupTimerInterrupt( void )
\r
672 /* Calculate the constants required to configure the tick interrupt. */
\r
673 #if configUSE_TICKLESS_IDLE == 1
\r
675 ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ );
\r
676 xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick;
\r
677 ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ );
\r
679 #endif /* configUSE_TICKLESS_IDLE */
\r
681 /* Stop and clear the SysTick. */
\r
682 portNVIC_SYSTICK_CTRL_REG = 0UL;
\r
683 portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
\r
685 /* Configure SysTick to interrupt at the requested rate. */
\r
686 portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
\r
687 portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT );
\r
689 /*-----------------------------------------------------------*/
\r
691 /* This is a naked function. */
\r
692 static void vPortEnableVFP( void )
\r
696 " ldr.w r0, =0xE000ED88 \n" /* The FPU enable bits are in the CPACR. */
\r
699 " orr r1, r1, #( 0xf << 20 ) \n" /* Enable CP10 and CP11 coprocessors, then save back. */
\r
704 /*-----------------------------------------------------------*/
\r
706 #if( configASSERT_DEFINED == 1 )
\r
708 void vPortValidateInterruptPriority( void )
\r
710 uint32_t ulCurrentInterrupt;
\r
711 uint8_t ucCurrentPriority;
\r
713 /* Obtain the number of the currently executing interrupt. */
\r
714 __asm volatile( "mrs %0, ipsr" : "=r"( ulCurrentInterrupt ) );
\r
716 /* Is the interrupt number a user defined interrupt? */
\r
717 if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER )
\r
719 /* Look up the interrupt's priority. */
\r
720 ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ];
\r
722 /* The following assertion will fail if a service routine (ISR) for
\r
723 an interrupt that has been assigned a priority above
\r
724 configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API
\r
725 function. ISR safe FreeRTOS API functions must *only* be called
\r
726 from interrupts that have been assigned a priority at or below
\r
727 configMAX_SYSCALL_INTERRUPT_PRIORITY.
\r
729 Numerically low interrupt priority numbers represent logically high
\r
730 interrupt priorities, therefore the priority of the interrupt must
\r
731 be set to a value equal to or numerically *higher* than
\r
732 configMAX_SYSCALL_INTERRUPT_PRIORITY.
\r
734 Interrupts that use the FreeRTOS API must not be left at their
\r
735 default priority of zero as that is the highest possible priority,
\r
736 which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY,
\r
737 and therefore also guaranteed to be invalid.
\r
739 FreeRTOS maintains separate thread and ISR API functions to ensure
\r
740 interrupt entry is as fast and simple as possible.
\r
742 The following links provide detailed information:
\r
743 http://www.freertos.org/RTOS-Cortex-M3-M4.html
\r
744 http://www.freertos.org/FAQHelp.html */
\r
745 configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );
\r
748 /* Priority grouping: The interrupt controller (NVIC) allows the bits
\r
749 that define each interrupt's priority to be split between bits that
\r
750 define the interrupt's pre-emption priority bits and bits that define
\r
751 the interrupt's sub-priority. For simplicity all bits must be defined
\r
752 to be pre-emption priority bits. The following assertion will fail if
\r
753 this is not the case (if some bits represent a sub-priority).
\r
755 If the application only uses CMSIS libraries for interrupt
\r
756 configuration then the correct setting can be achieved on all Cortex-M
\r
757 devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the
\r
758 scheduler. Note however that some vendor specific peripheral libraries
\r
759 assume a non-zero priority group setting, in which cases using a value
\r
760 of zero will result in unpredicable behaviour. */
\r
761 configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );
\r
764 #endif /* configASSERT_DEFINED */
\r
projects / freertos / blob