2 FreeRTOS V9.0.0 - Copyright (C) 2016 Real Time Engineers Ltd.
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5 VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
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7 This file is part of the FreeRTOS distribution.
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9 FreeRTOS is free software; you can redistribute it and/or modify it under
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10 the terms of the GNU General Public License (version 2) as published by the
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11 Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception.
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13 ***************************************************************************
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14 >>! NOTE: The modification to the GPL is included to allow you to !<<
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15 >>! distribute a combined work that includes FreeRTOS without being !<<
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16 >>! obliged to provide the source code for proprietary components !<<
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17 >>! outside of the FreeRTOS kernel. !<<
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18 ***************************************************************************
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20 FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
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21 WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
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22 FOR A PARTICULAR PURPOSE. Full license text is available on the following
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23 link: http://www.freertos.org/a00114.html
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25 ***************************************************************************
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27 * FreeRTOS provides completely free yet professionally developed, *
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28 * robust, strictly quality controlled, supported, and cross *
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29 * platform software that is more than just the market leader, it *
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30 * is the industry's de facto standard. *
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32 * Help yourself get started quickly while simultaneously helping *
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33 * to support the FreeRTOS project by purchasing a FreeRTOS *
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34 * tutorial book, reference manual, or both: *
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35 * http://www.FreeRTOS.org/Documentation *
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37 ***************************************************************************
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39 http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading
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40 the FAQ page "My application does not run, what could be wrong?". Have you
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41 defined configASSERT()?
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43 http://www.FreeRTOS.org/support - In return for receiving this top quality
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44 embedded software for free we request you assist our global community by
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45 participating in the support forum.
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47 http://www.FreeRTOS.org/training - Investing in training allows your team to
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48 be as productive as possible as early as possible. Now you can receive
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49 FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers
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50 Ltd, and the world's leading authority on the world's leading RTOS.
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52 http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
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53 including FreeRTOS+Trace - an indispensable productivity tool, a DOS
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54 compatible FAT file system, and our tiny thread aware UDP/IP stack.
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56 http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.
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57 Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.
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59 http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High
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60 Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS
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61 licenses offer ticketed support, indemnification and commercial middleware.
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63 http://www.SafeRTOS.com - High Integrity Systems also provide a safety
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64 engineered and independently SIL3 certified version for use in safety and
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65 mission critical applications that require provable dependability.
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70 /*-----------------------------------------------------------
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71 * Implementation of functions defined in portable.h for the ARM CM3 port.
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72 *----------------------------------------------------------*/
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74 /* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
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75 all the API functions to use the MPU wrappers. That should only be done when
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76 task.h is included from an application file. */
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77 #define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
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79 /* Scheduler includes. */
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80 #include "FreeRTOS.h"
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82 #include "event_groups.h"
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83 #include "mpu_prototypes.h"
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86 #error This port can only be used when the project options are configured to enable hardware floating point support.
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89 #undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
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91 /* Constants required to access and manipulate the NVIC. */
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92 #define portNVIC_SYSTICK_CTRL_REG ( * ( ( volatile uint32_t * ) 0xe000e010 ) )
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93 #define portNVIC_SYSTICK_LOAD_REG ( * ( ( volatile uint32_t * ) 0xe000e014 ) )
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94 #define portNVIC_SYSTICK_CURRENT_VALUE_REG ( * ( ( volatile uint32_t * ) 0xe000e018 ) )
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95 #define portNVIC_SYSPRI2_REG ( * ( ( volatile uint32_t * ) 0xe000ed20 ) )
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96 #define portNVIC_SYSPRI1_REG ( * ( ( volatile uint32_t * ) 0xe000ed1c ) )
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97 #define portNVIC_SYS_CTRL_STATE_REG ( * ( ( volatile uint32_t * ) 0xe000ed24 ) )
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98 #define portNVIC_MEM_FAULT_ENABLE ( 1UL << 16UL )
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100 /* Constants required to access and manipulate the MPU. */
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101 #define portMPU_TYPE_REG ( * ( ( volatile uint32_t * ) 0xe000ed90 ) )
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102 #define portMPU_REGION_BASE_ADDRESS_REG ( * ( ( volatile uint32_t * ) 0xe000ed9C ) )
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103 #define portMPU_REGION_ATTRIBUTE_REG ( * ( ( volatile uint32_t * ) 0xe000edA0 ) )
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104 #define portMPU_CTRL_REG ( * ( ( volatile uint32_t * ) 0xe000ed94 ) )
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105 #define portEXPECTED_MPU_TYPE_VALUE ( 8UL << 8UL ) /* 8 regions, unified. */
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106 #define portMPU_ENABLE ( 0x01UL )
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107 #define portMPU_BACKGROUND_ENABLE ( 1UL << 2UL )
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108 #define portPRIVILEGED_EXECUTION_START_ADDRESS ( 0UL )
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109 #define portMPU_REGION_VALID ( 0x10UL )
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110 #define portMPU_REGION_ENABLE ( 0x01UL )
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111 #define portPERIPHERALS_START_ADDRESS 0x40000000UL
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112 #define portPERIPHERALS_END_ADDRESS 0x5FFFFFFFUL
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114 /* Constants required to access and manipulate the SysTick. */
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115 #define portNVIC_SYSTICK_CLK ( 0x00000004UL )
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116 #define portNVIC_SYSTICK_INT ( 0x00000002UL )
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117 #define portNVIC_SYSTICK_ENABLE ( 0x00000001UL )
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118 #define portNVIC_PENDSV_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL )
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119 #define portNVIC_SYSTICK_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL )
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120 #define portNVIC_SVC_PRI ( ( ( uint32_t ) configMAX_SYSCALL_INTERRUPT_PRIORITY - 1UL ) << 24UL )
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122 /* Constants required to manipulate the VFP. */
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123 #define portFPCCR ( ( volatile uint32_t * ) 0xe000ef34UL ) /* Floating point context control register. */
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124 #define portASPEN_AND_LSPEN_BITS ( 0x3UL << 30UL )
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126 /* Constants required to set up the initial stack. */
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127 #define portINITIAL_XPSR ( 0x01000000UL )
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128 #define portINITIAL_EXEC_RETURN ( 0xfffffffdUL )
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129 #define portINITIAL_CONTROL_IF_UNPRIVILEGED ( 0x03 )
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130 #define portINITIAL_CONTROL_IF_PRIVILEGED ( 0x02 )
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132 /* Constants required to check the validity of an interrupt priority. */
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133 #define portFIRST_USER_INTERRUPT_NUMBER ( 16 )
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134 #define portNVIC_IP_REGISTERS_OFFSET_16 ( 0xE000E3F0 )
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135 #define portAIRCR_REG ( * ( ( volatile uint32_t * ) 0xE000ED0C ) )
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136 #define portMAX_8_BIT_VALUE ( ( uint8_t ) 0xff )
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137 #define portTOP_BIT_OF_BYTE ( ( uint8_t ) 0x80 )
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138 #define portMAX_PRIGROUP_BITS ( ( uint8_t ) 7 )
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139 #define portPRIORITY_GROUP_MASK ( 0x07UL << 8UL )
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140 #define portPRIGROUP_SHIFT ( 8UL )
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142 /* Offsets in the stack to the parameters when inside the SVC handler. */
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143 #define portOFFSET_TO_PC ( 6 )
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145 /* For strict compliance with the Cortex-M spec the task start address should
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146 have bit-0 clear, as it is loaded into the PC on exit from an ISR. */
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147 #define portSTART_ADDRESS_MASK ( ( StackType_t ) 0xfffffffeUL )
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149 /* Each task maintains its own interrupt status in the critical nesting
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150 variable. Note this is not saved as part of the task context as context
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151 switches can only occur when uxCriticalNesting is zero. */
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152 static UBaseType_t uxCriticalNesting = 0xaaaaaaaa;
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155 * Setup the timer to generate the tick interrupts.
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157 static void prvSetupTimerInterrupt( void ) PRIVILEGED_FUNCTION;
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160 * Configure a number of standard MPU regions that are used by all tasks.
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162 static void prvSetupMPU( void ) PRIVILEGED_FUNCTION;
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165 * Return the smallest MPU region size that a given number of bytes will fit
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166 * into. The region size is returned as the value that should be programmed
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167 * into the region attribute register for that region.
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169 static uint32_t prvGetMPURegionSizeSetting( uint32_t ulActualSizeInBytes ) PRIVILEGED_FUNCTION;
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172 * Checks to see if being called from the context of an unprivileged task, and
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173 * if so raises the privilege level and returns false - otherwise does nothing
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174 * other than return true.
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176 BaseType_t xPortRaisePrivilege( void ) __attribute__(( naked ));
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179 * Standard FreeRTOS exception handlers.
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181 void xPortPendSVHandler( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
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182 void xPortSysTickHandler( void ) __attribute__ ((optimize("3"))) PRIVILEGED_FUNCTION;
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183 void vPortSVCHandler( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
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186 * Starts the scheduler by restoring the context of the first task to run.
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188 static void prvRestoreContextOfFirstTask( void ) __attribute__(( naked )) PRIVILEGED_FUNCTION;
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191 * C portion of the SVC handler. The SVC handler is split between an asm entry
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192 * and a C wrapper for simplicity of coding and maintenance.
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194 static void prvSVCHandler( uint32_t *pulRegisters ) __attribute__(( noinline )) PRIVILEGED_FUNCTION;
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197 * Function to enable the VFP.
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199 static void vPortEnableVFP( void ) __attribute__ (( naked ));
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202 * Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure
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203 * FreeRTOS API functions are not called from interrupts that have been assigned
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204 * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY.
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206 #if ( configASSERT_DEFINED == 1 )
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207 static uint8_t ucMaxSysCallPriority = 0;
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208 static uint32_t ulMaxPRIGROUPValue = 0;
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209 static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const volatile uint8_t * const ) portNVIC_IP_REGISTERS_OFFSET_16;
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210 #endif /* configASSERT_DEFINED */
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212 /*-----------------------------------------------------------*/
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215 * See header file for description.
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217 StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters, BaseType_t xRunPrivileged )
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219 /* Simulate the stack frame as it would be created by a context switch
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221 pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
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222 *pxTopOfStack = portINITIAL_XPSR; /* xPSR */
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224 *pxTopOfStack = ( ( StackType_t ) pxCode ) & portSTART_ADDRESS_MASK; /* PC */
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226 *pxTopOfStack = 0; /* LR */
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227 pxTopOfStack -= 5; /* R12, R3, R2 and R1. */
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228 *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
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230 /* A save method is being used that requires each task to maintain its
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231 own exec return value. */
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233 *pxTopOfStack = portINITIAL_EXEC_RETURN;
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235 pxTopOfStack -= 9; /* R11, R10, R9, R8, R7, R6, R5 and R4. */
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237 if( xRunPrivileged == pdTRUE )
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239 *pxTopOfStack = portINITIAL_CONTROL_IF_PRIVILEGED;
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243 *pxTopOfStack = portINITIAL_CONTROL_IF_UNPRIVILEGED;
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246 return pxTopOfStack;
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248 /*-----------------------------------------------------------*/
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250 void vPortSVCHandler( void )
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252 /* Assumes psp was in use. */
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255 #ifndef USE_PROCESS_STACK /* Code should not be required if a main() is using the process stack. */
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258 " mrseq r0, msp \n"
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259 " mrsne r0, psp \n"
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264 ::"i"(prvSVCHandler):"r0"
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267 /*-----------------------------------------------------------*/
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269 static void prvSVCHandler( uint32_t *pulParam )
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271 uint8_t ucSVCNumber;
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273 /* The stack contains: r0, r1, r2, r3, r12, r14, the return address and
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274 xPSR. The first argument (r0) is pulParam[ 0 ]. */
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275 ucSVCNumber = ( ( uint8_t * ) pulParam[ portOFFSET_TO_PC ] )[ -2 ];
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276 switch( ucSVCNumber )
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278 case portSVC_START_SCHEDULER : portNVIC_SYSPRI1_REG |= portNVIC_SVC_PRI;
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279 prvRestoreContextOfFirstTask();
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282 case portSVC_YIELD : portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
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283 /* Barriers are normally not required
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284 but do ensure the code is completely
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285 within the specified behaviour for the
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287 __asm volatile( "dsb" );
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288 __asm volatile( "isb" );
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292 case portSVC_RAISE_PRIVILEGE : __asm volatile
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294 " mrs r1, control \n" /* Obtain current control value. */
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295 " bic r1, #1 \n" /* Set privilege bit. */
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296 " msr control, r1 \n" /* Write back new control value. */
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301 default : /* Unknown SVC call. */
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305 /*-----------------------------------------------------------*/
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307 static void prvRestoreContextOfFirstTask( void )
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311 " ldr r0, =0xE000ED08 \n" /* Use the NVIC offset register to locate the stack. */
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314 " msr msp, r0 \n" /* Set the msp back to the start of the stack. */
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315 " ldr r3, pxCurrentTCBConst2 \n" /* Restore the context. */
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317 " ldr r0, [r1] \n" /* The first item in the TCB is the task top of stack. */
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318 " add r1, r1, #4 \n" /* Move onto the second item in the TCB... */
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319 " ldr r2, =0xe000ed9c \n" /* Region Base Address register. */
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320 " ldmia r1!, {r4-r11} \n" /* Read 4 sets of MPU registers. */
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321 " stmia r2!, {r4-r11} \n" /* Write 4 sets of MPU registers. */
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322 " ldmia r0!, {r3-r11, r14} \n" /* Pop the registers that are not automatically saved on exception entry. */
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323 " msr control, r3 \n"
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324 " msr psp, r0 \n" /* Restore the task stack pointer. */
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326 " msr basepri, r0 \n"
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330 "pxCurrentTCBConst2: .word pxCurrentTCB \n"
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333 /*-----------------------------------------------------------*/
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336 * See header file for description.
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338 BaseType_t xPortStartScheduler( void )
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340 /* configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0. See
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341 http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
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342 configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) );
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344 #if( configASSERT_DEFINED == 1 )
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346 volatile uint32_t ulOriginalPriority;
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347 volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER );
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348 volatile uint8_t ucMaxPriorityValue;
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350 /* Determine the maximum priority from which ISR safe FreeRTOS API
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351 functions can be called. ISR safe functions are those that end in
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352 "FromISR". FreeRTOS maintains separate thread and ISR API functions to
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353 ensure interrupt entry is as fast and simple as possible.
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355 Save the interrupt priority value that is about to be clobbered. */
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356 ulOriginalPriority = *pucFirstUserPriorityRegister;
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358 /* Determine the number of priority bits available. First write to all
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360 *pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;
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362 /* Read the value back to see how many bits stuck. */
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363 ucMaxPriorityValue = *pucFirstUserPriorityRegister;
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365 /* Use the same mask on the maximum system call priority. */
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366 ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;
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368 /* Calculate the maximum acceptable priority group value for the number
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369 of bits read back. */
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370 ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;
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371 while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
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373 ulMaxPRIGROUPValue--;
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374 ucMaxPriorityValue <<= ( uint8_t ) 0x01;
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377 #ifdef __NVIC_PRIO_BITS
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379 /* Check the CMSIS configuration that defines the number of
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380 priority bits matches the number of priority bits actually queried
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381 from the hardware. */
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382 configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == __NVIC_PRIO_BITS );
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386 #ifdef configPRIO_BITS
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388 /* Check the FreeRTOS configuration that defines the number of
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389 priority bits matches the number of priority bits actually queried
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390 from the hardware. */
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391 configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == configPRIO_BITS );
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395 /* Shift the priority group value back to its position within the AIRCR
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397 ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;
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398 ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;
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400 /* Restore the clobbered interrupt priority register to its original
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402 *pucFirstUserPriorityRegister = ulOriginalPriority;
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404 #endif /* conifgASSERT_DEFINED */
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406 /* Make PendSV and SysTick the same priority as the kernel, and the SVC
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407 handler higher priority so it can be used to exit a critical section (where
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408 lower priorities are masked). */
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409 portNVIC_SYSPRI2_REG |= portNVIC_PENDSV_PRI;
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410 portNVIC_SYSPRI2_REG |= portNVIC_SYSTICK_PRI;
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412 /* Configure the regions in the MPU that are common to all tasks. */
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415 /* Start the timer that generates the tick ISR. Interrupts are disabled
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417 prvSetupTimerInterrupt();
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419 /* Initialise the critical nesting count ready for the first task. */
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420 uxCriticalNesting = 0;
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422 /* Ensure the VFP is enabled - it should be anyway. */
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425 /* Lazy save always. */
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426 *( portFPCCR ) |= portASPEN_AND_LSPEN_BITS;
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428 /* Start the first task. This also clears the bit that indicates the FPU is
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429 in use in case the FPU was used before the scheduler was started - which
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430 would otherwise result in the unnecessary leaving of space in the SVC stack
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431 for lazy saving of FPU registers. */
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433 " ldr r0, =0xE000ED08 \n" /* Use the NVIC offset register to locate the stack. */
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436 " msr msp, r0 \n" /* Set the msp back to the start of the stack. */
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437 " mov r0, #0 \n" /* Clear the bit that indicates the FPU is in use, see comment above. */
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438 " msr control, r0 \n"
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439 " cpsie i \n" /* Globally enable interrupts. */
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443 " svc %0 \n" /* System call to start first task. */
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445 :: "i" (portSVC_START_SCHEDULER) );
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447 /* Should not get here! */
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450 /*-----------------------------------------------------------*/
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452 void vPortEndScheduler( void )
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454 /* Not implemented in ports where there is nothing to return to.
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455 Artificially force an assert. */
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456 configASSERT( uxCriticalNesting == 1000UL );
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458 /*-----------------------------------------------------------*/
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460 void vPortEnterCritical( void )
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462 BaseType_t xRunningPrivileged = xPortRaisePrivilege();
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464 portDISABLE_INTERRUPTS();
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465 uxCriticalNesting++;
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467 vPortResetPrivilege( xRunningPrivileged );
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469 /*-----------------------------------------------------------*/
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471 void vPortExitCritical( void )
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473 BaseType_t xRunningPrivileged = xPortRaisePrivilege();
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475 configASSERT( uxCriticalNesting );
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476 uxCriticalNesting--;
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477 if( uxCriticalNesting == 0 )
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479 portENABLE_INTERRUPTS();
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481 vPortResetPrivilege( xRunningPrivileged );
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483 /*-----------------------------------------------------------*/
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485 void xPortPendSVHandler( void )
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487 /* This is a naked function. */
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493 " ldr r3, pxCurrentTCBConst \n" /* Get the location of the current TCB. */
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496 " tst r14, #0x10 \n" /* Is the task using the FPU context? If so, push high vfp registers. */
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498 " vstmdbeq r0!, {s16-s31} \n"
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500 " mrs r1, control \n"
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501 " stmdb r0!, {r1, r4-r11, r14} \n" /* Save the remaining registers. */
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502 " str r0, [r2] \n" /* Save the new top of stack into the first member of the TCB. */
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504 " stmdb sp!, {r3} \n"
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506 " msr basepri, r0 \n"
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509 " bl vTaskSwitchContext \n"
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511 " msr basepri, r0 \n"
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512 " ldmia sp!, {r3} \n"
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513 " \n" /* Restore the context. */
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515 " ldr r0, [r1] \n" /* The first item in the TCB is the task top of stack. */
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516 " add r1, r1, #4 \n" /* Move onto the second item in the TCB... */
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517 " ldr r2, =0xe000ed9c \n" /* Region Base Address register. */
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518 " ldmia r1!, {r4-r11} \n" /* Read 4 sets of MPU registers. */
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519 " stmia r2!, {r4-r11} \n" /* Write 4 sets of MPU registers. */
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520 " ldmia r0!, {r3-r11, r14} \n" /* Pop the registers that are not automatically saved on exception entry. */
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521 " msr control, r3 \n"
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523 " tst r14, #0x10 \n" /* Is the task using the FPU context? If so, pop the high vfp registers too. */
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525 " vldmiaeq r0!, {s16-s31} \n"
\r
531 "pxCurrentTCBConst: .word pxCurrentTCB \n"
\r
532 ::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY)
\r
535 /*-----------------------------------------------------------*/
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537 void xPortSysTickHandler( void )
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541 ulDummy = portSET_INTERRUPT_MASK_FROM_ISR();
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543 /* Increment the RTOS tick. */
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544 if( xTaskIncrementTick() != pdFALSE )
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546 /* Pend a context switch. */
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547 portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
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550 portCLEAR_INTERRUPT_MASK_FROM_ISR( ulDummy );
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552 /*-----------------------------------------------------------*/
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555 * Setup the systick timer to generate the tick interrupts at the required
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558 static void prvSetupTimerInterrupt( void )
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560 /* Clear the SysTick. */
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561 portNVIC_SYSTICK_CTRL_REG = 0UL;
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562 portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
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564 /* Configure SysTick to interrupt at the requested rate. */
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565 portNVIC_SYSTICK_LOAD_REG = ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
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566 portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK | portNVIC_SYSTICK_INT | portNVIC_SYSTICK_ENABLE;
\r
568 /*-----------------------------------------------------------*/
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570 /* This is a naked function. */
\r
571 static void vPortEnableVFP( void )
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575 " ldr.w r0, =0xE000ED88 \n" /* The FPU enable bits are in the CPACR. */
\r
578 " orr r1, r1, #( 0xf << 20 ) \n" /* Enable CP10 and CP11 coprocessors, then save back. */
\r
583 /*-----------------------------------------------------------*/
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585 static void prvSetupMPU( void )
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587 extern uint32_t __privileged_functions_end__[];
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588 extern uint32_t __FLASH_segment_start__[];
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589 extern uint32_t __FLASH_segment_end__[];
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590 extern uint32_t __privileged_data_start__[];
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591 extern uint32_t __privileged_data_end__[];
\r
593 /* Check the expected MPU is present. */
\r
594 if( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE )
\r
596 /* First setup the entire flash for unprivileged read only access. */
\r
597 portMPU_REGION_BASE_ADDRESS_REG = ( ( uint32_t ) __FLASH_segment_start__ ) | /* Base address. */
\r
598 ( portMPU_REGION_VALID ) |
\r
599 ( portUNPRIVILEGED_FLASH_REGION );
\r
601 portMPU_REGION_ATTRIBUTE_REG = ( portMPU_REGION_READ_ONLY ) |
\r
602 ( portMPU_REGION_CACHEABLE_BUFFERABLE ) |
\r
603 ( prvGetMPURegionSizeSetting( ( uint32_t ) __FLASH_segment_end__ - ( uint32_t ) __FLASH_segment_start__ ) ) |
\r
604 ( portMPU_REGION_ENABLE );
\r
606 /* Setup the first 16K for privileged only access (even though less
\r
607 than 10K is actually being used). This is where the kernel code is
\r
609 portMPU_REGION_BASE_ADDRESS_REG = ( ( uint32_t ) __FLASH_segment_start__ ) | /* Base address. */
\r
610 ( portMPU_REGION_VALID ) |
\r
611 ( portPRIVILEGED_FLASH_REGION );
\r
613 portMPU_REGION_ATTRIBUTE_REG = ( portMPU_REGION_PRIVILEGED_READ_ONLY ) |
\r
614 ( portMPU_REGION_CACHEABLE_BUFFERABLE ) |
\r
615 ( prvGetMPURegionSizeSetting( ( uint32_t ) __privileged_functions_end__ - ( uint32_t ) __FLASH_segment_start__ ) ) |
\r
616 ( portMPU_REGION_ENABLE );
\r
618 /* Setup the privileged data RAM region. This is where the kernel data
\r
620 portMPU_REGION_BASE_ADDRESS_REG = ( ( uint32_t ) __privileged_data_start__ ) | /* Base address. */
\r
621 ( portMPU_REGION_VALID ) |
\r
622 ( portPRIVILEGED_RAM_REGION );
\r
624 portMPU_REGION_ATTRIBUTE_REG = ( portMPU_REGION_PRIVILEGED_READ_WRITE ) |
\r
625 ( portMPU_REGION_CACHEABLE_BUFFERABLE ) |
\r
626 prvGetMPURegionSizeSetting( ( uint32_t ) __privileged_data_end__ - ( uint32_t ) __privileged_data_start__ ) |
\r
627 ( portMPU_REGION_ENABLE );
\r
629 /* By default allow everything to access the general peripherals. The
\r
630 system peripherals and registers are protected. */
\r
631 portMPU_REGION_BASE_ADDRESS_REG = ( portPERIPHERALS_START_ADDRESS ) |
\r
632 ( portMPU_REGION_VALID ) |
\r
633 ( portGENERAL_PERIPHERALS_REGION );
\r
635 portMPU_REGION_ATTRIBUTE_REG = ( portMPU_REGION_READ_WRITE | portMPU_REGION_EXECUTE_NEVER ) |
\r
636 ( prvGetMPURegionSizeSetting( portPERIPHERALS_END_ADDRESS - portPERIPHERALS_START_ADDRESS ) ) |
\r
637 ( portMPU_REGION_ENABLE );
\r
639 /* Enable the memory fault exception. */
\r
640 portNVIC_SYS_CTRL_STATE_REG |= portNVIC_MEM_FAULT_ENABLE;
\r
642 /* Enable the MPU with the background region configured. */
\r
643 portMPU_CTRL_REG |= ( portMPU_ENABLE | portMPU_BACKGROUND_ENABLE );
\r
646 /*-----------------------------------------------------------*/
\r
648 static uint32_t prvGetMPURegionSizeSetting( uint32_t ulActualSizeInBytes )
\r
650 uint32_t ulRegionSize, ulReturnValue = 4;
\r
652 /* 32 is the smallest region size, 31 is the largest valid value for
\r
654 for( ulRegionSize = 32UL; ulReturnValue < 31UL; ( ulRegionSize <<= 1UL ) )
\r
656 if( ulActualSizeInBytes <= ulRegionSize )
\r
666 /* Shift the code by one before returning so it can be written directly
\r
667 into the the correct bit position of the attribute register. */
\r
668 return ( ulReturnValue << 1UL );
\r
670 /*-----------------------------------------------------------*/
\r
672 BaseType_t xPortRaisePrivilege( void )
\r
676 " mrs r0, control \n"
\r
677 " tst r0, #1 \n" /* Is the task running privileged? */
\r
679 " movne r0, #0 \n" /* CONTROL[0]!=0, return false. */
\r
680 " svcne %0 \n" /* Switch to privileged. */
\r
681 " moveq r0, #1 \n" /* CONTROL[0]==0, return true. */
\r
683 :: "i" (portSVC_RAISE_PRIVILEGE) : "r0"
\r
688 /*-----------------------------------------------------------*/
\r
690 void vPortStoreTaskMPUSettings( xMPU_SETTINGS *xMPUSettings, const struct xMEMORY_REGION * const xRegions, StackType_t *pxBottomOfStack, uint32_t ulStackDepth )
\r
692 extern uint32_t __SRAM_segment_start__[];
\r
693 extern uint32_t __SRAM_segment_end__[];
\r
694 extern uint32_t __privileged_data_start__[];
\r
695 extern uint32_t __privileged_data_end__[];
\r
699 if( xRegions == NULL )
\r
701 /* No MPU regions are specified so allow access to all RAM. */
\r
702 xMPUSettings->xRegion[ 0 ].ulRegionBaseAddress =
\r
703 ( ( uint32_t ) __SRAM_segment_start__ ) | /* Base address. */
\r
704 ( portMPU_REGION_VALID ) |
\r
705 ( portSTACK_REGION );
\r
707 xMPUSettings->xRegion[ 0 ].ulRegionAttribute =
\r
708 ( portMPU_REGION_READ_WRITE ) |
\r
709 ( portMPU_REGION_CACHEABLE_BUFFERABLE ) |
\r
710 ( prvGetMPURegionSizeSetting( ( uint32_t ) __SRAM_segment_end__ - ( uint32_t ) __SRAM_segment_start__ ) ) |
\r
711 ( portMPU_REGION_ENABLE );
\r
713 /* Re-instate the privileged only RAM region as xRegion[ 0 ] will have
\r
714 just removed the privileged only parameters. */
\r
715 xMPUSettings->xRegion[ 1 ].ulRegionBaseAddress =
\r
716 ( ( uint32_t ) __privileged_data_start__ ) | /* Base address. */
\r
717 ( portMPU_REGION_VALID ) |
\r
718 ( portSTACK_REGION + 1 );
\r
720 xMPUSettings->xRegion[ 1 ].ulRegionAttribute =
\r
721 ( portMPU_REGION_PRIVILEGED_READ_WRITE ) |
\r
722 ( portMPU_REGION_CACHEABLE_BUFFERABLE ) |
\r
723 prvGetMPURegionSizeSetting( ( uint32_t ) __privileged_data_end__ - ( uint32_t ) __privileged_data_start__ ) |
\r
724 ( portMPU_REGION_ENABLE );
\r
726 /* Invalidate all other regions. */
\r
727 for( ul = 2; ul <= portNUM_CONFIGURABLE_REGIONS; ul++ )
\r
729 xMPUSettings->xRegion[ ul ].ulRegionBaseAddress = ( portSTACK_REGION + ul ) | portMPU_REGION_VALID;
\r
730 xMPUSettings->xRegion[ ul ].ulRegionAttribute = 0UL;
\r
735 /* This function is called automatically when the task is created - in
\r
736 which case the stack region parameters will be valid. At all other
\r
737 times the stack parameters will not be valid and it is assumed that the
\r
738 stack region has already been configured. */
\r
739 if( ulStackDepth > 0 )
\r
741 /* Define the region that allows access to the stack. */
\r
742 xMPUSettings->xRegion[ 0 ].ulRegionBaseAddress =
\r
743 ( ( uint32_t ) pxBottomOfStack ) |
\r
744 ( portMPU_REGION_VALID ) |
\r
745 ( portSTACK_REGION ); /* Region number. */
\r
747 xMPUSettings->xRegion[ 0 ].ulRegionAttribute =
\r
748 ( portMPU_REGION_READ_WRITE ) | /* Read and write. */
\r
749 ( prvGetMPURegionSizeSetting( ulStackDepth * ( uint32_t ) sizeof( StackType_t ) ) ) |
\r
750 ( portMPU_REGION_CACHEABLE_BUFFERABLE ) |
\r
751 ( portMPU_REGION_ENABLE );
\r
756 for( ul = 1; ul <= portNUM_CONFIGURABLE_REGIONS; ul++ )
\r
758 if( ( xRegions[ lIndex ] ).ulLengthInBytes > 0UL )
\r
760 /* Translate the generic region definition contained in
\r
761 xRegions into the CM3 specific MPU settings that are then
\r
762 stored in xMPUSettings. */
\r
763 xMPUSettings->xRegion[ ul ].ulRegionBaseAddress =
\r
764 ( ( uint32_t ) xRegions[ lIndex ].pvBaseAddress ) |
\r
765 ( portMPU_REGION_VALID ) |
\r
766 ( portSTACK_REGION + ul ); /* Region number. */
\r
768 xMPUSettings->xRegion[ ul ].ulRegionAttribute =
\r
769 ( prvGetMPURegionSizeSetting( xRegions[ lIndex ].ulLengthInBytes ) ) |
\r
770 ( xRegions[ lIndex ].ulParameters ) |
\r
771 ( portMPU_REGION_ENABLE );
\r
775 /* Invalidate the region. */
\r
776 xMPUSettings->xRegion[ ul ].ulRegionBaseAddress = ( portSTACK_REGION + ul ) | portMPU_REGION_VALID;
\r
777 xMPUSettings->xRegion[ ul ].ulRegionAttribute = 0UL;
\r
784 /*-----------------------------------------------------------*/
\r
786 #if( configASSERT_DEFINED == 1 )
\r
788 void vPortValidateInterruptPriority( void )
\r
790 uint32_t ulCurrentInterrupt;
\r
791 uint8_t ucCurrentPriority;
\r
793 /* Obtain the number of the currently executing interrupt. */
\r
794 __asm volatile( "mrs %0, ipsr" : "=r"( ulCurrentInterrupt ) );
\r
796 /* Is the interrupt number a user defined interrupt? */
\r
797 if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER )
\r
799 /* Look up the interrupt's priority. */
\r
800 ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ];
\r
802 /* The following assertion will fail if a service routine (ISR) for
\r
803 an interrupt that has been assigned a priority above
\r
804 configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API
\r
805 function. ISR safe FreeRTOS API functions must *only* be called
\r
806 from interrupts that have been assigned a priority at or below
\r
807 configMAX_SYSCALL_INTERRUPT_PRIORITY.
\r
809 Numerically low interrupt priority numbers represent logically high
\r
810 interrupt priorities, therefore the priority of the interrupt must
\r
811 be set to a value equal to or numerically *higher* than
\r
812 configMAX_SYSCALL_INTERRUPT_PRIORITY.
\r
814 Interrupts that use the FreeRTOS API must not be left at their
\r
815 default priority of zero as that is the highest possible priority,
\r
816 which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY,
\r
817 and therefore also guaranteed to be invalid.
\r
819 FreeRTOS maintains separate thread and ISR API functions to ensure
\r
820 interrupt entry is as fast and simple as possible.
\r
822 The following links provide detailed information:
\r
823 http://www.freertos.org/RTOS-Cortex-M3-M4.html
\r
824 http://www.freertos.org/FAQHelp.html */
\r
825 configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );
\r
828 /* Priority grouping: The interrupt controller (NVIC) allows the bits
\r
829 that define each interrupt's priority to be split between bits that
\r
830 define the interrupt's pre-emption priority bits and bits that define
\r
831 the interrupt's sub-priority. For simplicity all bits must be defined
\r
832 to be pre-emption priority bits. The following assertion will fail if
\r
833 this is not the case (if some bits represent a sub-priority).
\r
835 If the application only uses CMSIS libraries for interrupt
\r
836 configuration then the correct setting can be achieved on all Cortex-M
\r
837 devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the
\r
838 scheduler. Note however that some vendor specific peripheral libraries
\r
839 assume a non-zero priority group setting, in which cases using a value
\r
840 of zero will result in unpredicable behaviour. */
\r
841 configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );
\r
844 #endif /* configASSERT_DEFINED */
\r
845 /*-----------------------------------------------------------*/
\r
projects / freertos / blob