git.sur5r.net Git - freertos/blob - FreeRTOS/Source/portable/GCC/ARM_CM4_MPU/port.c

   1 /*\r
   2  * FreeRTOS Kernel V10.0.1\r
   3  * Copyright (C) 2017 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\r
   4  *\r
   5  * Permission is hereby granted, free of charge, to any person obtaining a copy of\r
   6  * this software and associated documentation files (the "Software"), to deal in\r
   7  * the Software without restriction, including without limitation the rights to\r
   8  * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\r
   9  * the Software, and to permit persons to whom the Software is furnished to do so,\r
  10  * subject to the following conditions:\r
  11  *\r
  12  * The above copyright notice and this permission notice shall be included in all\r
  13  * copies or substantial portions of the Software.\r
  14  *\r
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\r
  17  * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\r
  18  * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r
  19  * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
  20  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
  21  *\r
  22  * http://www.FreeRTOS.org\r
  23  * http://aws.amazon.com/freertos\r
  24  *\r
  25  * 1 tab == 4 spaces!\r
  26  */\r
  27 \r
  28 /*-----------------------------------------------------------\r
  29  * Implementation of functions defined in portable.h for the ARM CM3 port.\r
  30  *----------------------------------------------------------*/\r
  31 \r
  32 /* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining\r
  33 all the API functions to use the MPU wrappers.  That should only be done when\r
  34 task.h is included from an application file. */\r
  35 #define MPU_WRAPPERS_INCLUDED_FROM_API_FILE\r
  36 \r
  37 /* Scheduler includes. */\r
  38 #include "FreeRTOS.h"\r
  39 #include "task.h"\r
  40 \r
  41 #ifndef __VFP_FP__\r
  42         #error This port can only be used when the project options are configured to enable hardware floating point support.\r
  43 #endif\r
  44 \r
  45 #undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE\r
  46 \r
  47 #ifndef configSYSTICK_CLOCK_HZ\r
  48         #define configSYSTICK_CLOCK_HZ configCPU_CLOCK_HZ\r
  49         /* Ensure the SysTick is clocked at the same frequency as the core. */\r
  50         #define portNVIC_SYSTICK_CLK    ( 1UL << 2UL )\r
  51 #else\r
  52         /* The way the SysTick is clocked is not modified in case it is not the same\r
  53         as the core. */\r
  54         #define portNVIC_SYSTICK_CLK    ( 0 )\r
  55 #endif\r
  56 \r
  57 /* Constants required to access and manipulate the NVIC. */\r
  58 #define portNVIC_SYSTICK_CTRL_REG                               ( * ( ( volatile uint32_t * ) 0xe000e010 ) )\r
  59 #define portNVIC_SYSTICK_LOAD_REG                               ( * ( ( volatile uint32_t * ) 0xe000e014 ) )\r
  60 #define portNVIC_SYSTICK_CURRENT_VALUE_REG              ( * ( ( volatile uint32_t * ) 0xe000e018 ) )\r
  61 #define portNVIC_SYSPRI2_REG                                    ( *     ( ( volatile uint32_t * ) 0xe000ed20 ) )\r
  62 #define portNVIC_SYSPRI1_REG                                    ( * ( ( volatile uint32_t * ) 0xe000ed1c ) )\r
  63 #define portNVIC_SYS_CTRL_STATE_REG                             ( * ( ( volatile uint32_t * ) 0xe000ed24 ) )\r
  64 #define portNVIC_MEM_FAULT_ENABLE                               ( 1UL << 16UL )\r
  65 \r
  66 /* Constants required to access and manipulate the MPU. */\r
  67 #define portMPU_TYPE_REG                                                ( * ( ( volatile uint32_t * ) 0xe000ed90 ) )\r
  68 #define portMPU_REGION_BASE_ADDRESS_REG                 ( * ( ( volatile uint32_t * ) 0xe000ed9C ) )\r
  69 #define portMPU_REGION_ATTRIBUTE_REG                    ( * ( ( volatile uint32_t * ) 0xe000edA0 ) )\r
  70 #define portMPU_CTRL_REG                                                ( * ( ( volatile uint32_t * ) 0xe000ed94 ) )\r
  71 #define portEXPECTED_MPU_TYPE_VALUE                             ( 8UL << 8UL ) /* 8 regions, unified. */\r
  72 #define portMPU_ENABLE                                                  ( 0x01UL )\r
  73 #define portMPU_BACKGROUND_ENABLE                               ( 1UL << 2UL )\r
  74 #define portPRIVILEGED_EXECUTION_START_ADDRESS  ( 0UL )\r
  75 #define portMPU_REGION_VALID                                    ( 0x10UL )\r
  76 #define portMPU_REGION_ENABLE                                   ( 0x01UL )\r
  77 #define portPERIPHERALS_START_ADDRESS                   0x40000000UL\r
  78 #define portPERIPHERALS_END_ADDRESS                             0x5FFFFFFFUL\r
  79 \r
  80 /* Constants required to access and manipulate the SysTick. */\r
  81 #define portNVIC_SYSTICK_INT                                    ( 0x00000002UL )\r
  82 #define portNVIC_SYSTICK_ENABLE                                 ( 0x00000001UL )\r
  83 #define portNVIC_PENDSV_PRI                                             ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL )\r
  84 #define portNVIC_SYSTICK_PRI                                    ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL )\r
  85 #define portNVIC_SVC_PRI                                                ( ( ( uint32_t ) configMAX_SYSCALL_INTERRUPT_PRIORITY - 1UL ) << 24UL )\r
  86 \r
  87 /* Constants required to manipulate the VFP. */\r
  88 #define portFPCCR                                                               ( ( volatile uint32_t * ) 0xe000ef34UL ) /* Floating point context control register. */\r
  89 #define portASPEN_AND_LSPEN_BITS                                ( 0x3UL << 30UL )\r
  90 \r
  91 /* Constants required to set up the initial stack. */\r
  92 #define portINITIAL_XPSR                                                ( 0x01000000UL )\r
  93 #define portINITIAL_EXC_RETURN                                  ( 0xfffffffdUL )\r
  94 #define portINITIAL_CONTROL_IF_UNPRIVILEGED             ( 0x03 )\r
  95 #define portINITIAL_CONTROL_IF_PRIVILEGED               ( 0x02 )\r
  96 \r
  97 /* Constants required to check the validity of an interrupt priority. */\r
  98 #define portFIRST_USER_INTERRUPT_NUMBER         ( 16 )\r
  99 #define portNVIC_IP_REGISTERS_OFFSET_16         ( 0xE000E3F0 )\r
 100 #define portAIRCR_REG                                           ( * ( ( volatile uint32_t * ) 0xE000ED0C ) )\r
 101 #define portMAX_8_BIT_VALUE                                     ( ( uint8_t ) 0xff )\r
 102 #define portTOP_BIT_OF_BYTE                                     ( ( uint8_t ) 0x80 )\r
 103 #define portMAX_PRIGROUP_BITS                           ( ( uint8_t ) 7 )\r
 104 #define portPRIORITY_GROUP_MASK                         ( 0x07UL << 8UL )\r
 105 #define portPRIGROUP_SHIFT                                      ( 8UL )\r
 106 \r
 107 /* Offsets in the stack to the parameters when inside the SVC handler. */\r
 108 #define portOFFSET_TO_PC                                                ( 6 )\r
 109 \r
 110 /* For strict compliance with the Cortex-M spec the task start address should\r
 111 have bit-0 clear, as it is loaded into the PC on exit from an ISR. */\r
 112 #define portSTART_ADDRESS_MASK                          ( ( StackType_t ) 0xfffffffeUL )\r
 113 \r
 114 /*\r
 115  * Configure a number of standard MPU regions that are used by all tasks.\r
 116  */\r
 117 static void prvSetupMPU( void ) PRIVILEGED_FUNCTION;\r
 118 \r
 119 /*\r
 120  * Return the smallest MPU region size that a given number of bytes will fit\r
 121  * into.  The region size is returned as the value that should be programmed\r
 122  * into the region attribute register for that region.\r
 123  */\r
 124 static uint32_t prvGetMPURegionSizeSetting( uint32_t ulActualSizeInBytes ) PRIVILEGED_FUNCTION;\r
 125 \r
 126 /*\r
 127  * Checks to see if being called from the context of an unprivileged task, and\r
 128  * if so raises the privilege level and returns false - otherwise does nothing\r
 129  * other than return true.\r
 130  */\r
 131 BaseType_t xPortRaisePrivilege( void ) __attribute__(( naked ));\r
 132 \r
 133 /*\r
 134  * Setup the timer to generate the tick interrupts.  The implementation in this\r
 135  * file is weak to allow application writers to change the timer used to\r
 136  * generate the tick interrupt.\r
 137  */\r
 138 void vPortSetupTimerInterrupt( void );\r
 139 \r
 140 /*\r
 141  * Standard FreeRTOS exception handlers.\r
 142  */\r
 143 void xPortPendSVHandler( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;\r
 144 void xPortSysTickHandler( void )  __attribute__ ((optimize("3"))) PRIVILEGED_FUNCTION;\r
 145 void vPortSVCHandler( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;\r
 146 \r
 147 /*\r
 148  * Starts the scheduler by restoring the context of the first task to run.\r
 149  */\r
 150 static void prvRestoreContextOfFirstTask( void ) __attribute__(( naked )) PRIVILEGED_FUNCTION;\r
 151 \r
 152 /*\r
 153  * C portion of the SVC handler.  The SVC handler is split between an asm entry\r
 154  * and a C wrapper for simplicity of coding and maintenance.\r
 155  */\r
 156 static void prvSVCHandler( uint32_t *pulRegisters ) __attribute__(( noinline )) PRIVILEGED_FUNCTION;\r
 157 \r
 158 /*\r
 159  * Function to enable the VFP.\r
 160  */\r
 161  static void vPortEnableVFP( void ) __attribute__ (( naked ));\r
 162 \r
 163 /*-----------------------------------------------------------*/\r
 164 \r
 165 /* Each task maintains its own interrupt status in the critical nesting\r
 166 variable.  Note this is not saved as part of the task context as context\r
 167 switches can only occur when uxCriticalNesting is zero. */\r
 168 static UBaseType_t uxCriticalNesting = 0xaaaaaaaa;\r
 169 \r
 170 /*\r
 171  * Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure\r
 172  * FreeRTOS API functions are not called from interrupts that have been assigned\r
 173  * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY.\r
 174  */\r
 175 #if ( configASSERT_DEFINED == 1 )\r
 176          static uint8_t ucMaxSysCallPriority = 0;\r
 177          static uint32_t ulMaxPRIGROUPValue = 0;\r
 178          static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const volatile uint8_t * const ) portNVIC_IP_REGISTERS_OFFSET_16;\r
 179 #endif /* configASSERT_DEFINED */\r
 180 \r
 181 /*-----------------------------------------------------------*/\r
 182 \r
 183 /*\r
 184  * See header file for description.\r
 185  */\r
 186 StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters, BaseType_t xRunPrivileged )\r
 187 {\r
 188         /* Simulate the stack frame as it would be created by a context switch\r
 189         interrupt. */\r
 190         pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */\r
 191         *pxTopOfStack = portINITIAL_XPSR;       /* xPSR */\r
 192         pxTopOfStack--;\r
 193         *pxTopOfStack = ( ( StackType_t ) pxCode ) & portSTART_ADDRESS_MASK;    /* PC */\r
 194         pxTopOfStack--;\r
 195         *pxTopOfStack = 0;      /* LR */\r
 196         pxTopOfStack -= 5;      /* R12, R3, R2 and R1. */\r
 197         *pxTopOfStack = ( StackType_t ) pvParameters;   /* R0 */\r
 198 \r
 199         /* A save method is being used that requires each task to maintain its\r
 200         own exec return value. */\r
 201         pxTopOfStack--;\r
 202         *pxTopOfStack = portINITIAL_EXC_RETURN;\r
 203 \r
 204         pxTopOfStack -= 9;      /* R11, R10, R9, R8, R7, R6, R5 and R4. */\r
 205 \r
 206         if( xRunPrivileged == pdTRUE )\r
 207         {\r
 208                 *pxTopOfStack = portINITIAL_CONTROL_IF_PRIVILEGED;\r
 209         }\r
 210         else\r
 211         {\r
 212                 *pxTopOfStack = portINITIAL_CONTROL_IF_UNPRIVILEGED;\r
 213         }\r
 214 \r
 215         return pxTopOfStack;\r
 216 }\r
 217 /*-----------------------------------------------------------*/\r
 218 \r
 219 void vPortSVCHandler( void )\r
 220 {\r
 221         /* Assumes psp was in use. */\r
 222         __asm volatile\r
 223         (\r
 224                 #ifndef USE_PROCESS_STACK       /* Code should not be required if a main() is using the process stack. */\r
 225                         "       tst lr, #4                                              \n"\r
 226                         "       ite eq                                                  \n"\r
 227                         "       mrseq r0, msp                                   \n"\r
 228                         "       mrsne r0, psp                                   \n"\r
 229                 #else\r
 230                         "       mrs r0, psp                                             \n"\r
 231                 #endif\r
 232                         "       b %0                                                    \n"\r
 233                         ::"i"(prvSVCHandler):"r0", "memory"\r
 234         );\r
 235 }\r
 236 /*-----------------------------------------------------------*/\r
 237 \r
 238 static void prvSVCHandler(      uint32_t *pulParam )\r
 239 {\r
 240 uint8_t ucSVCNumber;\r
 241 \r
 242         /* The stack contains: r0, r1, r2, r3, r12, r14, the return address and\r
 243         xPSR.  The first argument (r0) is pulParam[ 0 ]. */\r
 244         ucSVCNumber = ( ( uint8_t * ) pulParam[ portOFFSET_TO_PC ] )[ -2 ];\r
 245         switch( ucSVCNumber )\r
 246         {\r
 247                 case portSVC_START_SCHEDULER    :       portNVIC_SYSPRI1_REG |= portNVIC_SVC_PRI;\r
 248                                                                                         prvRestoreContextOfFirstTask();\r
 249                                                                                         break;\r
 250 \r
 251                 case portSVC_YIELD                              :       portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;\r
 252                                                                                         /* Barriers are normally not required\r
 253                                                                                         but do ensure the code is completely\r
 254                                                                                         within the specified behaviour for the\r
 255                                                                                         architecture. */\r
 256                                                                                         __asm volatile( "dsb" ::: "memory" );\r
 257                                                                                         __asm volatile( "isb" );\r
 258 \r
 259                                                                                         break;\r
 260 \r
 261                 case portSVC_RAISE_PRIVILEGE    :       __asm volatile\r
 262                                                                                         (\r
 263                                                                                                 "       mrs r1, control         \n" /* Obtain current control value. */\r
 264                                                                                                 "       bic r1, #1                      \n" /* Set privilege bit. */\r
 265                                                                                                 "       msr control, r1         \n" /* Write back new control value. */\r
 266                                                                                                 ::: "r1", "memory"\r
 267                                                                                         );\r
 268                                                                                         break;\r
 269 \r
 270                 default                                                 :       /* Unknown SVC call. */\r
 271                                                                                         break;\r
 272         }\r
 273 }\r
 274 /*-----------------------------------------------------------*/\r
 275 \r
 276 static void prvRestoreContextOfFirstTask( void )\r
 277 {\r
 278         __asm volatile\r
 279         (\r
 280                 "       ldr r0, =0xE000ED08                             \n" /* Use the NVIC offset register to locate the stack. */\r
 281                 "       ldr r0, [r0]                                    \n"\r
 282                 "       ldr r0, [r0]                                    \n"\r
 283                 "       msr msp, r0                                             \n" /* Set the msp back to the start of the stack. */\r
 284                 "       ldr     r3, pxCurrentTCBConst2          \n" /* Restore the context. */\r
 285                 "       ldr r1, [r3]                                    \n"\r
 286                 "       ldr r0, [r1]                                    \n" /* The first item in the TCB is the task top of stack. */\r
 287                 "       add r1, r1, #4                                  \n" /* Move onto the second item in the TCB... */\r
 288                 "       ldr r2, =0xe000ed9c                             \n" /* Region Base Address register. */\r
 289                 "       ldmia r1!, {r4-r11}                             \n" /* Read 4 sets of MPU registers. */\r
 290                 "       stmia r2!, {r4-r11}                             \n" /* Write 4 sets of MPU registers. */\r
 291                 "       ldmia r0!, {r3-r11, r14}                \n" /* Pop the registers that are not automatically saved on exception entry. */\r
 292                 "       msr control, r3                                 \n"\r
 293                 "       msr psp, r0                                             \n" /* Restore the task stack pointer. */\r
 294                 "       mov r0, #0                                              \n"\r
 295                 "       msr     basepri, r0                                     \n"\r
 296                 "       bx r14                                                  \n"\r
 297                 "                                                                       \n"\r
 298                 "       .align 4                                                \n"\r
 299                 "pxCurrentTCBConst2: .word pxCurrentTCB \n"\r
 300         );\r
 301 }\r
 302 /*-----------------------------------------------------------*/\r
 303 \r
 304 /*\r
 305  * See header file for description.\r
 306  */\r
 307 BaseType_t xPortStartScheduler( void )\r
 308 {\r
 309         /* configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0.  See\r
 310         http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */\r
 311         configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) );\r
 312 \r
 313         #if( configASSERT_DEFINED == 1 )\r
 314         {\r
 315                 volatile uint32_t ulOriginalPriority;\r
 316                 volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER );\r
 317                 volatile uint8_t ucMaxPriorityValue;\r
 318 \r
 319                 /* Determine the maximum priority from which ISR safe FreeRTOS API\r
 320                 functions can be called.  ISR safe functions are those that end in\r
 321                 "FromISR".  FreeRTOS maintains separate thread and ISR API functions to\r
 322                 ensure interrupt entry is as fast and simple as possible.\r
 323 \r
 324                 Save the interrupt priority value that is about to be clobbered. */\r
 325                 ulOriginalPriority = *pucFirstUserPriorityRegister;\r
 326 \r
 327                 /* Determine the number of priority bits available.  First write to all\r
 328                 possible bits. */\r
 329                 *pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;\r
 330 \r
 331                 /* Read the value back to see how many bits stuck. */\r
 332                 ucMaxPriorityValue = *pucFirstUserPriorityRegister;\r
 333 \r
 334                 /* Use the same mask on the maximum system call priority. */\r
 335                 ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;\r
 336 \r
 337                 /* Calculate the maximum acceptable priority group value for the number\r
 338                 of bits read back. */\r
 339                 ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;\r
 340                 while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )\r
 341                 {\r
 342                         ulMaxPRIGROUPValue--;\r
 343                         ucMaxPriorityValue <<= ( uint8_t ) 0x01;\r
 344                 }\r
 345 \r
 346                 #ifdef __NVIC_PRIO_BITS\r
 347                 {\r
 348                         /* Check the CMSIS configuration that defines the number of\r
 349                         priority bits matches the number of priority bits actually queried\r
 350                         from the hardware. */\r
 351                         configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == __NVIC_PRIO_BITS );\r
 352                 }\r
 353                 #endif\r
 354 \r
 355                 #ifdef configPRIO_BITS\r
 356                 {\r
 357                         /* Check the FreeRTOS configuration that defines the number of\r
 358                         priority bits matches the number of priority bits actually queried\r
 359                         from the hardware. */\r
 360                         configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == configPRIO_BITS );\r
 361                 }\r
 362                 #endif\r
 363 \r
 364                 /* Shift the priority group value back to its position within the AIRCR\r
 365                 register. */\r
 366                 ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;\r
 367                 ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;\r
 368 \r
 369                 /* Restore the clobbered interrupt priority register to its original\r
 370                 value. */\r
 371                 *pucFirstUserPriorityRegister = ulOriginalPriority;\r
 372         }\r
 373         #endif /* conifgASSERT_DEFINED */\r
 374 \r
 375         /* Make PendSV and SysTick the same priority as the kernel, and the SVC\r
 376         handler higher priority so it can be used to exit a critical section (where\r
 377         lower priorities are masked). */\r
 378         portNVIC_SYSPRI2_REG |= portNVIC_PENDSV_PRI;\r
 379         portNVIC_SYSPRI2_REG |= portNVIC_SYSTICK_PRI;\r
 380 \r
 381         /* Configure the regions in the MPU that are common to all tasks. */\r
 382         prvSetupMPU();\r
 383 \r
 384         /* Start the timer that generates the tick ISR.  Interrupts are disabled\r
 385         here already. */\r
 386         vPortSetupTimerInterrupt();\r
 387 \r
 388         /* Initialise the critical nesting count ready for the first task. */\r
 389         uxCriticalNesting = 0;\r
 390 \r
 391         /* Ensure the VFP is enabled - it should be anyway. */\r
 392         vPortEnableVFP();\r
 393 \r
 394         /* Lazy save always. */\r
 395         *( portFPCCR ) |= portASPEN_AND_LSPEN_BITS;\r
 396 \r
 397         /* Start the first task.  This also clears the bit that indicates the FPU is\r
 398         in use in case the FPU was used before the scheduler was started - which\r
 399         would otherwise result in the unnecessary leaving of space in the SVC stack\r
 400         for lazy saving of FPU registers. */\r
 401         __asm volatile(\r
 402                                         " ldr r0, =0xE000ED08   \n" /* Use the NVIC offset register to locate the stack. */\r
 403                                         " ldr r0, [r0]                  \n"\r
 404                                         " ldr r0, [r0]                  \n"\r
 405                                         " msr msp, r0                   \n" /* Set the msp back to the start of the stack. */\r
 406                                         " mov r0, #0                    \n" /* Clear the bit that indicates the FPU is in use, see comment above. */\r
 407                                         " msr control, r0               \n"\r
 408                                         " cpsie i                               \n" /* Globally enable interrupts. */\r
 409                                         " cpsie f                               \n"\r
 410                                         " dsb                                   \n"\r
 411                                         " isb                                   \n"\r
 412                                         " svc %0                                \n" /* System call to start first task. */\r
 413                                         " nop                                   \n"\r
 414                                         :: "i" (portSVC_START_SCHEDULER) : "memory" );\r
 415 \r
 416         /* Should not get here! */\r
 417         return 0;\r
 418 }\r
 419 /*-----------------------------------------------------------*/\r
 420 \r
 421 void vPortEndScheduler( void )\r
 422 {\r
 423         /* Not implemented in ports where there is nothing to return to.\r
 424         Artificially force an assert. */\r
 425         configASSERT( uxCriticalNesting == 1000UL );\r
 426 }\r
 427 /*-----------------------------------------------------------*/\r
 428 \r
 429 void vPortEnterCritical( void )\r
 430 {\r
 431 BaseType_t xRunningPrivileged = xPortRaisePrivilege();\r
 432 \r
 433         portDISABLE_INTERRUPTS();\r
 434         uxCriticalNesting++;\r
 435 \r
 436         vPortResetPrivilege( xRunningPrivileged );\r
 437 }\r
 438 /*-----------------------------------------------------------*/\r
 439 \r
 440 void vPortExitCritical( void )\r
 441 {\r
 442 BaseType_t xRunningPrivileged = xPortRaisePrivilege();\r
 443 \r
 444         configASSERT( uxCriticalNesting );\r
 445         uxCriticalNesting--;\r
 446         if( uxCriticalNesting == 0 )\r
 447         {\r
 448                 portENABLE_INTERRUPTS();\r
 449         }\r
 450         vPortResetPrivilege( xRunningPrivileged );\r
 451 }\r
 452 /*-----------------------------------------------------------*/\r
 453 \r
 454 void xPortPendSVHandler( void )\r
 455 {\r
 456         /* This is a naked function. */\r
 457 \r
 458         __asm volatile\r
 459         (\r
 460                 "       mrs r0, psp                                                     \n"\r
 461                 "       isb                                                                     \n"\r
 462                 "                                                                               \n"\r
 463                 "       ldr     r3, pxCurrentTCBConst                   \n" /* Get the location of the current TCB. */\r
 464                 "       ldr     r2, [r3]                                                \n"\r
 465                 "                                                                               \n"\r
 466                 "       tst r14, #0x10                                          \n" /* Is the task using the FPU context?  If so, push high vfp registers. */\r
 467                 "       it eq                                                           \n"\r
 468                 "       vstmdbeq r0!, {s16-s31}                         \n"\r
 469                 "                                                                               \n"\r
 470                 "       mrs r1, control                                         \n"\r
 471                 "       stmdb r0!, {r1, r4-r11, r14}            \n" /* Save the remaining registers. */\r
 472                 "       str r0, [r2]                                            \n" /* Save the new top of stack into the first member of the TCB. */\r
 473                 "                                                                               \n"\r
 474                 "       stmdb sp!, {r0, r3}                                     \n"\r
 475                 "       mov r0, %0                                                      \n"\r
 476                 "       msr basepri, r0                                         \n"\r
 477                 "       dsb                                                                     \n"\r
 478                 "       isb                                                                     \n"\r
 479                 "       bl vTaskSwitchContext                           \n"\r
 480                 "       mov r0, #0                                                      \n"\r
 481                 "       msr basepri, r0                                         \n"\r
 482                 "       ldmia sp!, {r0, r3}                                     \n"\r
 483                 "                                                                               \n" /* Restore the context. */\r
 484                 "       ldr r1, [r3]                                            \n"\r
 485                 "       ldr r0, [r1]                                            \n" /* The first item in the TCB is the task top of stack. */\r
 486                 "       add r1, r1, #4                                          \n" /* Move onto the second item in the TCB... */\r
 487                 "       ldr r2, =0xe000ed9c                                     \n" /* Region Base Address register. */\r
 488                 "       ldmia r1!, {r4-r11}                                     \n" /* Read 4 sets of MPU registers. */\r
 489                 "       stmia r2!, {r4-r11}                                     \n" /* Write 4 sets of MPU registers. */\r
 490                 "       ldmia r0!, {r3-r11, r14}                        \n" /* Pop the registers that are not automatically saved on exception entry. */\r
 491                 "       msr control, r3                                         \n"\r
 492                 "                                                                               \n"\r
 493                 "       tst r14, #0x10                                          \n" /* Is the task using the FPU context?  If so, pop the high vfp registers too. */\r
 494                 "       it eq                                                           \n"\r
 495                 "       vldmiaeq r0!, {s16-s31}                         \n"\r
 496                 "                                                                               \n"\r
 497                 "       msr psp, r0                                                     \n"\r
 498                 "       bx r14                                                          \n"\r
 499                 "                                                                               \n"\r
 500                 "       .align 4                                                        \n"\r
 501                 "pxCurrentTCBConst: .word pxCurrentTCB  \n"\r
 502                 ::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY)\r
 503         );\r
 504 }\r
 505 /*-----------------------------------------------------------*/\r
 506 \r
 507 void xPortSysTickHandler( void )\r
 508 {\r
 509 uint32_t ulDummy;\r
 510 \r
 511         ulDummy = portSET_INTERRUPT_MASK_FROM_ISR();\r
 512         {\r
 513                 /* Increment the RTOS tick. */\r
 514                 if( xTaskIncrementTick() != pdFALSE )\r
 515                 {\r
 516                         /* Pend a context switch. */\r
 517                         portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;\r
 518                 }\r
 519         }\r
 520         portCLEAR_INTERRUPT_MASK_FROM_ISR( ulDummy );\r
 521 }\r
 522 /*-----------------------------------------------------------*/\r
 523 \r
 524 /*\r
 525  * Setup the systick timer to generate the tick interrupts at the required\r
 526  * frequency.\r
 527  */\r
 528 __attribute__(( weak )) void vPortSetupTimerInterrupt( void )\r
 529 {\r
 530         /* Stop and clear the SysTick. */\r
 531         portNVIC_SYSTICK_CTRL_REG = 0UL;\r
 532         portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;\r
 533 \r
 534         /* Configure SysTick to interrupt at the requested rate. */\r
 535         portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;\r
 536         portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK | portNVIC_SYSTICK_INT | portNVIC_SYSTICK_ENABLE );\r
 537 }\r
 538 /*-----------------------------------------------------------*/\r
 539 \r
 540 /* This is a naked function. */\r
 541 static void vPortEnableVFP( void )\r
 542 {\r
 543         __asm volatile\r
 544         (\r
 545                 "       ldr.w r0, =0xE000ED88           \n" /* The FPU enable bits are in the CPACR. */\r
 546                 "       ldr r1, [r0]                            \n"\r
 547                 "                                                               \n"\r
 548                 "       orr r1, r1, #( 0xf << 20 )      \n" /* Enable CP10 and CP11 coprocessors, then save back. */\r
 549                 "       str r1, [r0]                            \n"\r
 550                 "       bx r14                                          "\r
 551         );\r
 552 }\r
 553 /*-----------------------------------------------------------*/\r
 554 \r
 555 static void prvSetupMPU( void )\r
 556 {\r
 557 extern uint32_t __privileged_functions_end__[];\r
 558 extern uint32_t __FLASH_segment_start__[];\r
 559 extern uint32_t __FLASH_segment_end__[];\r
 560 extern uint32_t __privileged_data_start__[];\r
 561 extern uint32_t __privileged_data_end__[];\r
 562 \r
 563         /* Check the expected MPU is present. */\r
 564         if( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE )\r
 565         {\r
 566                 /* First setup the entire flash for unprivileged read only access. */\r
 567                 portMPU_REGION_BASE_ADDRESS_REG =       ( ( uint32_t ) __FLASH_segment_start__ ) | /* Base address. */\r
 568                                                                                         ( portMPU_REGION_VALID ) |\r
 569                                                                                         ( portUNPRIVILEGED_FLASH_REGION );\r
 570 \r
 571                 portMPU_REGION_ATTRIBUTE_REG =  ( portMPU_REGION_READ_ONLY ) |\r
 572                                                                                 ( portMPU_REGION_CACHEABLE_BUFFERABLE ) |\r
 573                                                                                 ( prvGetMPURegionSizeSetting( ( uint32_t ) __FLASH_segment_end__ - ( uint32_t ) __FLASH_segment_start__ ) ) |\r
 574                                                                                 ( portMPU_REGION_ENABLE );\r
 575 \r
 576                 /* Setup the first 16K for privileged only access (even though less\r
 577                 than 10K is actually being used).  This is where the kernel code is\r
 578                 placed. */\r
 579                 portMPU_REGION_BASE_ADDRESS_REG =       ( ( uint32_t ) __FLASH_segment_start__ ) | /* Base address. */\r
 580                                                                                         ( portMPU_REGION_VALID ) |\r
 581                                                                                         ( portPRIVILEGED_FLASH_REGION );\r
 582 \r
 583                 portMPU_REGION_ATTRIBUTE_REG =  ( portMPU_REGION_PRIVILEGED_READ_ONLY ) |\r
 584                                                                                 ( portMPU_REGION_CACHEABLE_BUFFERABLE ) |\r
 585                                                                                 ( prvGetMPURegionSizeSetting( ( uint32_t ) __privileged_functions_end__ - ( uint32_t ) __FLASH_segment_start__ ) ) |\r
 586                                                                                 ( portMPU_REGION_ENABLE );\r
 587 \r
 588                 /* Setup the privileged data RAM region.  This is where the kernel data\r
 589                 is placed. */\r
 590                 portMPU_REGION_BASE_ADDRESS_REG =       ( ( uint32_t ) __privileged_data_start__ ) | /* Base address. */\r
 591                                                                                         ( portMPU_REGION_VALID ) |\r
 592                                                                                         ( portPRIVILEGED_RAM_REGION );\r
 593 \r
 594                 portMPU_REGION_ATTRIBUTE_REG =  ( portMPU_REGION_PRIVILEGED_READ_WRITE ) |\r
 595                                                                                 ( portMPU_REGION_CACHEABLE_BUFFERABLE ) |\r
 596                                                                                 prvGetMPURegionSizeSetting( ( uint32_t ) __privileged_data_end__ - ( uint32_t ) __privileged_data_start__ ) |\r
 597                                                                                 ( portMPU_REGION_ENABLE );\r
 598 \r
 599                 /* By default allow everything to access the general peripherals.  The\r
 600                 system peripherals and registers are protected. */\r
 601                 portMPU_REGION_BASE_ADDRESS_REG =       ( portPERIPHERALS_START_ADDRESS ) |\r
 602                                                                                         ( portMPU_REGION_VALID ) |\r
 603                                                                                         ( portGENERAL_PERIPHERALS_REGION );\r
 604 \r
 605                 portMPU_REGION_ATTRIBUTE_REG =  ( portMPU_REGION_READ_WRITE | portMPU_REGION_EXECUTE_NEVER ) |\r
 606                                                                                 ( prvGetMPURegionSizeSetting( portPERIPHERALS_END_ADDRESS - portPERIPHERALS_START_ADDRESS ) ) |\r
 607                                                                                 ( portMPU_REGION_ENABLE );\r
 608 \r
 609                 /* Enable the memory fault exception. */\r
 610                 portNVIC_SYS_CTRL_STATE_REG |= portNVIC_MEM_FAULT_ENABLE;\r
 611 \r
 612                 /* Enable the MPU with the background region configured. */\r
 613                 portMPU_CTRL_REG |= ( portMPU_ENABLE | portMPU_BACKGROUND_ENABLE );\r
 614         }\r
 615 }\r
 616 /*-----------------------------------------------------------*/\r
 617 \r
 618 static uint32_t prvGetMPURegionSizeSetting( uint32_t ulActualSizeInBytes )\r
 619 {\r
 620 uint32_t ulRegionSize, ulReturnValue = 4;\r
 621 \r
 622         /* 32 is the smallest region size, 31 is the largest valid value for\r
 623         ulReturnValue. */\r
 624         for( ulRegionSize = 32UL; ulReturnValue < 31UL; ( ulRegionSize <<= 1UL ) )\r
 625         {\r
 626                 if( ulActualSizeInBytes <= ulRegionSize )\r
 627                 {\r
 628                         break;\r
 629                 }\r
 630                 else\r
 631                 {\r
 632                         ulReturnValue++;\r
 633                 }\r
 634         }\r
 635 \r
 636         /* Shift the code by one before returning so it can be written directly\r
 637         into the the correct bit position of the attribute register. */\r
 638         return ( ulReturnValue << 1UL );\r
 639 }\r
 640 /*-----------------------------------------------------------*/\r
 641 \r
 642 BaseType_t xPortRaisePrivilege( void )\r
 643 {\r
 644         __asm volatile\r
 645         (\r
 646                 "       mrs r0, control                                         \n"\r
 647                 "       tst r0, #1                                                      \n" /* Is the task running privileged? */\r
 648                 "       itte ne                                                         \n"\r
 649                 "       movne r0, #0                                            \n" /* CONTROL[0]!=0, return false. */\r
 650                 "       svcne %0                                                        \n" /* Switch to privileged. */\r
 651                 "       moveq r0, #1                                            \n" /* CONTROL[0]==0, return true. */\r
 652                 "       bx lr                                                           \n"\r
 653                 :: "i" (portSVC_RAISE_PRIVILEGE) : "r0", "memory"\r
 654         );\r
 655 \r
 656         return 0;\r
 657 }\r
 658 /*-----------------------------------------------------------*/\r
 659 \r
 660 void vPortStoreTaskMPUSettings( xMPU_SETTINGS *xMPUSettings, const struct xMEMORY_REGION * const xRegions, StackType_t *pxBottomOfStack, uint32_t ulStackDepth )\r
 661 {\r
 662 extern uint32_t __SRAM_segment_start__[];\r
 663 extern uint32_t __SRAM_segment_end__[];\r
 664 extern uint32_t __privileged_data_start__[];\r
 665 extern uint32_t __privileged_data_end__[];\r
 666 int32_t lIndex;\r
 667 uint32_t ul;\r
 668 \r
 669         if( xRegions == NULL )\r
 670         {\r
 671                 /* No MPU regions are specified so allow access to all RAM. */\r
 672                 xMPUSettings->xRegion[ 0 ].ulRegionBaseAddress =\r
 673                                 ( ( uint32_t ) __SRAM_segment_start__ ) | /* Base address. */\r
 674                                 ( portMPU_REGION_VALID ) |\r
 675                                 ( portSTACK_REGION );\r
 676 \r
 677                 xMPUSettings->xRegion[ 0 ].ulRegionAttribute =\r
 678                                 ( portMPU_REGION_READ_WRITE ) |\r
 679                                 ( portMPU_REGION_CACHEABLE_BUFFERABLE ) |\r
 680                                 ( prvGetMPURegionSizeSetting( ( uint32_t ) __SRAM_segment_end__ - ( uint32_t ) __SRAM_segment_start__ ) ) |\r
 681                                 ( portMPU_REGION_ENABLE );\r
 682 \r
 683                 /* Re-instate the privileged only RAM region as xRegion[ 0 ] will have\r
 684                 just removed the privileged only parameters. */\r
 685                 xMPUSettings->xRegion[ 1 ].ulRegionBaseAddress =\r
 686                                 ( ( uint32_t ) __privileged_data_start__ ) | /* Base address. */\r
 687                                 ( portMPU_REGION_VALID ) |\r
 688                                 ( portSTACK_REGION + 1 );\r
 689 \r
 690                 xMPUSettings->xRegion[ 1 ].ulRegionAttribute =\r
 691                                 ( portMPU_REGION_PRIVILEGED_READ_WRITE ) |\r
 692                                 ( portMPU_REGION_CACHEABLE_BUFFERABLE ) |\r
 693                                 prvGetMPURegionSizeSetting( ( uint32_t ) __privileged_data_end__ - ( uint32_t ) __privileged_data_start__ ) |\r
 694                                 ( portMPU_REGION_ENABLE );\r
 695 \r
 696                 /* Invalidate all other regions. */\r
 697                 for( ul = 2; ul <= portNUM_CONFIGURABLE_REGIONS; ul++ )\r
 698                 {\r
 699                         xMPUSettings->xRegion[ ul ].ulRegionBaseAddress = ( portSTACK_REGION + ul ) | portMPU_REGION_VALID;\r
 700                         xMPUSettings->xRegion[ ul ].ulRegionAttribute = 0UL;\r
 701                 }\r
 702         }\r
 703         else\r
 704         {\r
 705                 /* This function is called automatically when the task is created - in\r
 706                 which case the stack region parameters will be valid.  At all other\r
 707                 times the stack parameters will not be valid and it is assumed that the\r
 708                 stack region has already been configured. */\r
 709                 if( ulStackDepth > 0 )\r
 710                 {\r
 711                         /* Define the region that allows access to the stack. */\r
 712                         xMPUSettings->xRegion[ 0 ].ulRegionBaseAddress =\r
 713                                         ( ( uint32_t ) pxBottomOfStack ) |\r
 714                                         ( portMPU_REGION_VALID ) |\r
 715                                         ( portSTACK_REGION ); /* Region number. */\r
 716 \r
 717                         xMPUSettings->xRegion[ 0 ].ulRegionAttribute =\r
 718                                         ( portMPU_REGION_READ_WRITE ) | /* Read and write. */\r
 719                                         ( prvGetMPURegionSizeSetting( ulStackDepth * ( uint32_t ) sizeof( StackType_t ) ) ) |\r
 720                                         ( portMPU_REGION_CACHEABLE_BUFFERABLE ) |\r
 721                                         ( portMPU_REGION_ENABLE );\r
 722                 }\r
 723 \r
 724                 lIndex = 0;\r
 725 \r
 726                 for( ul = 1; ul <= portNUM_CONFIGURABLE_REGIONS; ul++ )\r
 727                 {\r
 728                         if( ( xRegions[ lIndex ] ).ulLengthInBytes > 0UL )\r
 729                         {\r
 730                                 /* Translate the generic region definition contained in\r
 731                                 xRegions into the CM3 specific MPU settings that are then\r
 732                                 stored in xMPUSettings. */\r
 733                                 xMPUSettings->xRegion[ ul ].ulRegionBaseAddress =\r
 734                                                 ( ( uint32_t ) xRegions[ lIndex ].pvBaseAddress ) |\r
 735                                                 ( portMPU_REGION_VALID ) |\r
 736                                                 ( portSTACK_REGION + ul ); /* Region number. */\r
 737 \r
 738                                 xMPUSettings->xRegion[ ul ].ulRegionAttribute =\r
 739                                                 ( prvGetMPURegionSizeSetting( xRegions[ lIndex ].ulLengthInBytes ) ) |\r
 740                                                 ( xRegions[ lIndex ].ulParameters ) |\r
 741                                                 ( portMPU_REGION_ENABLE );\r
 742                         }\r
 743                         else\r
 744                         {\r
 745                                 /* Invalidate the region. */\r
 746                                 xMPUSettings->xRegion[ ul ].ulRegionBaseAddress = ( portSTACK_REGION + ul ) | portMPU_REGION_VALID;\r
 747                                 xMPUSettings->xRegion[ ul ].ulRegionAttribute = 0UL;\r
 748                         }\r
 749 \r
 750                         lIndex++;\r
 751                 }\r
 752         }\r
 753 }\r
 754 /*-----------------------------------------------------------*/\r
 755 \r
 756 #if( configASSERT_DEFINED == 1 )\r
 757 \r
 758         void vPortValidateInterruptPriority( void )\r
 759         {\r
 760         uint32_t ulCurrentInterrupt;\r
 761         uint8_t ucCurrentPriority;\r
 762 \r
 763                 /* Obtain the number of the currently executing interrupt. */\r
 764                 __asm volatile( "mrs %0, ipsr" : "=r"( ulCurrentInterrupt ) :: "memory" );\r
 765 \r
 766                 /* Is the interrupt number a user defined interrupt? */\r
 767                 if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER )\r
 768                 {\r
 769                         /* Look up the interrupt's priority. */\r
 770                         ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ];\r
 771 \r
 772                         /* The following assertion will fail if a service routine (ISR) for\r
 773                         an interrupt that has been assigned a priority above\r
 774                         configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API\r
 775                         function.  ISR safe FreeRTOS API functions must *only* be called\r
 776                         from interrupts that have been assigned a priority at or below\r
 777                         configMAX_SYSCALL_INTERRUPT_PRIORITY.\r
 778 \r
 779                         Numerically low interrupt priority numbers represent logically high\r
 780                         interrupt priorities, therefore the priority of the interrupt must\r
 781                         be set to a value equal to or numerically *higher* than\r
 782                         configMAX_SYSCALL_INTERRUPT_PRIORITY.\r
 783 \r
 784                         Interrupts that use the FreeRTOS API must not be left at their\r
 785                         default priority of     zero as that is the highest possible priority,\r
 786                         which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY,\r
 787                         and     therefore also guaranteed to be invalid.\r
 788 \r
 789                         FreeRTOS maintains separate thread and ISR API functions to ensure\r
 790                         interrupt entry is as fast and simple as possible.\r
 791 \r
 792                         The following links provide detailed information:\r
 793                         http://www.freertos.org/RTOS-Cortex-M3-M4.html\r
 794                         http://www.freertos.org/FAQHelp.html */\r
 795                         configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );\r
 796                 }\r
 797 \r
 798                 /* Priority grouping:  The interrupt controller (NVIC) allows the bits\r
 799                 that define each interrupt's priority to be split between bits that\r
 800                 define the interrupt's pre-emption priority bits and bits that define\r
 801                 the interrupt's sub-priority.  For simplicity all bits must be defined\r
 802                 to be pre-emption priority bits.  The following assertion will fail if\r
 803                 this is not the case (if some bits represent a sub-priority).\r
 804 \r
 805                 If the application only uses CMSIS libraries for interrupt\r
 806                 configuration then the correct setting can be achieved on all Cortex-M\r
 807                 devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the\r
 808                 scheduler.  Note however that some vendor specific peripheral libraries\r
 809                 assume a non-zero priority group setting, in which cases using a value\r
 810                 of zero will result in unpredicable behaviour. */\r
 811                 configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );\r
 812         }\r
 813 \r
 814 #endif /* configASSERT_DEFINED */\r
 815 /*-----------------------------------------------------------*/\r
 816 \r
 817 \r