git.sur5r.net Git - freertos/blob - FreeRTOS/Source/portable/GCC/ARM_CM4_MPU/port.c

   1 /*\r
   2     FreeRTOS V9.0.0 - Copyright (C) 2016 Real Time Engineers Ltd.\r
   3     All rights reserved\r
   4 \r
   5     VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
   6 \r
   7     This file is part of the FreeRTOS distribution.\r
   8 \r
   9     FreeRTOS is free software; you can redistribute it and/or modify it under\r
  10     the terms of the GNU General Public License (version 2) as published by the\r
  11     Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception.\r
  12 \r
  13     ***************************************************************************\r
  14     >>!   NOTE: The modification to the GPL is included to allow you to     !<<\r
  15     >>!   distribute a combined work that includes FreeRTOS without being   !<<\r
  16     >>!   obliged to provide the source code for proprietary components     !<<\r
  17     >>!   outside of the FreeRTOS kernel.                                   !<<\r
  18     ***************************************************************************\r
  19 \r
  20     FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
  21     WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
  22     FOR A PARTICULAR PURPOSE.  Full license text is available on the following\r
  23     link: http://www.freertos.org/a00114.html\r
  24 \r
  25     ***************************************************************************\r
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  36      *                                                                       *\r
  37     ***************************************************************************\r
  38 \r
  39     http://www.FreeRTOS.org/FAQHelp.html - Having a problem?  Start by reading\r
  40     the FAQ page "My application does not run, what could be wrong?".  Have you\r
  41     defined configASSERT()?\r
  42 \r
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  60     Integrity Systems ltd. to sell under the OpenRTOS brand.  Low cost OpenRTOS\r
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  62 \r
  63     http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
  64     engineered and independently SIL3 certified version for use in safety and\r
  65     mission critical applications that require provable dependability.\r
  66 \r
  67     1 tab == 4 spaces!\r
  68 */\r
  69 \r
  70 /*-----------------------------------------------------------\r
  71  * Implementation of functions defined in portable.h for the ARM CM3 port.\r
  72  *----------------------------------------------------------*/\r
  73 \r
  74 /* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining\r
  75 all the API functions to use the MPU wrappers.  That should only be done when\r
  76 task.h is included from an application file. */\r
  77 #define MPU_WRAPPERS_INCLUDED_FROM_API_FILE\r
  78 \r
  79 /* Scheduler includes. */\r
  80 #include "FreeRTOS.h"\r
  81 #include "queue.h"\r
  82 #include "event_groups.h"\r
  83 #include "mpu_prototypes.h"\r
  84 \r
  85 #ifndef __VFP_FP__\r
  86         #error This port can only be used when the project options are configured to enable hardware floating point support.\r
  87 #endif\r
  88 \r
  89 #undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE\r
  90 \r
  91 /* Constants required to access and manipulate the NVIC. */\r
  92 #define portNVIC_SYSTICK_CTRL_REG                               ( * ( ( volatile uint32_t * ) 0xe000e010 ) )\r
  93 #define portNVIC_SYSTICK_LOAD_REG                               ( * ( ( volatile uint32_t * ) 0xe000e014 ) )\r
  94 #define portNVIC_SYSPRI2_REG                                    ( *     ( ( volatile uint32_t * ) 0xe000ed20 ) )\r
  95 #define portNVIC_SYSPRI1_REG                                    ( * ( ( volatile uint32_t * ) 0xe000ed1c ) )\r
  96 #define portNVIC_SYS_CTRL_STATE_REG                             ( * ( ( volatile uint32_t * ) 0xe000ed24 ) )\r
  97 #define portNVIC_MEM_FAULT_ENABLE                               ( 1UL << 16UL )\r
  98 \r
  99 /* Constants required to access and manipulate the MPU. */\r
 100 #define portMPU_TYPE_REG                                                ( * ( ( volatile uint32_t * ) 0xe000ed90 ) )\r
 101 #define portMPU_REGION_BASE_ADDRESS_REG                 ( * ( ( volatile uint32_t * ) 0xe000ed9C ) )\r
 102 #define portMPU_REGION_ATTRIBUTE_REG                    ( * ( ( volatile uint32_t * ) 0xe000edA0 ) )\r
 103 #define portMPU_CTRL_REG                                                ( * ( ( volatile uint32_t * ) 0xe000ed94 ) )\r
 104 #define portEXPECTED_MPU_TYPE_VALUE                             ( 8UL << 8UL ) /* 8 regions, unified. */\r
 105 #define portMPU_ENABLE                                                  ( 0x01UL )\r
 106 #define portMPU_BACKGROUND_ENABLE                               ( 1UL << 2UL )\r
 107 #define portPRIVILEGED_EXECUTION_START_ADDRESS  ( 0UL )\r
 108 #define portMPU_REGION_VALID                                    ( 0x10UL )\r
 109 #define portMPU_REGION_ENABLE                                   ( 0x01UL )\r
 110 #define portPERIPHERALS_START_ADDRESS                   0x40000000UL\r
 111 #define portPERIPHERALS_END_ADDRESS                             0x5FFFFFFFUL\r
 112 \r
 113 /* Constants required to access and manipulate the SysTick. */\r
 114 #define portNVIC_SYSTICK_CLK                                    ( 0x00000004UL )\r
 115 #define portNVIC_SYSTICK_INT                                    ( 0x00000002UL )\r
 116 #define portNVIC_SYSTICK_ENABLE                                 ( 0x00000001UL )\r
 117 #define portNVIC_PENDSV_PRI                                             ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL )\r
 118 #define portNVIC_SYSTICK_PRI                                    ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL )\r
 119 #define portNVIC_SVC_PRI                                                ( ( ( uint32_t ) configMAX_SYSCALL_INTERRUPT_PRIORITY - 1UL ) << 24UL )\r
 120 \r
 121 /* Constants required to manipulate the VFP. */\r
 122 #define portFPCCR                                                               ( ( volatile uint32_t * ) 0xe000ef34UL ) /* Floating point context control register. */\r
 123 #define portASPEN_AND_LSPEN_BITS                                ( 0x3UL << 30UL )\r
 124 \r
 125 /* Constants required to set up the initial stack. */\r
 126 #define portINITIAL_XPSR                                                ( 0x01000000UL )\r
 127 #define portINITIAL_EXEC_RETURN                                 ( 0xfffffffdUL )\r
 128 #define portINITIAL_CONTROL_IF_UNPRIVILEGED             ( 0x03 )\r
 129 #define portINITIAL_CONTROL_IF_PRIVILEGED               ( 0x02 )\r
 130 \r
 131 /* Constants required to check the validity of an interrupt priority. */\r
 132 #define portFIRST_USER_INTERRUPT_NUMBER         ( 16 )\r
 133 #define portNVIC_IP_REGISTERS_OFFSET_16         ( 0xE000E3F0 )\r
 134 #define portAIRCR_REG                                           ( * ( ( volatile uint32_t * ) 0xE000ED0C ) )\r
 135 #define portMAX_8_BIT_VALUE                                     ( ( uint8_t ) 0xff )\r
 136 #define portTOP_BIT_OF_BYTE                                     ( ( uint8_t ) 0x80 )\r
 137 #define portMAX_PRIGROUP_BITS                           ( ( uint8_t ) 7 )\r
 138 #define portPRIORITY_GROUP_MASK                         ( 0x07UL << 8UL )\r
 139 #define portPRIGROUP_SHIFT                                      ( 8UL )\r
 140 \r
 141 /* Offsets in the stack to the parameters when inside the SVC handler. */\r
 142 #define portOFFSET_TO_PC                                                ( 6 )\r
 143 \r
 144 /* For strict compliance with the Cortex-M spec the task start address should\r
 145 have bit-0 clear, as it is loaded into the PC on exit from an ISR. */\r
 146 #define portSTART_ADDRESS_MASK                          ( ( StackType_t ) 0xfffffffeUL )\r
 147 \r
 148 /* Each task maintains its own interrupt status in the critical nesting\r
 149 variable.  Note this is not saved as part of the task context as context\r
 150 switches can only occur when uxCriticalNesting is zero. */\r
 151 static UBaseType_t uxCriticalNesting = 0xaaaaaaaa;\r
 152 \r
 153 /*\r
 154  * Setup the timer to generate the tick interrupts.\r
 155  */\r
 156 static void prvSetupTimerInterrupt( void ) PRIVILEGED_FUNCTION;\r
 157 \r
 158 /*\r
 159  * Configure a number of standard MPU regions that are used by all tasks.\r
 160  */\r
 161 static void prvSetupMPU( void ) PRIVILEGED_FUNCTION;\r
 162 \r
 163 /*\r
 164  * Return the smallest MPU region size that a given number of bytes will fit\r
 165  * into.  The region size is returned as the value that should be programmed\r
 166  * into the region attribute register for that region.\r
 167  */\r
 168 static uint32_t prvGetMPURegionSizeSetting( uint32_t ulActualSizeInBytes ) PRIVILEGED_FUNCTION;\r
 169 \r
 170 /*\r
 171  * Checks to see if being called from the context of an unprivileged task, and\r
 172  * if so raises the privilege level and returns false - otherwise does nothing\r
 173  * other than return true.\r
 174  */\r
 175 BaseType_t xPortRaisePrivilege( void ) __attribute__(( naked ));\r
 176 \r
 177 /*\r
 178  * Standard FreeRTOS exception handlers.\r
 179  */\r
 180 void xPortPendSVHandler( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;\r
 181 void xPortSysTickHandler( void )  __attribute__ ((optimize("3"))) PRIVILEGED_FUNCTION;\r
 182 void vPortSVCHandler( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;\r
 183 \r
 184 /*\r
 185  * Starts the scheduler by restoring the context of the first task to run.\r
 186  */\r
 187 static void prvRestoreContextOfFirstTask( void ) __attribute__(( naked )) PRIVILEGED_FUNCTION;\r
 188 \r
 189 /*\r
 190  * C portion of the SVC handler.  The SVC handler is split between an asm entry\r
 191  * and a C wrapper for simplicity of coding and maintenance.\r
 192  */\r
 193 static void prvSVCHandler( uint32_t *pulRegisters ) __attribute__(( noinline )) PRIVILEGED_FUNCTION;\r
 194 \r
 195 /*\r
 196  * Function to enable the VFP.\r
 197  */\r
 198  static void vPortEnableVFP( void ) __attribute__ (( naked ));\r
 199  \r
 200 /*\r
 201  * Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure\r
 202  * FreeRTOS API functions are not called from interrupts that have been assigned\r
 203  * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY.\r
 204  */\r
 205 #if ( configASSERT_DEFINED == 1 )\r
 206          static uint8_t ucMaxSysCallPriority = 0;\r
 207          static uint32_t ulMaxPRIGROUPValue = 0;\r
 208          static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const volatile uint8_t * const ) portNVIC_IP_REGISTERS_OFFSET_16;\r
 209 #endif /* configASSERT_DEFINED */\r
 210 \r
 211 /*-----------------------------------------------------------*/\r
 212 \r
 213 /*\r
 214  * See header file for description.\r
 215  */\r
 216 StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters, BaseType_t xRunPrivileged )\r
 217 {\r
 218         /* Simulate the stack frame as it would be created by a context switch\r
 219         interrupt. */\r
 220         pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */\r
 221         *pxTopOfStack = portINITIAL_XPSR;       /* xPSR */\r
 222         pxTopOfStack--;\r
 223         *pxTopOfStack = ( ( StackType_t ) pxCode ) & portSTART_ADDRESS_MASK;    /* PC */\r
 224         pxTopOfStack--;\r
 225         *pxTopOfStack = 0;      /* LR */\r
 226         pxTopOfStack -= 5;      /* R12, R3, R2 and R1. */\r
 227         *pxTopOfStack = ( StackType_t ) pvParameters;   /* R0 */\r
 228         \r
 229         /* A save method is being used that requires each task to maintain its\r
 230         own exec return value. */\r
 231         pxTopOfStack--;\r
 232         *pxTopOfStack = portINITIAL_EXEC_RETURN;\r
 233         \r
 234         pxTopOfStack -= 9;      /* R11, R10, R9, R8, R7, R6, R5 and R4. */\r
 235 \r
 236         if( xRunPrivileged == pdTRUE )\r
 237         {\r
 238                 *pxTopOfStack = portINITIAL_CONTROL_IF_PRIVILEGED;\r
 239         }\r
 240         else\r
 241         {\r
 242                 *pxTopOfStack = portINITIAL_CONTROL_IF_UNPRIVILEGED;\r
 243         }\r
 244 \r
 245         return pxTopOfStack;\r
 246 }\r
 247 /*-----------------------------------------------------------*/\r
 248 \r
 249 void vPortSVCHandler( void )\r
 250 {\r
 251         /* Assumes psp was in use. */\r
 252         __asm volatile\r
 253         (\r
 254                 #ifndef USE_PROCESS_STACK       /* Code should not be required if a main() is using the process stack. */\r
 255                         "       tst lr, #4                                              \n"\r
 256                         "       ite eq                                                  \n"\r
 257                         "       mrseq r0, msp                                   \n"\r
 258                         "       mrsne r0, psp                                   \n"\r
 259                 #else\r
 260                         "       mrs r0, psp                                             \n"\r
 261                 #endif\r
 262                         "       b %0                                                    \n"\r
 263                         ::"i"(prvSVCHandler):"r0"\r
 264         );\r
 265 }\r
 266 /*-----------------------------------------------------------*/\r
 267 \r
 268 static void prvSVCHandler(      uint32_t *pulParam )\r
 269 {\r
 270 uint8_t ucSVCNumber;\r
 271 \r
 272         /* The stack contains: r0, r1, r2, r3, r12, r14, the return address and\r
 273         xPSR.  The first argument (r0) is pulParam[ 0 ]. */\r
 274         ucSVCNumber = ( ( uint8_t * ) pulParam[ portOFFSET_TO_PC ] )[ -2 ];\r
 275         switch( ucSVCNumber )\r
 276         {\r
 277                 case portSVC_START_SCHEDULER    :       portNVIC_SYSPRI1_REG |= portNVIC_SVC_PRI;\r
 278                                                                                         prvRestoreContextOfFirstTask();\r
 279                                                                                         break;\r
 280 \r
 281                 case portSVC_YIELD                              :       portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;\r
 282                                                                                         /* Barriers are normally not required\r
 283                                                                                         but do ensure the code is completely\r
 284                                                                                         within the specified behaviour for the\r
 285                                                                                         architecture. */\r
 286                                                                                         __asm volatile( "dsb" );\r
 287                                                                                         __asm volatile( "isb" );\r
 288 \r
 289                                                                                         break;\r
 290 \r
 291                 case portSVC_RAISE_PRIVILEGE    :       __asm volatile\r
 292                                                                                         (\r
 293                                                                                                 "       mrs r1, control         \n" /* Obtain current control value. */\r
 294                                                                                                 "       bic r1, #1                      \n" /* Set privilege bit. */\r
 295                                                                                                 "       msr control, r1         \n" /* Write back new control value. */\r
 296                                                                                                 :::"r1"\r
 297                                                                                         );\r
 298                                                                                         break;\r
 299 \r
 300                 default                                                 :       /* Unknown SVC call. */\r
 301                                                                                         break;\r
 302         }\r
 303 }\r
 304 /*-----------------------------------------------------------*/\r
 305 \r
 306 static void prvRestoreContextOfFirstTask( void )\r
 307 {\r
 308         __asm volatile\r
 309         (\r
 310                 "       ldr r0, =0xE000ED08                             \n" /* Use the NVIC offset register to locate the stack. */\r
 311                 "       ldr r0, [r0]                                    \n"\r
 312                 "       ldr r0, [r0]                                    \n"\r
 313                 "       msr msp, r0                                             \n" /* Set the msp back to the start of the stack. */\r
 314                 "       ldr     r3, pxCurrentTCBConst2          \n" /* Restore the context. */\r
 315                 "       ldr r1, [r3]                                    \n"\r
 316                 "       ldr r0, [r1]                                    \n" /* The first item in the TCB is the task top of stack. */\r
 317                 "       add r1, r1, #4                                  \n" /* Move onto the second item in the TCB... */\r
 318                 "       ldr r2, =0xe000ed9c                             \n" /* Region Base Address register. */\r
 319                 "       ldmia r1!, {r4-r11}                             \n" /* Read 4 sets of MPU registers. */\r
 320                 "       stmia r2!, {r4-r11}                             \n" /* Write 4 sets of MPU registers. */\r
 321                 "       ldmia r0!, {r3-r11, r14}                \n" /* Pop the registers that are not automatically saved on exception entry. */\r
 322                 "       msr control, r3                                 \n"\r
 323                 "       msr psp, r0                                             \n" /* Restore the task stack pointer. */\r
 324                 "       mov r0, #0                                              \n"\r
 325                 "       msr     basepri, r0                                     \n"\r
 326                 "       bx r14                                                  \n"\r
 327                 "                                                                       \n"\r
 328                 "       .align 4                                                \n"\r
 329                 "pxCurrentTCBConst2: .word pxCurrentTCB \n"\r
 330         );\r
 331 }\r
 332 /*-----------------------------------------------------------*/\r
 333 \r
 334 /*\r
 335  * See header file for description.\r
 336  */\r
 337 BaseType_t xPortStartScheduler( void )\r
 338 {\r
 339         /* configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0.  See\r
 340         http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */\r
 341         configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) );\r
 342 \r
 343         #if( configASSERT_DEFINED == 1 )\r
 344         {\r
 345                 volatile uint32_t ulOriginalPriority;\r
 346                 volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER );\r
 347                 volatile uint8_t ucMaxPriorityValue;\r
 348 \r
 349                 /* Determine the maximum priority from which ISR safe FreeRTOS API\r
 350                 functions can be called.  ISR safe functions are those that end in\r
 351                 "FromISR".  FreeRTOS maintains separate thread and ISR API functions to\r
 352                 ensure interrupt entry is as fast and simple as possible.\r
 353 \r
 354                 Save the interrupt priority value that is about to be clobbered. */\r
 355                 ulOriginalPriority = *pucFirstUserPriorityRegister;\r
 356 \r
 357                 /* Determine the number of priority bits available.  First write to all\r
 358                 possible bits. */\r
 359                 *pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;\r
 360 \r
 361                 /* Read the value back to see how many bits stuck. */\r
 362                 ucMaxPriorityValue = *pucFirstUserPriorityRegister;\r
 363 \r
 364                 /* Use the same mask on the maximum system call priority. */\r
 365                 ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;\r
 366 \r
 367                 /* Calculate the maximum acceptable priority group value for the number\r
 368                 of bits read back. */\r
 369                 ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;\r
 370                 while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )\r
 371                 {\r
 372                         ulMaxPRIGROUPValue--;\r
 373                         ucMaxPriorityValue <<= ( uint8_t ) 0x01;\r
 374                 }\r
 375 \r
 376                 /* Shift the priority group value back to its position within the AIRCR\r
 377                 register. */\r
 378                 ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;\r
 379                 ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;\r
 380 \r
 381                 /* Restore the clobbered interrupt priority register to its original\r
 382                 value. */\r
 383                 *pucFirstUserPriorityRegister = ulOriginalPriority;\r
 384         }\r
 385         #endif /* conifgASSERT_DEFINED */\r
 386 \r
 387         /* Make PendSV and SysTick the same priority as the kernel, and the SVC\r
 388         handler higher priority so it can be used to exit a critical section (where\r
 389         lower priorities are masked). */\r
 390         portNVIC_SYSPRI2_REG |= portNVIC_PENDSV_PRI;\r
 391         portNVIC_SYSPRI2_REG |= portNVIC_SYSTICK_PRI;\r
 392 \r
 393         /* Configure the regions in the MPU that are common to all tasks. */\r
 394         prvSetupMPU();\r
 395 \r
 396         /* Start the timer that generates the tick ISR.  Interrupts are disabled\r
 397         here already. */\r
 398         prvSetupTimerInterrupt();\r
 399 \r
 400         /* Initialise the critical nesting count ready for the first task. */\r
 401         uxCriticalNesting = 0;\r
 402 \r
 403         /* Ensure the VFP is enabled - it should be anyway. */\r
 404         vPortEnableVFP();\r
 405 \r
 406         /* Lazy save always. */\r
 407         *( portFPCCR ) |= portASPEN_AND_LSPEN_BITS;\r
 408 \r
 409         /* Start the first task. */\r
 410         __asm volatile(\r
 411                                         " ldr r0, =0xE000ED08   \n" /* Use the NVIC offset register to locate the stack. */\r
 412                                         " ldr r0, [r0]                  \n"\r
 413                                         " ldr r0, [r0]                  \n"\r
 414                                         " msr msp, r0                   \n" /* Set the msp back to the start of the stack. */\r
 415                                         " cpsie i                               \n" /* Globally enable interrupts. */\r
 416                                         " cpsie f                               \n"\r
 417                                         " dsb                                   \n"\r
 418                                         " isb                                   \n"\r
 419                                         " svc %0                                \n" /* System call to start first task. */\r
 420                                         " nop                                   \n"\r
 421                                         :: "i" (portSVC_START_SCHEDULER) );\r
 422 \r
 423         /* Should not get here! */\r
 424         return 0;\r
 425 }\r
 426 /*-----------------------------------------------------------*/\r
 427 \r
 428 void vPortEndScheduler( void )\r
 429 {\r
 430         /* Not implemented in ports where there is nothing to return to.\r
 431         Artificially force an assert. */\r
 432         configASSERT( uxCriticalNesting == 1000UL );\r
 433 }\r
 434 /*-----------------------------------------------------------*/\r
 435 \r
 436 void vPortEnterCritical( void )\r
 437 {\r
 438 BaseType_t xRunningPrivileged = xPortRaisePrivilege();\r
 439 \r
 440         portDISABLE_INTERRUPTS();\r
 441         uxCriticalNesting++;\r
 442 \r
 443         vPortResetPrivilege( xRunningPrivileged );\r
 444 }\r
 445 /*-----------------------------------------------------------*/\r
 446 \r
 447 void vPortExitCritical( void )\r
 448 {\r
 449 BaseType_t xRunningPrivileged = xPortRaisePrivilege();\r
 450 \r
 451         configASSERT( uxCriticalNesting );\r
 452         uxCriticalNesting--;\r
 453         if( uxCriticalNesting == 0 )\r
 454         {\r
 455                 portENABLE_INTERRUPTS();\r
 456         }\r
 457         vPortResetPrivilege( xRunningPrivileged );\r
 458 }\r
 459 /*-----------------------------------------------------------*/\r
 460 \r
 461 void xPortPendSVHandler( void )\r
 462 {\r
 463         /* This is a naked function. */\r
 464 \r
 465         __asm volatile\r
 466         (\r
 467                 "       mrs r0, psp                                                     \n"\r
 468                 "                                                                               \n"\r
 469                 "       ldr     r3, pxCurrentTCBConst                   \n" /* Get the location of the current TCB. */\r
 470                 "       ldr     r2, [r3]                                                \n"\r
 471                 "                                                                               \n"\r
 472                 "       tst r14, #0x10                                          \n" /* Is the task using the FPU context?  If so, push high vfp registers. */\r
 473                 "       it eq                                                           \n"\r
 474                 "       vstmdbeq r0!, {s16-s31}                         \n"\r
 475                 "                                                                               \n"\r
 476                 "       mrs r1, control                                         \n"\r
 477                 "       stmdb r0!, {r1, r4-r11, r14}            \n" /* Save the remaining registers. */\r
 478                 "       str r0, [r2]                                            \n" /* Save the new top of stack into the first member of the TCB. */\r
 479                 "                                                                               \n"\r
 480                 "       stmdb sp!, {r3}                                         \n"\r
 481                 "       mov r0, %0                                                      \n"\r
 482                 "       msr basepri, r0                                         \n"\r
 483                 "       dsb                                                                     \n"\r
 484                 "       isb                                                                     \n"\r
 485                 "       bl vTaskSwitchContext                           \n"\r
 486                 "       mov r0, #0                                                      \n"\r
 487                 "       msr basepri, r0                                         \n"\r
 488                 "       ldmia sp!, {r3}                                         \n"\r
 489                 "                                                                               \n"     /* Restore the context. */\r
 490                 "       ldr r1, [r3]                                            \n"\r
 491                 "       ldr r0, [r1]                                            \n" /* The first item in the TCB is the task top of stack. */\r
 492                 "       add r1, r1, #4                                          \n" /* Move onto the second item in the TCB... */\r
 493                 "       ldr r2, =0xe000ed9c                                     \n" /* Region Base Address register. */\r
 494                 "       ldmia r1!, {r4-r11}                                     \n" /* Read 4 sets of MPU registers. */\r
 495                 "       stmia r2!, {r4-r11}                                     \n" /* Write 4 sets of MPU registers. */\r
 496                 "       ldmia r0!, {r3-r11, r14}                        \n" /* Pop the registers that are not automatically saved on exception entry. */\r
 497                 "       msr control, r3                                         \n"\r
 498                 "                                                                               \n"\r
 499                 "       tst r14, #0x10                                          \n" /* Is the task using the FPU context?  If so, pop the high vfp registers too. */\r
 500                 "       it eq                                                           \n"\r
 501                 "       vldmiaeq r0!, {s16-s31}                         \n"\r
 502                 "                                                                               \n"\r
 503                 "       msr psp, r0                                                     \n"\r
 504                 "       bx r14                                                          \n"\r
 505                 "                                                                               \n"\r
 506                 "       .align 4                                                        \n"\r
 507                 "pxCurrentTCBConst: .word pxCurrentTCB  \n"\r
 508                 ::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY)\r
 509         );\r
 510 }\r
 511 /*-----------------------------------------------------------*/\r
 512 \r
 513 void xPortSysTickHandler( void )\r
 514 {\r
 515 uint32_t ulDummy;\r
 516 \r
 517         ulDummy = portSET_INTERRUPT_MASK_FROM_ISR();\r
 518         {\r
 519                 /* Increment the RTOS tick. */\r
 520                 if( xTaskIncrementTick() != pdFALSE )\r
 521                 {\r
 522                         /* Pend a context switch. */\r
 523                         portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;\r
 524                 }\r
 525         }\r
 526         portCLEAR_INTERRUPT_MASK_FROM_ISR( ulDummy );\r
 527 }\r
 528 /*-----------------------------------------------------------*/\r
 529 \r
 530 /*\r
 531  * Setup the systick timer to generate the tick interrupts at the required\r
 532  * frequency.\r
 533  */\r
 534 static void prvSetupTimerInterrupt( void )\r
 535 {\r
 536         /* Configure SysTick to interrupt at the requested rate. */\r
 537         portNVIC_SYSTICK_LOAD_REG = ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;\r
 538         portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK | portNVIC_SYSTICK_INT | portNVIC_SYSTICK_ENABLE;\r
 539 }\r
 540 /*-----------------------------------------------------------*/\r
 541 \r
 542 /* This is a naked function. */\r
 543 static void vPortEnableVFP( void )\r
 544 {\r
 545         __asm volatile\r
 546         (\r
 547                 "       ldr.w r0, =0xE000ED88           \n" /* The FPU enable bits are in the CPACR. */\r
 548                 "       ldr r1, [r0]                            \n"\r
 549                 "                                                               \n"\r
 550                 "       orr r1, r1, #( 0xf << 20 )      \n" /* Enable CP10 and CP11 coprocessors, then save back. */\r
 551                 "       str r1, [r0]                            \n"\r
 552                 "       bx r14                                          "\r
 553         );\r
 554 }\r
 555 /*-----------------------------------------------------------*/\r
 556 \r
 557 static void prvSetupMPU( void )\r
 558 {\r
 559 extern uint32_t __privileged_functions_end__[];\r
 560 extern uint32_t __FLASH_segment_start__[];\r
 561 extern uint32_t __FLASH_segment_end__[];\r
 562 extern uint32_t __privileged_data_start__[];\r
 563 extern uint32_t __privileged_data_end__[];\r
 564 \r
 565         /* Check the expected MPU is present. */\r
 566         if( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE )\r
 567         {\r
 568                 /* First setup the entire flash for unprivileged read only access. */\r
 569                 portMPU_REGION_BASE_ADDRESS_REG =       ( ( uint32_t ) __FLASH_segment_start__ ) | /* Base address. */\r
 570                                                                                         ( portMPU_REGION_VALID ) |\r
 571                                                                                         ( portUNPRIVILEGED_FLASH_REGION );\r
 572 \r
 573                 portMPU_REGION_ATTRIBUTE_REG =  ( portMPU_REGION_READ_ONLY ) |\r
 574                                                                                 ( portMPU_REGION_CACHEABLE_BUFFERABLE ) |\r
 575                                                                                 ( prvGetMPURegionSizeSetting( ( uint32_t ) __FLASH_segment_end__ - ( uint32_t ) __FLASH_segment_start__ ) ) |\r
 576                                                                                 ( portMPU_REGION_ENABLE );\r
 577 \r
 578                 /* Setup the first 16K for privileged only access (even though less\r
 579                 than 10K is actually being used).  This is where the kernel code is\r
 580                 placed. */\r
 581                 portMPU_REGION_BASE_ADDRESS_REG =       ( ( uint32_t ) __FLASH_segment_start__ ) | /* Base address. */\r
 582                                                                                         ( portMPU_REGION_VALID ) |\r
 583                                                                                         ( portPRIVILEGED_FLASH_REGION );\r
 584 \r
 585                 portMPU_REGION_ATTRIBUTE_REG =  ( portMPU_REGION_PRIVILEGED_READ_ONLY ) |\r
 586                                                                                 ( portMPU_REGION_CACHEABLE_BUFFERABLE ) |\r
 587                                                                                 ( prvGetMPURegionSizeSetting( ( uint32_t ) __privileged_functions_end__ - ( uint32_t ) __FLASH_segment_start__ ) ) |\r
 588                                                                                 ( portMPU_REGION_ENABLE );\r
 589 \r
 590                 /* Setup the privileged data RAM region.  This is where the kernel data\r
 591                 is placed. */\r
 592                 portMPU_REGION_BASE_ADDRESS_REG =       ( ( uint32_t ) __privileged_data_start__ ) | /* Base address. */\r
 593                                                                                         ( portMPU_REGION_VALID ) |\r
 594                                                                                         ( portPRIVILEGED_RAM_REGION );\r
 595 \r
 596                 portMPU_REGION_ATTRIBUTE_REG =  ( portMPU_REGION_PRIVILEGED_READ_WRITE ) |\r
 597                                                                                 ( portMPU_REGION_CACHEABLE_BUFFERABLE ) |\r
 598                                                                                 prvGetMPURegionSizeSetting( ( uint32_t ) __privileged_data_end__ - ( uint32_t ) __privileged_data_start__ ) |\r
 599                                                                                 ( portMPU_REGION_ENABLE );\r
 600 \r
 601                 /* By default allow everything to access the general peripherals.  The\r
 602                 system peripherals and registers are protected. */\r
 603                 portMPU_REGION_BASE_ADDRESS_REG =       ( portPERIPHERALS_START_ADDRESS ) |\r
 604                                                                                         ( portMPU_REGION_VALID ) |\r
 605                                                                                         ( portGENERAL_PERIPHERALS_REGION );\r
 606 \r
 607                 portMPU_REGION_ATTRIBUTE_REG =  ( portMPU_REGION_READ_WRITE | portMPU_REGION_EXECUTE_NEVER ) |\r
 608                                                                                 ( prvGetMPURegionSizeSetting( portPERIPHERALS_END_ADDRESS - portPERIPHERALS_START_ADDRESS ) ) |\r
 609                                                                                 ( portMPU_REGION_ENABLE );\r
 610 \r
 611                 /* Enable the memory fault exception. */\r
 612                 portNVIC_SYS_CTRL_STATE_REG |= portNVIC_MEM_FAULT_ENABLE;\r
 613 \r
 614                 /* Enable the MPU with the background region configured. */\r
 615                 portMPU_CTRL_REG |= ( portMPU_ENABLE | portMPU_BACKGROUND_ENABLE );\r
 616         }\r
 617 }\r
 618 /*-----------------------------------------------------------*/\r
 619 \r
 620 static uint32_t prvGetMPURegionSizeSetting( uint32_t ulActualSizeInBytes )\r
 621 {\r
 622 uint32_t ulRegionSize, ulReturnValue = 4;\r
 623 \r
 624         /* 32 is the smallest region size, 31 is the largest valid value for\r
 625         ulReturnValue. */\r
 626         for( ulRegionSize = 32UL; ulReturnValue < 31UL; ( ulRegionSize <<= 1UL ) )\r
 627         {\r
 628                 if( ulActualSizeInBytes <= ulRegionSize )\r
 629                 {\r
 630                         break;\r
 631                 }\r
 632                 else\r
 633                 {\r
 634                         ulReturnValue++;\r
 635                 }\r
 636         }\r
 637 \r
 638         /* Shift the code by one before returning so it can be written directly\r
 639         into the the correct bit position of the attribute register. */\r
 640         return ( ulReturnValue << 1UL );\r
 641 }\r
 642 /*-----------------------------------------------------------*/\r
 643 \r
 644 BaseType_t xPortRaisePrivilege( void )\r
 645 {\r
 646         __asm volatile\r
 647         (\r
 648                 "       mrs r0, control                                         \n"\r
 649                 "       tst r0, #1                                                      \n" /* Is the task running privileged? */\r
 650                 "       itte ne                                                         \n"\r
 651                 "       movne r0, #0                                            \n" /* CONTROL[0]!=0, return false. */\r
 652                 "       svcne %0                                                        \n" /* Switch to privileged. */\r
 653                 "       moveq r0, #1                                            \n" /* CONTROL[0]==0, return true. */\r
 654                 "       bx lr                                                           \n"\r
 655                 :: "i" (portSVC_RAISE_PRIVILEGE) : "r0"\r
 656         );\r
 657 \r
 658         return 0;\r
 659 }\r
 660 /*-----------------------------------------------------------*/\r
 661 \r
 662 void vPortStoreTaskMPUSettings( xMPU_SETTINGS *xMPUSettings, const struct xMEMORY_REGION * const xRegions, StackType_t *pxBottomOfStack, uint32_t ulStackDepth )\r
 663 {\r
 664 extern uint32_t __SRAM_segment_start__[];\r
 665 extern uint32_t __SRAM_segment_end__[];\r
 666 extern uint32_t __privileged_data_start__[];\r
 667 extern uint32_t __privileged_data_end__[];\r
 668 int32_t lIndex;\r
 669 uint32_t ul;\r
 670 \r
 671         if( xRegions == NULL )\r
 672         {\r
 673                 /* No MPU regions are specified so allow access to all RAM. */\r
 674                 xMPUSettings->xRegion[ 0 ].ulRegionBaseAddress =\r
 675                                 ( ( uint32_t ) __SRAM_segment_start__ ) | /* Base address. */\r
 676                                 ( portMPU_REGION_VALID ) |\r
 677                                 ( portSTACK_REGION );\r
 678 \r
 679                 xMPUSettings->xRegion[ 0 ].ulRegionAttribute =\r
 680                                 ( portMPU_REGION_READ_WRITE ) |\r
 681                                 ( portMPU_REGION_CACHEABLE_BUFFERABLE ) |\r
 682                                 ( prvGetMPURegionSizeSetting( ( uint32_t ) __SRAM_segment_end__ - ( uint32_t ) __SRAM_segment_start__ ) ) |\r
 683                                 ( portMPU_REGION_ENABLE );\r
 684 \r
 685                 /* Re-instate the privileged only RAM region as xRegion[ 0 ] will have\r
 686                 just removed the privileged only parameters. */\r
 687                 xMPUSettings->xRegion[ 1 ].ulRegionBaseAddress =\r
 688                                 ( ( uint32_t ) __privileged_data_start__ ) | /* Base address. */\r
 689                                 ( portMPU_REGION_VALID ) |\r
 690                                 ( portSTACK_REGION + 1 );\r
 691 \r
 692                 xMPUSettings->xRegion[ 1 ].ulRegionAttribute =\r
 693                                 ( portMPU_REGION_PRIVILEGED_READ_WRITE ) |\r
 694                                 ( portMPU_REGION_CACHEABLE_BUFFERABLE ) |\r
 695                                 prvGetMPURegionSizeSetting( ( uint32_t ) __privileged_data_end__ - ( uint32_t ) __privileged_data_start__ ) |\r
 696                                 ( portMPU_REGION_ENABLE );\r
 697 \r
 698                 /* Invalidate all other regions. */\r
 699                 for( ul = 2; ul <= portNUM_CONFIGURABLE_REGIONS; ul++ )\r
 700                 {\r
 701                         xMPUSettings->xRegion[ ul ].ulRegionBaseAddress = ( portSTACK_REGION + ul ) | portMPU_REGION_VALID;\r
 702                         xMPUSettings->xRegion[ ul ].ulRegionAttribute = 0UL;\r
 703                 }\r
 704         }\r
 705         else\r
 706         {\r
 707                 /* This function is called automatically when the task is created - in\r
 708                 which case the stack region parameters will be valid.  At all other\r
 709                 times the stack parameters will not be valid and it is assumed that the\r
 710                 stack region has already been configured. */\r
 711                 if( ulStackDepth > 0 )\r
 712                 {\r
 713                         /* Define the region that allows access to the stack. */\r
 714                         xMPUSettings->xRegion[ 0 ].ulRegionBaseAddress =\r
 715                                         ( ( uint32_t ) pxBottomOfStack ) |\r
 716                                         ( portMPU_REGION_VALID ) |\r
 717                                         ( portSTACK_REGION ); /* Region number. */\r
 718 \r
 719                         xMPUSettings->xRegion[ 0 ].ulRegionAttribute =\r
 720                                         ( portMPU_REGION_READ_WRITE ) | /* Read and write. */\r
 721                                         ( prvGetMPURegionSizeSetting( ulStackDepth * ( uint32_t ) sizeof( StackType_t ) ) ) |\r
 722                                         ( portMPU_REGION_CACHEABLE_BUFFERABLE ) |\r
 723                                         ( portMPU_REGION_ENABLE );\r
 724                 }\r
 725 \r
 726                 lIndex = 0;\r
 727 \r
 728                 for( ul = 1; ul <= portNUM_CONFIGURABLE_REGIONS; ul++ )\r
 729                 {\r
 730                         if( ( xRegions[ lIndex ] ).ulLengthInBytes > 0UL )\r
 731                         {\r
 732                                 /* Translate the generic region definition contained in\r
 733                                 xRegions into the CM3 specific MPU settings that are then\r
 734                                 stored in xMPUSettings. */\r
 735                                 xMPUSettings->xRegion[ ul ].ulRegionBaseAddress =\r
 736                                                 ( ( uint32_t ) xRegions[ lIndex ].pvBaseAddress ) |\r
 737                                                 ( portMPU_REGION_VALID ) |\r
 738                                                 ( portSTACK_REGION + ul ); /* Region number. */\r
 739 \r
 740                                 xMPUSettings->xRegion[ ul ].ulRegionAttribute =\r
 741                                                 ( prvGetMPURegionSizeSetting( xRegions[ lIndex ].ulLengthInBytes ) ) |\r
 742                                                 ( xRegions[ lIndex ].ulParameters ) |\r
 743                                                 ( portMPU_REGION_ENABLE );\r
 744                         }\r
 745                         else\r
 746                         {\r
 747                                 /* Invalidate the region. */\r
 748                                 xMPUSettings->xRegion[ ul ].ulRegionBaseAddress = ( portSTACK_REGION + ul ) | portMPU_REGION_VALID;\r
 749                                 xMPUSettings->xRegion[ ul ].ulRegionAttribute = 0UL;\r
 750                         }\r
 751 \r
 752                         lIndex++;\r
 753                 }\r
 754         }\r
 755 }\r
 756 /*-----------------------------------------------------------*/\r
 757 \r
 758 #if( configASSERT_DEFINED == 1 )\r
 759 \r
 760         void vPortValidateInterruptPriority( void )\r
 761         {\r
 762         uint32_t ulCurrentInterrupt;\r
 763         uint8_t ucCurrentPriority;\r
 764 \r
 765                 /* Obtain the number of the currently executing interrupt. */\r
 766                 __asm volatile( "mrs %0, ipsr" : "=r"( ulCurrentInterrupt ) );\r
 767 \r
 768                 /* Is the interrupt number a user defined interrupt? */\r
 769                 if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER )\r
 770                 {\r
 771                         /* Look up the interrupt's priority. */\r
 772                         ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ];\r
 773 \r
 774                         /* The following assertion will fail if a service routine (ISR) for\r
 775                         an interrupt that has been assigned a priority above\r
 776                         configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API\r
 777                         function.  ISR safe FreeRTOS API functions must *only* be called\r
 778                         from interrupts that have been assigned a priority at or below\r
 779                         configMAX_SYSCALL_INTERRUPT_PRIORITY.\r
 780 \r
 781                         Numerically low interrupt priority numbers represent logically high\r
 782                         interrupt priorities, therefore the priority of the interrupt must\r
 783                         be set to a value equal to or numerically *higher* than\r
 784                         configMAX_SYSCALL_INTERRUPT_PRIORITY.\r
 785 \r
 786                         Interrupts that use the FreeRTOS API must not be left at their\r
 787                         default priority of     zero as that is the highest possible priority,\r
 788                         which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY,\r
 789                         and     therefore also guaranteed to be invalid.\r
 790 \r
 791                         FreeRTOS maintains separate thread and ISR API functions to ensure\r
 792                         interrupt entry is as fast and simple as possible.\r
 793 \r
 794                         The following links provide detailed information:\r
 795                         http://www.freertos.org/RTOS-Cortex-M3-M4.html\r
 796                         http://www.freertos.org/FAQHelp.html */\r
 797                         configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );\r
 798                 }\r
 799 \r
 800                 /* Priority grouping:  The interrupt controller (NVIC) allows the bits\r
 801                 that define each interrupt's priority to be split between bits that\r
 802                 define the interrupt's pre-emption priority bits and bits that define\r
 803                 the interrupt's sub-priority.  For simplicity all bits must be defined\r
 804                 to be pre-emption priority bits.  The following assertion will fail if\r
 805                 this is not the case (if some bits represent a sub-priority).\r
 806 \r
 807                 If the application only uses CMSIS libraries for interrupt\r
 808                 configuration then the correct setting can be achieved on all Cortex-M\r
 809                 devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the\r
 810                 scheduler.  Note however that some vendor specific peripheral libraries\r
 811                 assume a non-zero priority group setting, in which cases using a value\r
 812                 of zero will result in unpredicable behaviour. */\r
 813                 configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );\r
 814         }\r
 815 \r
 816 #endif /* configASSERT_DEFINED */\r
 817 /*-----------------------------------------------------------*/\r
 818 \r
 819 \r