git.sur5r.net Git - freertos/blob - FreeRTOS/Source/portable/GCC/ARM_CM4_MPU/port.c

   1 /*\r
   2  * FreeRTOS Kernel V10.2.1\r
   3  * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\r
   4  *\r
   5  * Permission is hereby granted, free of charge, to any person obtaining a copy of\r
   6  * this software and associated documentation files (the "Software"), to deal in\r
   7  * the Software without restriction, including without limitation the rights to\r
   8  * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\r
   9  * the Software, and to permit persons to whom the Software is furnished to do so,\r
  10  * subject to the following conditions:\r
  11  *\r
  12  * The above copyright notice and this permission notice shall be included in all\r
  13  * copies or substantial portions of the Software.\r
  14  *\r
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\r
  17  * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\r
  18  * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r
  19  * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
  20  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
  21  *\r
  22  * http://www.FreeRTOS.org\r
  23  * http://aws.amazon.com/freertos\r
  24  *\r
  25  * 1 tab == 4 spaces!\r
  26  */\r
  27 \r
  28 /*-----------------------------------------------------------\r
  29  * Implementation of functions defined in portable.h for the ARM CM3 port.\r
  30  *----------------------------------------------------------*/\r
  31 \r
  32 /* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining\r
  33 all the API functions to use the MPU wrappers.  That should only be done when\r
  34 task.h is included from an application file. */\r
  35 #define MPU_WRAPPERS_INCLUDED_FROM_API_FILE\r
  36 \r
  37 /* Scheduler includes. */\r
  38 #include "FreeRTOS.h"\r
  39 #include "task.h"\r
  40 \r
  41 #ifndef __VFP_FP__\r
  42         #error This port can only be used when the project options are configured to enable hardware floating point support.\r
  43 #endif\r
  44 \r
  45 #undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE\r
  46 \r
  47 #ifndef configSYSTICK_CLOCK_HZ\r
  48         #define configSYSTICK_CLOCK_HZ configCPU_CLOCK_HZ\r
  49         /* Ensure the SysTick is clocked at the same frequency as the core. */\r
  50         #define portNVIC_SYSTICK_CLK    ( 1UL << 2UL )\r
  51 #else\r
  52         /* The way the SysTick is clocked is not modified in case it is not the same\r
  53         as the core. */\r
  54         #define portNVIC_SYSTICK_CLK    ( 0 )\r
  55 #endif\r
  56 \r
  57 /* Constants required to access and manipulate the NVIC. */\r
  58 #define portNVIC_SYSTICK_CTRL_REG                               ( * ( ( volatile uint32_t * ) 0xe000e010 ) )\r
  59 #define portNVIC_SYSTICK_LOAD_REG                               ( * ( ( volatile uint32_t * ) 0xe000e014 ) )\r
  60 #define portNVIC_SYSTICK_CURRENT_VALUE_REG              ( * ( ( volatile uint32_t * ) 0xe000e018 ) )\r
  61 #define portNVIC_SYSPRI2_REG                                    ( *     ( ( volatile uint32_t * ) 0xe000ed20 ) )\r
  62 #define portNVIC_SYSPRI1_REG                                    ( * ( ( volatile uint32_t * ) 0xe000ed1c ) )\r
  63 #define portNVIC_SYS_CTRL_STATE_REG                             ( * ( ( volatile uint32_t * ) 0xe000ed24 ) )\r
  64 #define portNVIC_MEM_FAULT_ENABLE                               ( 1UL << 16UL )\r
  65 \r
  66 /* Constants required to access and manipulate the MPU. */\r
  67 #define portMPU_TYPE_REG                                                ( * ( ( volatile uint32_t * ) 0xe000ed90 ) )\r
  68 #define portMPU_REGION_BASE_ADDRESS_REG                 ( * ( ( volatile uint32_t * ) 0xe000ed9C ) )\r
  69 #define portMPU_REGION_ATTRIBUTE_REG                    ( * ( ( volatile uint32_t * ) 0xe000edA0 ) )\r
  70 #define portMPU_CTRL_REG                                                ( * ( ( volatile uint32_t * ) 0xe000ed94 ) )\r
  71 #define portEXPECTED_MPU_TYPE_VALUE                             ( 8UL << 8UL ) /* 8 regions, unified. */\r
  72 #define portMPU_ENABLE                                                  ( 0x01UL )\r
  73 #define portMPU_BACKGROUND_ENABLE                               ( 1UL << 2UL )\r
  74 #define portPRIVILEGED_EXECUTION_START_ADDRESS  ( 0UL )\r
  75 #define portMPU_REGION_VALID                                    ( 0x10UL )\r
  76 #define portMPU_REGION_ENABLE                                   ( 0x01UL )\r
  77 #define portPERIPHERALS_START_ADDRESS                   0x40000000UL\r
  78 #define portPERIPHERALS_END_ADDRESS                             0x5FFFFFFFUL\r
  79 \r
  80 /* Constants required to access and manipulate the SysTick. */\r
  81 #define portNVIC_SYSTICK_INT                                    ( 0x00000002UL )\r
  82 #define portNVIC_SYSTICK_ENABLE                                 ( 0x00000001UL )\r
  83 #define portNVIC_PENDSV_PRI                                             ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL )\r
  84 #define portNVIC_SYSTICK_PRI                                    ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL )\r
  85 #define portNVIC_SVC_PRI                                                ( ( ( uint32_t ) configMAX_SYSCALL_INTERRUPT_PRIORITY - 1UL ) << 24UL )\r
  86 \r
  87 /* Constants required to manipulate the VFP. */\r
  88 #define portFPCCR                                                               ( ( volatile uint32_t * ) 0xe000ef34UL ) /* Floating point context control register. */\r
  89 #define portASPEN_AND_LSPEN_BITS                                ( 0x3UL << 30UL )\r
  90 \r
  91 /* Constants required to set up the initial stack. */\r
  92 #define portINITIAL_XPSR                                                ( 0x01000000UL )\r
  93 #define portINITIAL_EXC_RETURN                                  ( 0xfffffffdUL )\r
  94 #define portINITIAL_CONTROL_IF_UNPRIVILEGED             ( 0x03 )\r
  95 #define portINITIAL_CONTROL_IF_PRIVILEGED               ( 0x02 )\r
  96 \r
  97 /* Constants required to check the validity of an interrupt priority. */\r
  98 #define portFIRST_USER_INTERRUPT_NUMBER         ( 16 )\r
  99 #define portNVIC_IP_REGISTERS_OFFSET_16         ( 0xE000E3F0 )\r
 100 #define portAIRCR_REG                                           ( * ( ( volatile uint32_t * ) 0xE000ED0C ) )\r
 101 #define portMAX_8_BIT_VALUE                                     ( ( uint8_t ) 0xff )\r
 102 #define portTOP_BIT_OF_BYTE                                     ( ( uint8_t ) 0x80 )\r
 103 #define portMAX_PRIGROUP_BITS                           ( ( uint8_t ) 7 )\r
 104 #define portPRIORITY_GROUP_MASK                         ( 0x07UL << 8UL )\r
 105 #define portPRIGROUP_SHIFT                                      ( 8UL )\r
 106 \r
 107 /* Offsets in the stack to the parameters when inside the SVC handler. */\r
 108 #define portOFFSET_TO_PC                                                ( 6 )\r
 109 \r
 110 /* For strict compliance with the Cortex-M spec the task start address should\r
 111 have bit-0 clear, as it is loaded into the PC on exit from an ISR. */\r
 112 #define portSTART_ADDRESS_MASK                          ( ( StackType_t ) 0xfffffffeUL )\r
 113 \r
 114 /*\r
 115  * Configure a number of standard MPU regions that are used by all tasks.\r
 116  */\r
 117 static void prvSetupMPU( void ) PRIVILEGED_FUNCTION;\r
 118 \r
 119 /*\r
 120  * Return the smallest MPU region size that a given number of bytes will fit\r
 121  * into.  The region size is returned as the value that should be programmed\r
 122  * into the region attribute register for that region.\r
 123  */\r
 124 static uint32_t prvGetMPURegionSizeSetting( uint32_t ulActualSizeInBytes ) PRIVILEGED_FUNCTION;\r
 125 \r
 126 /*\r
 127  * Setup the timer to generate the tick interrupts.  The implementation in this\r
 128  * file is weak to allow application writers to change the timer used to\r
 129  * generate the tick interrupt.\r
 130  */\r
 131 void vPortSetupTimerInterrupt( void );\r
 132 \r
 133 /*\r
 134  * Standard FreeRTOS exception handlers.\r
 135  */\r
 136 void xPortPendSVHandler( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;\r
 137 void xPortSysTickHandler( void )  __attribute__ ((optimize("3"))) PRIVILEGED_FUNCTION;\r
 138 void vPortSVCHandler( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;\r
 139 \r
 140 /*\r
 141  * Starts the scheduler by restoring the context of the first task to run.\r
 142  */\r
 143 static void prvRestoreContextOfFirstTask( void ) __attribute__(( naked )) PRIVILEGED_FUNCTION;\r
 144 \r
 145 /*\r
 146  * C portion of the SVC handler.  The SVC handler is split between an asm entry\r
 147  * and a C wrapper for simplicity of coding and maintenance.\r
 148  */\r
 149 static void prvSVCHandler( uint32_t *pulRegisters ) __attribute__(( noinline )) PRIVILEGED_FUNCTION;\r
 150 \r
 151 /*\r
 152  * Function to enable the VFP.\r
 153  */\r
 154  static void vPortEnableVFP( void ) __attribute__ (( naked ));\r
 155 \r
 156 /**\r
 157  * @brief Checks whether or not the processor is privileged.\r
 158  *\r
 159  * @return 1 if the processor is already privileged, 0 otherwise.\r
 160  */\r
 161 BaseType_t xIsPrivileged( void ) __attribute__ (( naked ));\r
 162 \r
 163 /**\r
 164  * @brief Lowers the privilege level by setting the bit 0 of the CONTROL\r
 165  * register.\r
 166  *\r
 167  * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.\r
 168  *  Bit[0] = 0 --> The processor is running privileged\r
 169  *  Bit[0] = 1 --> The processor is running unprivileged.\r
 170  */\r
 171 void vResetPrivilege( void ) __attribute__ (( naked ));\r
 172 \r
 173 /**\r
 174  * @brief Calls the port specific code to raise the privilege.\r
 175  *\r
 176  * @return pdFALSE if privilege was raised, pdTRUE otherwise.\r
 177  */\r
 178 extern BaseType_t xPortRaisePrivilege( void );\r
 179 \r
 180 /**\r
 181  * @brief If xRunningPrivileged is not pdTRUE, calls the port specific\r
 182  * code to reset the privilege, otherwise does nothing.\r
 183  */\r
 184 extern void vPortResetPrivilege( BaseType_t xRunningPrivileged );\r
 185 /*-----------------------------------------------------------*/\r
 186 \r
 187 /* Each task maintains its own interrupt status in the critical nesting\r
 188 variable.  Note this is not saved as part of the task context as context\r
 189 switches can only occur when uxCriticalNesting is zero. */\r
 190 static UBaseType_t uxCriticalNesting = 0xaaaaaaaa;\r
 191 \r
 192 /*\r
 193  * Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure\r
 194  * FreeRTOS API functions are not called from interrupts that have been assigned\r
 195  * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY.\r
 196  */\r
 197 #if ( configASSERT_DEFINED == 1 )\r
 198          static uint8_t ucMaxSysCallPriority = 0;\r
 199          static uint32_t ulMaxPRIGROUPValue = 0;\r
 200          static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const volatile uint8_t * const ) portNVIC_IP_REGISTERS_OFFSET_16;\r
 201 #endif /* configASSERT_DEFINED */\r
 202 \r
 203 /*-----------------------------------------------------------*/\r
 204 \r
 205 /*\r
 206  * See header file for description.\r
 207  */\r
 208 StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters, BaseType_t xRunPrivileged )\r
 209 {\r
 210         /* Simulate the stack frame as it would be created by a context switch\r
 211         interrupt. */\r
 212         pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */\r
 213         *pxTopOfStack = portINITIAL_XPSR;       /* xPSR */\r
 214         pxTopOfStack--;\r
 215         *pxTopOfStack = ( ( StackType_t ) pxCode ) & portSTART_ADDRESS_MASK;    /* PC */\r
 216         pxTopOfStack--;\r
 217         *pxTopOfStack = 0;      /* LR */\r
 218         pxTopOfStack -= 5;      /* R12, R3, R2 and R1. */\r
 219         *pxTopOfStack = ( StackType_t ) pvParameters;   /* R0 */\r
 220 \r
 221         /* A save method is being used that requires each task to maintain its\r
 222         own exec return value. */\r
 223         pxTopOfStack--;\r
 224         *pxTopOfStack = portINITIAL_EXC_RETURN;\r
 225 \r
 226         pxTopOfStack -= 9;      /* R11, R10, R9, R8, R7, R6, R5 and R4. */\r
 227 \r
 228         if( xRunPrivileged == pdTRUE )\r
 229         {\r
 230                 *pxTopOfStack = portINITIAL_CONTROL_IF_PRIVILEGED;\r
 231         }\r
 232         else\r
 233         {\r
 234                 *pxTopOfStack = portINITIAL_CONTROL_IF_UNPRIVILEGED;\r
 235         }\r
 236 \r
 237         return pxTopOfStack;\r
 238 }\r
 239 /*-----------------------------------------------------------*/\r
 240 \r
 241 void vPortSVCHandler( void )\r
 242 {\r
 243         /* Assumes psp was in use. */\r
 244         __asm volatile\r
 245         (\r
 246                 #ifndef USE_PROCESS_STACK       /* Code should not be required if a main() is using the process stack. */\r
 247                         "       tst lr, #4                                              \n"\r
 248                         "       ite eq                                                  \n"\r
 249                         "       mrseq r0, msp                                   \n"\r
 250                         "       mrsne r0, psp                                   \n"\r
 251                 #else\r
 252                         "       mrs r0, psp                                             \n"\r
 253                 #endif\r
 254                         "       b %0                                                    \n"\r
 255                         ::"i"(prvSVCHandler):"r0", "memory"\r
 256         );\r
 257 }\r
 258 /*-----------------------------------------------------------*/\r
 259 \r
 260 static void prvSVCHandler(      uint32_t *pulParam )\r
 261 {\r
 262 uint8_t ucSVCNumber;\r
 263 \r
 264         /* The stack contains: r0, r1, r2, r3, r12, r14, the return address and\r
 265         xPSR.  The first argument (r0) is pulParam[ 0 ]. */\r
 266         ucSVCNumber = ( ( uint8_t * ) pulParam[ portOFFSET_TO_PC ] )[ -2 ];\r
 267         switch( ucSVCNumber )\r
 268         {\r
 269                 case portSVC_START_SCHEDULER    :       portNVIC_SYSPRI1_REG |= portNVIC_SVC_PRI;\r
 270                                                                                         prvRestoreContextOfFirstTask();\r
 271                                                                                         break;\r
 272 \r
 273                 case portSVC_YIELD                              :       portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;\r
 274                                                                                         /* Barriers are normally not required\r
 275                                                                                         but do ensure the code is completely\r
 276                                                                                         within the specified behaviour for the\r
 277                                                                                         architecture. */\r
 278                                                                                         __asm volatile( "dsb" ::: "memory" );\r
 279                                                                                         __asm volatile( "isb" );\r
 280 \r
 281                                                                                         break;\r
 282 \r
 283                 case portSVC_RAISE_PRIVILEGE    :       __asm volatile\r
 284                                                                                         (\r
 285                                                                                                 "       mrs r1, control         \n" /* Obtain current control value. */\r
 286                                                                                                 "       bic r1, #1                      \n" /* Set privilege bit. */\r
 287                                                                                                 "       msr control, r1         \n" /* Write back new control value. */\r
 288                                                                                                 ::: "r1", "memory"\r
 289                                                                                         );\r
 290                                                                                         break;\r
 291 \r
 292                 default                                                 :       /* Unknown SVC call. */\r
 293                                                                                         break;\r
 294         }\r
 295 }\r
 296 /*-----------------------------------------------------------*/\r
 297 \r
 298 static void prvRestoreContextOfFirstTask( void )\r
 299 {\r
 300         __asm volatile\r
 301         (\r
 302                 "       ldr r0, =0xE000ED08                             \n" /* Use the NVIC offset register to locate the stack. */\r
 303                 "       ldr r0, [r0]                                    \n"\r
 304                 "       ldr r0, [r0]                                    \n"\r
 305                 "       msr msp, r0                                             \n" /* Set the msp back to the start of the stack. */\r
 306                 "       ldr     r3, pxCurrentTCBConst2          \n" /* Restore the context. */\r
 307                 "       ldr r1, [r3]                                    \n"\r
 308                 "       ldr r0, [r1]                                    \n" /* The first item in the TCB is the task top of stack. */\r
 309                 "       add r1, r1, #4                                  \n" /* Move onto the second item in the TCB... */\r
 310                 "       ldr r2, =0xe000ed9c                             \n" /* Region Base Address register. */\r
 311                 "       ldmia r1!, {r4-r11}                             \n" /* Read 4 sets of MPU registers. */\r
 312                 "       stmia r2!, {r4-r11}                             \n" /* Write 4 sets of MPU registers. */\r
 313                 "       ldmia r0!, {r3-r11, r14}                \n" /* Pop the registers that are not automatically saved on exception entry. */\r
 314                 "       msr control, r3                                 \n"\r
 315                 "       msr psp, r0                                             \n" /* Restore the task stack pointer. */\r
 316                 "       mov r0, #0                                              \n"\r
 317                 "       msr     basepri, r0                                     \n"\r
 318                 "       bx r14                                                  \n"\r
 319                 "                                                                       \n"\r
 320                 "       .align 4                                                \n"\r
 321                 "pxCurrentTCBConst2: .word pxCurrentTCB \n"\r
 322         );\r
 323 }\r
 324 /*-----------------------------------------------------------*/\r
 325 \r
 326 /*\r
 327  * See header file for description.\r
 328  */\r
 329 BaseType_t xPortStartScheduler( void )\r
 330 {\r
 331         /* configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0.  See\r
 332         http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */\r
 333         configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) );\r
 334 \r
 335         #if( configASSERT_DEFINED == 1 )\r
 336         {\r
 337                 volatile uint32_t ulOriginalPriority;\r
 338                 volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER );\r
 339                 volatile uint8_t ucMaxPriorityValue;\r
 340 \r
 341                 /* Determine the maximum priority from which ISR safe FreeRTOS API\r
 342                 functions can be called.  ISR safe functions are those that end in\r
 343                 "FromISR".  FreeRTOS maintains separate thread and ISR API functions to\r
 344                 ensure interrupt entry is as fast and simple as possible.\r
 345 \r
 346                 Save the interrupt priority value that is about to be clobbered. */\r
 347                 ulOriginalPriority = *pucFirstUserPriorityRegister;\r
 348 \r
 349                 /* Determine the number of priority bits available.  First write to all\r
 350                 possible bits. */\r
 351                 *pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;\r
 352 \r
 353                 /* Read the value back to see how many bits stuck. */\r
 354                 ucMaxPriorityValue = *pucFirstUserPriorityRegister;\r
 355 \r
 356                 /* Use the same mask on the maximum system call priority. */\r
 357                 ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;\r
 358 \r
 359                 /* Calculate the maximum acceptable priority group value for the number\r
 360                 of bits read back. */\r
 361                 ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;\r
 362                 while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )\r
 363                 {\r
 364                         ulMaxPRIGROUPValue--;\r
 365                         ucMaxPriorityValue <<= ( uint8_t ) 0x01;\r
 366                 }\r
 367 \r
 368                 #ifdef __NVIC_PRIO_BITS\r
 369                 {\r
 370                         /* Check the CMSIS configuration that defines the number of\r
 371                         priority bits matches the number of priority bits actually queried\r
 372                         from the hardware. */\r
 373                         configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == __NVIC_PRIO_BITS );\r
 374                 }\r
 375                 #endif\r
 376 \r
 377                 #ifdef configPRIO_BITS\r
 378                 {\r
 379                         /* Check the FreeRTOS configuration that defines the number of\r
 380                         priority bits matches the number of priority bits actually queried\r
 381                         from the hardware. */\r
 382                         configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == configPRIO_BITS );\r
 383                 }\r
 384                 #endif\r
 385 \r
 386                 /* Shift the priority group value back to its position within the AIRCR\r
 387                 register. */\r
 388                 ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;\r
 389                 ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;\r
 390 \r
 391                 /* Restore the clobbered interrupt priority register to its original\r
 392                 value. */\r
 393                 *pucFirstUserPriorityRegister = ulOriginalPriority;\r
 394         }\r
 395         #endif /* conifgASSERT_DEFINED */\r
 396 \r
 397         /* Make PendSV and SysTick the same priority as the kernel, and the SVC\r
 398         handler higher priority so it can be used to exit a critical section (where\r
 399         lower priorities are masked). */\r
 400         portNVIC_SYSPRI2_REG |= portNVIC_PENDSV_PRI;\r
 401         portNVIC_SYSPRI2_REG |= portNVIC_SYSTICK_PRI;\r
 402 \r
 403         /* Configure the regions in the MPU that are common to all tasks. */\r
 404         prvSetupMPU();\r
 405 \r
 406         /* Start the timer that generates the tick ISR.  Interrupts are disabled\r
 407         here already. */\r
 408         vPortSetupTimerInterrupt();\r
 409 \r
 410         /* Initialise the critical nesting count ready for the first task. */\r
 411         uxCriticalNesting = 0;\r
 412 \r
 413         /* Ensure the VFP is enabled - it should be anyway. */\r
 414         vPortEnableVFP();\r
 415 \r
 416         /* Lazy save always. */\r
 417         *( portFPCCR ) |= portASPEN_AND_LSPEN_BITS;\r
 418 \r
 419         /* Start the first task.  This also clears the bit that indicates the FPU is\r
 420         in use in case the FPU was used before the scheduler was started - which\r
 421         would otherwise result in the unnecessary leaving of space in the SVC stack\r
 422         for lazy saving of FPU registers. */\r
 423         __asm volatile(\r
 424                                         " ldr r0, =0xE000ED08   \n" /* Use the NVIC offset register to locate the stack. */\r
 425                                         " ldr r0, [r0]                  \n"\r
 426                                         " ldr r0, [r0]                  \n"\r
 427                                         " msr msp, r0                   \n" /* Set the msp back to the start of the stack. */\r
 428                                         " mov r0, #0                    \n" /* Clear the bit that indicates the FPU is in use, see comment above. */\r
 429                                         " msr control, r0               \n"\r
 430                                         " cpsie i                               \n" /* Globally enable interrupts. */\r
 431                                         " cpsie f                               \n"\r
 432                                         " dsb                                   \n"\r
 433                                         " isb                                   \n"\r
 434                                         " svc %0                                \n" /* System call to start first task. */\r
 435                                         " nop                                   \n"\r
 436                                         :: "i" (portSVC_START_SCHEDULER) : "memory" );\r
 437 \r
 438         /* Should not get here! */\r
 439         return 0;\r
 440 }\r
 441 /*-----------------------------------------------------------*/\r
 442 \r
 443 void vPortEndScheduler( void )\r
 444 {\r
 445         /* Not implemented in ports where there is nothing to return to.\r
 446         Artificially force an assert. */\r
 447         configASSERT( uxCriticalNesting == 1000UL );\r
 448 }\r
 449 /*-----------------------------------------------------------*/\r
 450 \r
 451 void vPortEnterCritical( void )\r
 452 {\r
 453 BaseType_t xRunningPrivileged = xPortRaisePrivilege();\r
 454 \r
 455         portDISABLE_INTERRUPTS();\r
 456         uxCriticalNesting++;\r
 457 \r
 458         vPortResetPrivilege( xRunningPrivileged );\r
 459 }\r
 460 /*-----------------------------------------------------------*/\r
 461 \r
 462 void vPortExitCritical( void )\r
 463 {\r
 464 BaseType_t xRunningPrivileged = xPortRaisePrivilege();\r
 465 \r
 466         configASSERT( uxCriticalNesting );\r
 467         uxCriticalNesting--;\r
 468         if( uxCriticalNesting == 0 )\r
 469         {\r
 470                 portENABLE_INTERRUPTS();\r
 471         }\r
 472         vPortResetPrivilege( xRunningPrivileged );\r
 473 }\r
 474 /*-----------------------------------------------------------*/\r
 475 \r
 476 void xPortPendSVHandler( void )\r
 477 {\r
 478         /* This is a naked function. */\r
 479 \r
 480         __asm volatile\r
 481         (\r
 482                 "       mrs r0, psp                                                     \n"\r
 483                 "       isb                                                                     \n"\r
 484                 "                                                                               \n"\r
 485                 "       ldr     r3, pxCurrentTCBConst                   \n" /* Get the location of the current TCB. */\r
 486                 "       ldr     r2, [r3]                                                \n"\r
 487                 "                                                                               \n"\r
 488                 "       tst r14, #0x10                                          \n" /* Is the task using the FPU context?  If so, push high vfp registers. */\r
 489                 "       it eq                                                           \n"\r
 490                 "       vstmdbeq r0!, {s16-s31}                         \n"\r
 491                 "                                                                               \n"\r
 492                 "       mrs r1, control                                         \n"\r
 493                 "       stmdb r0!, {r1, r4-r11, r14}            \n" /* Save the remaining registers. */\r
 494                 "       str r0, [r2]                                            \n" /* Save the new top of stack into the first member of the TCB. */\r
 495                 "                                                                               \n"\r
 496                 "       stmdb sp!, {r0, r3}                                     \n"\r
 497                 "       mov r0, %0                                                      \n"\r
 498                 "       msr basepri, r0                                         \n"\r
 499                 "       dsb                                                                     \n"\r
 500                 "       isb                                                                     \n"\r
 501                 "       bl vTaskSwitchContext                           \n"\r
 502                 "       mov r0, #0                                                      \n"\r
 503                 "       msr basepri, r0                                         \n"\r
 504                 "       ldmia sp!, {r0, r3}                                     \n"\r
 505                 "                                                                               \n" /* Restore the context. */\r
 506                 "       ldr r1, [r3]                                            \n"\r
 507                 "       ldr r0, [r1]                                            \n" /* The first item in the TCB is the task top of stack. */\r
 508                 "       add r1, r1, #4                                          \n" /* Move onto the second item in the TCB... */\r
 509                 "       ldr r2, =0xe000ed9c                                     \n" /* Region Base Address register. */\r
 510                 "       ldmia r1!, {r4-r11}                                     \n" /* Read 4 sets of MPU registers. */\r
 511                 "       stmia r2!, {r4-r11}                                     \n" /* Write 4 sets of MPU registers. */\r
 512                 "       ldmia r0!, {r3-r11, r14}                        \n" /* Pop the registers that are not automatically saved on exception entry. */\r
 513                 "       msr control, r3                                         \n"\r
 514                 "                                                                               \n"\r
 515                 "       tst r14, #0x10                                          \n" /* Is the task using the FPU context?  If so, pop the high vfp registers too. */\r
 516                 "       it eq                                                           \n"\r
 517                 "       vldmiaeq r0!, {s16-s31}                         \n"\r
 518                 "                                                                               \n"\r
 519                 "       msr psp, r0                                                     \n"\r
 520                 "       bx r14                                                          \n"\r
 521                 "                                                                               \n"\r
 522                 "       .align 4                                                        \n"\r
 523                 "pxCurrentTCBConst: .word pxCurrentTCB  \n"\r
 524                 ::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY)\r
 525         );\r
 526 }\r
 527 /*-----------------------------------------------------------*/\r
 528 \r
 529 void xPortSysTickHandler( void )\r
 530 {\r
 531 uint32_t ulDummy;\r
 532 \r
 533         ulDummy = portSET_INTERRUPT_MASK_FROM_ISR();\r
 534         {\r
 535                 /* Increment the RTOS tick. */\r
 536                 if( xTaskIncrementTick() != pdFALSE )\r
 537                 {\r
 538                         /* Pend a context switch. */\r
 539                         portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;\r
 540                 }\r
 541         }\r
 542         portCLEAR_INTERRUPT_MASK_FROM_ISR( ulDummy );\r
 543 }\r
 544 /*-----------------------------------------------------------*/\r
 545 \r
 546 /*\r
 547  * Setup the systick timer to generate the tick interrupts at the required\r
 548  * frequency.\r
 549  */\r
 550 __attribute__(( weak )) void vPortSetupTimerInterrupt( void )\r
 551 {\r
 552         /* Stop and clear the SysTick. */\r
 553         portNVIC_SYSTICK_CTRL_REG = 0UL;\r
 554         portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;\r
 555 \r
 556         /* Configure SysTick to interrupt at the requested rate. */\r
 557         portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;\r
 558         portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK | portNVIC_SYSTICK_INT | portNVIC_SYSTICK_ENABLE );\r
 559 }\r
 560 /*-----------------------------------------------------------*/\r
 561 \r
 562 /* This is a naked function. */\r
 563 static void vPortEnableVFP( void )\r
 564 {\r
 565         __asm volatile\r
 566         (\r
 567                 "       ldr.w r0, =0xE000ED88           \n" /* The FPU enable bits are in the CPACR. */\r
 568                 "       ldr r1, [r0]                            \n"\r
 569                 "                                                               \n"\r
 570                 "       orr r1, r1, #( 0xf << 20 )      \n" /* Enable CP10 and CP11 coprocessors, then save back. */\r
 571                 "       str r1, [r0]                            \n"\r
 572                 "       bx r14                                          "\r
 573         );\r
 574 }\r
 575 /*-----------------------------------------------------------*/\r
 576 \r
 577 static void prvSetupMPU( void )\r
 578 {\r
 579 extern uint32_t __privileged_functions_end__[];\r
 580 extern uint32_t __FLASH_segment_start__[];\r
 581 extern uint32_t __FLASH_segment_end__[];\r
 582 extern uint32_t __privileged_data_start__[];\r
 583 extern uint32_t __privileged_data_end__[];\r
 584 \r
 585         /* Check the expected MPU is present. */\r
 586         if( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE )\r
 587         {\r
 588                 /* First setup the entire flash for unprivileged read only access. */\r
 589                 portMPU_REGION_BASE_ADDRESS_REG =       ( ( uint32_t ) __FLASH_segment_start__ ) | /* Base address. */\r
 590                                                                                         ( portMPU_REGION_VALID ) |\r
 591                                                                                         ( portUNPRIVILEGED_FLASH_REGION );\r
 592 \r
 593                 portMPU_REGION_ATTRIBUTE_REG =  ( portMPU_REGION_READ_ONLY ) |\r
 594                                                                                 ( portMPU_REGION_CACHEABLE_BUFFERABLE ) |\r
 595                                                                                 ( prvGetMPURegionSizeSetting( ( uint32_t ) __FLASH_segment_end__ - ( uint32_t ) __FLASH_segment_start__ ) ) |\r
 596                                                                                 ( portMPU_REGION_ENABLE );\r
 597 \r
 598                 /* Setup the first nK for privileged only access (even though less\r
 599                 than 10K is actually being used).  This is where the kernel code is\r
 600                 placed. */\r
 601                 portMPU_REGION_BASE_ADDRESS_REG =       ( ( uint32_t ) __FLASH_segment_start__ ) | /* Base address. */\r
 602                                                                                         ( portMPU_REGION_VALID ) |\r
 603                                                                                         ( portPRIVILEGED_FLASH_REGION );\r
 604 \r
 605                 portMPU_REGION_ATTRIBUTE_REG =  ( portMPU_REGION_PRIVILEGED_READ_ONLY ) |\r
 606                                                                                 ( portMPU_REGION_CACHEABLE_BUFFERABLE ) |\r
 607                                                                                 ( prvGetMPURegionSizeSetting( ( uint32_t ) __privileged_functions_end__ - ( uint32_t ) __FLASH_segment_start__ ) ) |\r
 608                                                                                 ( portMPU_REGION_ENABLE );\r
 609 \r
 610                 /* Setup the privileged data RAM region.  This is where the kernel data\r
 611                 is placed. */\r
 612                 portMPU_REGION_BASE_ADDRESS_REG =       ( ( uint32_t ) __privileged_data_start__ ) | /* Base address. */\r
 613                                                                                         ( portMPU_REGION_VALID ) |\r
 614                                                                                         ( portPRIVILEGED_RAM_REGION );\r
 615 \r
 616                 portMPU_REGION_ATTRIBUTE_REG =  ( portMPU_REGION_PRIVILEGED_READ_WRITE ) |\r
 617                                                                                 ( portMPU_REGION_CACHEABLE_BUFFERABLE ) |\r
 618                                                                                 prvGetMPURegionSizeSetting( ( uint32_t ) __privileged_data_end__ - ( uint32_t ) __privileged_data_start__ ) |\r
 619                                                                                 ( portMPU_REGION_ENABLE );\r
 620 \r
 621                 /* By default allow everything to access the general peripherals.  The\r
 622                 system peripherals and registers are protected. */\r
 623                 portMPU_REGION_BASE_ADDRESS_REG =       ( portPERIPHERALS_START_ADDRESS ) |\r
 624                                                                                         ( portMPU_REGION_VALID ) |\r
 625                                                                                         ( portGENERAL_PERIPHERALS_REGION );\r
 626 \r
 627                 portMPU_REGION_ATTRIBUTE_REG =  ( portMPU_REGION_READ_WRITE | portMPU_REGION_EXECUTE_NEVER ) |\r
 628                                                                                 ( prvGetMPURegionSizeSetting( portPERIPHERALS_END_ADDRESS - portPERIPHERALS_START_ADDRESS ) ) |\r
 629                                                                                 ( portMPU_REGION_ENABLE );\r
 630 \r
 631                 /* Enable the memory fault exception. */\r
 632                 portNVIC_SYS_CTRL_STATE_REG |= portNVIC_MEM_FAULT_ENABLE;\r
 633 \r
 634                 /* Enable the MPU with the background region configured. */\r
 635                 portMPU_CTRL_REG |= ( portMPU_ENABLE | portMPU_BACKGROUND_ENABLE );\r
 636         }\r
 637 }\r
 638 /*-----------------------------------------------------------*/\r
 639 \r
 640 static uint32_t prvGetMPURegionSizeSetting( uint32_t ulActualSizeInBytes )\r
 641 {\r
 642 uint32_t ulRegionSize, ulReturnValue = 4;\r
 643 \r
 644         /* 32 is the smallest region size, 31 is the largest valid value for\r
 645         ulReturnValue. */\r
 646         for( ulRegionSize = 32UL; ulReturnValue < 31UL; ( ulRegionSize <<= 1UL ) )\r
 647         {\r
 648                 if( ulActualSizeInBytes <= ulRegionSize )\r
 649                 {\r
 650                         break;\r
 651                 }\r
 652                 else\r
 653                 {\r
 654                         ulReturnValue++;\r
 655                 }\r
 656         }\r
 657 \r
 658         /* Shift the code by one before returning so it can be written directly\r
 659         into the the correct bit position of the attribute register. */\r
 660         return ( ulReturnValue << 1UL );\r
 661 }\r
 662 /*-----------------------------------------------------------*/\r
 663 \r
 664 BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */\r
 665 {\r
 666         __asm volatile\r
 667         (\r
 668         "       mrs r0, control                                                 \n" /* r0 = CONTROL. */\r
 669         "       tst r0, #1                                                              \n" /* Perform r0 & 1 (bitwise AND) and update the conditions flag. */\r
 670         "       ite ne                                                                  \n"\r
 671         "       movne r0, #0                                                    \n" /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */\r
 672         "       moveq r0, #1                                                    \n" /* CONTROL[0]==0. Return true to indicate that the processor is privileged. */\r
 673         "       bx lr                                                                   \n" /* Return. */\r
 674         "                                                                                       \n"\r
 675         "       .align 4                                                                \n"\r
 676         ::: "r0", "memory"\r
 677         );\r
 678 }\r
 679 /*-----------------------------------------------------------*/\r
 680 \r
 681 void vResetPrivilege( void ) /* __attribute__ (( naked )) */\r
 682 {\r
 683         __asm volatile\r
 684         (\r
 685         "       mrs r0, control                                                 \n" /* r0 = CONTROL. */\r
 686         "       orr r0, #1                                                              \n" /* r0 = r0 | 1. */\r
 687         "       msr control, r0                                                 \n" /* CONTROL = r0. */\r
 688         "       bx lr                                                                   \n" /* Return to the caller. */\r
 689         :::"r0", "memory"\r
 690         );\r
 691 }\r
 692 /*-----------------------------------------------------------*/\r
 693 \r
 694 void vPortStoreTaskMPUSettings( xMPU_SETTINGS *xMPUSettings, const struct xMEMORY_REGION * const xRegions, StackType_t *pxBottomOfStack, uint32_t ulStackDepth )\r
 695 {\r
 696 extern uint32_t __SRAM_segment_start__[];\r
 697 extern uint32_t __SRAM_segment_end__[];\r
 698 extern uint32_t __privileged_data_start__[];\r
 699 extern uint32_t __privileged_data_end__[];\r
 700 int32_t lIndex;\r
 701 uint32_t ul;\r
 702 \r
 703         if( xRegions == NULL )\r
 704         {\r
 705                 /* No MPU regions are specified so allow access to all RAM. */\r
 706                 xMPUSettings->xRegion[ 0 ].ulRegionBaseAddress =\r
 707                                 ( ( uint32_t ) __SRAM_segment_start__ ) | /* Base address. */\r
 708                                 ( portMPU_REGION_VALID ) |\r
 709                                 ( portSTACK_REGION );\r
 710 \r
 711                 xMPUSettings->xRegion[ 0 ].ulRegionAttribute =\r
 712                                 ( portMPU_REGION_READ_WRITE ) |\r
 713                                 ( portMPU_REGION_CACHEABLE_BUFFERABLE ) |\r
 714                                 ( prvGetMPURegionSizeSetting( ( uint32_t ) __SRAM_segment_end__ - ( uint32_t ) __SRAM_segment_start__ ) ) |\r
 715                                 ( portMPU_REGION_ENABLE );\r
 716 \r
 717                 /* Re-instate the privileged only RAM region as xRegion[ 0 ] will have\r
 718                 just removed the privileged only parameters. */\r
 719                 xMPUSettings->xRegion[ 1 ].ulRegionBaseAddress =\r
 720                                 ( ( uint32_t ) __privileged_data_start__ ) | /* Base address. */\r
 721                                 ( portMPU_REGION_VALID ) |\r
 722                                 ( portSTACK_REGION + 1 );\r
 723 \r
 724                 xMPUSettings->xRegion[ 1 ].ulRegionAttribute =\r
 725                                 ( portMPU_REGION_PRIVILEGED_READ_WRITE ) |\r
 726                                 ( portMPU_REGION_CACHEABLE_BUFFERABLE ) |\r
 727                                 prvGetMPURegionSizeSetting( ( uint32_t ) __privileged_data_end__ - ( uint32_t ) __privileged_data_start__ ) |\r
 728                                 ( portMPU_REGION_ENABLE );\r
 729 \r
 730                 /* Invalidate all other regions. */\r
 731                 for( ul = 2; ul <= portNUM_CONFIGURABLE_REGIONS; ul++ )\r
 732                 {\r
 733                         xMPUSettings->xRegion[ ul ].ulRegionBaseAddress = ( portSTACK_REGION + ul ) | portMPU_REGION_VALID;\r
 734                         xMPUSettings->xRegion[ ul ].ulRegionAttribute = 0UL;\r
 735                 }\r
 736         }\r
 737         else\r
 738         {\r
 739                 /* This function is called automatically when the task is created - in\r
 740                 which case the stack region parameters will be valid.  At all other\r
 741                 times the stack parameters will not be valid and it is assumed that the\r
 742                 stack region has already been configured. */\r
 743                 if( ulStackDepth > 0 )\r
 744                 {\r
 745                         /* Define the region that allows access to the stack. */\r
 746                         xMPUSettings->xRegion[ 0 ].ulRegionBaseAddress =\r
 747                                         ( ( uint32_t ) pxBottomOfStack ) |\r
 748                                         ( portMPU_REGION_VALID ) |\r
 749                                         ( portSTACK_REGION ); /* Region number. */\r
 750 \r
 751                         xMPUSettings->xRegion[ 0 ].ulRegionAttribute =\r
 752                                         ( portMPU_REGION_READ_WRITE ) | /* Read and write. */\r
 753                                         ( prvGetMPURegionSizeSetting( ulStackDepth * ( uint32_t ) sizeof( StackType_t ) ) ) |\r
 754                                         ( portMPU_REGION_CACHEABLE_BUFFERABLE ) |\r
 755                                         ( portMPU_REGION_ENABLE );\r
 756                 }\r
 757 \r
 758                 lIndex = 0;\r
 759 \r
 760                 for( ul = 1; ul <= portNUM_CONFIGURABLE_REGIONS; ul++ )\r
 761                 {\r
 762                         if( ( xRegions[ lIndex ] ).ulLengthInBytes > 0UL )\r
 763                         {\r
 764                                 /* Translate the generic region definition contained in\r
 765                                 xRegions into the CM3 specific MPU settings that are then\r
 766                                 stored in xMPUSettings. */\r
 767                                 xMPUSettings->xRegion[ ul ].ulRegionBaseAddress =\r
 768                                                 ( ( uint32_t ) xRegions[ lIndex ].pvBaseAddress ) |\r
 769                                                 ( portMPU_REGION_VALID ) |\r
 770                                                 ( portSTACK_REGION + ul ); /* Region number. */\r
 771 \r
 772                                 xMPUSettings->xRegion[ ul ].ulRegionAttribute =\r
 773                                                 ( prvGetMPURegionSizeSetting( xRegions[ lIndex ].ulLengthInBytes ) ) |\r
 774                                                 ( xRegions[ lIndex ].ulParameters ) |\r
 775                                                 ( portMPU_REGION_ENABLE );\r
 776                         }\r
 777                         else\r
 778                         {\r
 779                                 /* Invalidate the region. */\r
 780                                 xMPUSettings->xRegion[ ul ].ulRegionBaseAddress = ( portSTACK_REGION + ul ) | portMPU_REGION_VALID;\r
 781                                 xMPUSettings->xRegion[ ul ].ulRegionAttribute = 0UL;\r
 782                         }\r
 783 \r
 784                         lIndex++;\r
 785                 }\r
 786         }\r
 787 }\r
 788 /*-----------------------------------------------------------*/\r
 789 \r
 790 #if( configASSERT_DEFINED == 1 )\r
 791 \r
 792         void vPortValidateInterruptPriority( void )\r
 793         {\r
 794         uint32_t ulCurrentInterrupt;\r
 795         uint8_t ucCurrentPriority;\r
 796 \r
 797                 /* Obtain the number of the currently executing interrupt. */\r
 798                 __asm volatile( "mrs %0, ipsr" : "=r"( ulCurrentInterrupt ) :: "memory" );\r
 799 \r
 800                 /* Is the interrupt number a user defined interrupt? */\r
 801                 if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER )\r
 802                 {\r
 803                         /* Look up the interrupt's priority. */\r
 804                         ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ];\r
 805 \r
 806                         /* The following assertion will fail if a service routine (ISR) for\r
 807                         an interrupt that has been assigned a priority above\r
 808                         configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API\r
 809                         function.  ISR safe FreeRTOS API functions must *only* be called\r
 810                         from interrupts that have been assigned a priority at or below\r
 811                         configMAX_SYSCALL_INTERRUPT_PRIORITY.\r
 812 \r
 813                         Numerically low interrupt priority numbers represent logically high\r
 814                         interrupt priorities, therefore the priority of the interrupt must\r
 815                         be set to a value equal to or numerically *higher* than\r
 816                         configMAX_SYSCALL_INTERRUPT_PRIORITY.\r
 817 \r
 818                         Interrupts that use the FreeRTOS API must not be left at their\r
 819                         default priority of     zero as that is the highest possible priority,\r
 820                         which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY,\r
 821                         and     therefore also guaranteed to be invalid.\r
 822 \r
 823                         FreeRTOS maintains separate thread and ISR API functions to ensure\r
 824                         interrupt entry is as fast and simple as possible.\r
 825 \r
 826                         The following links provide detailed information:\r
 827                         http://www.freertos.org/RTOS-Cortex-M3-M4.html\r
 828                         http://www.freertos.org/FAQHelp.html */\r
 829                         configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );\r
 830                 }\r
 831 \r
 832                 /* Priority grouping:  The interrupt controller (NVIC) allows the bits\r
 833                 that define each interrupt's priority to be split between bits that\r
 834                 define the interrupt's pre-emption priority bits and bits that define\r
 835                 the interrupt's sub-priority.  For simplicity all bits must be defined\r
 836                 to be pre-emption priority bits.  The following assertion will fail if\r
 837                 this is not the case (if some bits represent a sub-priority).\r
 838 \r
 839                 If the application only uses CMSIS libraries for interrupt\r
 840                 configuration then the correct setting can be achieved on all Cortex-M\r
 841                 devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the\r
 842                 scheduler.  Note however that some vendor specific peripheral libraries\r
 843                 assume a non-zero priority group setting, in which cases using a value\r
 844                 of zero will result in unpredicable behaviour. */\r
 845                 configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );\r
 846         }\r
 847 \r
 848 #endif /* configASSERT_DEFINED */\r
 849 /*-----------------------------------------------------------*/\r
 850 \r
 851 \r