2 FreeRTOS V8.2.0 - Copyright (C) 2015 Real Time Engineers Ltd.
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5 VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
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7 This file is part of the FreeRTOS distribution.
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9 FreeRTOS is free software; you can redistribute it and/or modify it under
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10 the terms of the GNU General Public License (version 2) as published by the
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11 Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.
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13 ***************************************************************************
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14 >>! NOTE: The modification to the GPL is included to allow you to !<<
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15 >>! distribute a combined work that includes FreeRTOS without being !<<
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16 >>! obliged to provide the source code for proprietary components !<<
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17 >>! outside of the FreeRTOS kernel. !<<
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18 ***************************************************************************
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20 FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
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21 WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
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22 FOR A PARTICULAR PURPOSE. Full license text is available on the following
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23 link: http://www.freertos.org/a00114.html
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25 ***************************************************************************
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27 * FreeRTOS provides completely free yet professionally developed, *
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28 * robust, strictly quality controlled, supported, and cross *
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29 * platform software that is more than just the market leader, it *
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30 * is the industry's de facto standard. *
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32 * Help yourself get started quickly while simultaneously helping *
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33 * to support the FreeRTOS project by purchasing a FreeRTOS *
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34 * tutorial book, reference manual, or both: *
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35 * http://www.FreeRTOS.org/Documentation *
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37 ***************************************************************************
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39 http://www.FreeRTOS.org/FAQHelp.html - Having a problem? Start by reading
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40 the FAQ page "My application does not run, what could be wrong?". Have you
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41 defined configASSERT()?
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43 http://www.FreeRTOS.org/support - In return for receiving this top quality
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44 embedded software for free we request you assist our global community by
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45 participating in the support forum.
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47 http://www.FreeRTOS.org/training - Investing in training allows your team to
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48 be as productive as possible as early as possible. Now you can receive
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49 FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers
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50 Ltd, and the world's leading authority on the world's leading RTOS.
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52 http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
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53 including FreeRTOS+Trace - an indispensable productivity tool, a DOS
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54 compatible FAT file system, and our tiny thread aware UDP/IP stack.
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56 http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.
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57 Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.
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59 http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High
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60 Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS
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61 licenses offer ticketed support, indemnification and commercial middleware.
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63 http://www.SafeRTOS.com - High Integrity Systems also provide a safety
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64 engineered and independently SIL3 certified version for use in safety and
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65 mission critical applications that require provable dependability.
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70 /*-----------------------------------------------------------
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71 * Implementation of functions defined in portable.h for the ARM CM4F port.
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72 *----------------------------------------------------------*/
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74 /* Scheduler includes. */
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75 #include "FreeRTOS.h"
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79 #error This port can only be used when the project options are configured to enable hardware floating point support.
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82 #ifndef configSYSTICK_CLOCK_HZ
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83 #define configSYSTICK_CLOCK_HZ configCPU_CLOCK_HZ
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84 /* Ensure the SysTick is clocked at the same frequency as the core. */
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85 #define portNVIC_SYSTICK_CLK_BIT ( 1UL << 2UL )
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87 /* The way the SysTick is clocked is not modified in case it is not the same
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89 #define portNVIC_SYSTICK_CLK_BIT ( 0 )
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92 /* Constants required to manipulate the core. Registers first... */
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93 #define portNVIC_SYSTICK_CTRL_REG ( * ( ( volatile uint32_t * ) 0xe000e010 ) )
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94 #define portNVIC_SYSTICK_LOAD_REG ( * ( ( volatile uint32_t * ) 0xe000e014 ) )
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95 #define portNVIC_SYSTICK_CURRENT_VALUE_REG ( * ( ( volatile uint32_t * ) 0xe000e018 ) )
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96 #define portNVIC_SYSPRI2_REG ( * ( ( volatile uint32_t * ) 0xe000ed20 ) )
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97 /* ...then bits in the registers. */
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98 #define portNVIC_SYSTICK_INT_BIT ( 1UL << 1UL )
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99 #define portNVIC_SYSTICK_ENABLE_BIT ( 1UL << 0UL )
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100 #define portNVIC_SYSTICK_COUNT_FLAG_BIT ( 1UL << 16UL )
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101 #define portNVIC_PENDSVCLEAR_BIT ( 1UL << 27UL )
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102 #define portNVIC_PEND_SYSTICK_CLEAR_BIT ( 1UL << 25UL )
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104 #define portNVIC_PENDSV_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL )
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105 #define portNVIC_SYSTICK_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL )
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107 /* Constants required to check the validity of an interrupt priority. */
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108 #define portFIRST_USER_INTERRUPT_NUMBER ( 16 )
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109 #define portNVIC_IP_REGISTERS_OFFSET_16 ( 0xE000E3F0 )
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110 #define portAIRCR_REG ( * ( ( volatile uint32_t * ) 0xE000ED0C ) )
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111 #define portMAX_8_BIT_VALUE ( ( uint8_t ) 0xff )
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112 #define portTOP_BIT_OF_BYTE ( ( uint8_t ) 0x80 )
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113 #define portMAX_PRIGROUP_BITS ( ( uint8_t ) 7 )
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114 #define portPRIORITY_GROUP_MASK ( 0x07UL << 8UL )
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115 #define portPRIGROUP_SHIFT ( 8UL )
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117 /* Masks off all bits but the VECTACTIVE bits in the ICSR register. */
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118 #define portVECTACTIVE_MASK ( 0xFFUL )
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120 /* Constants required to manipulate the VFP. */
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121 #define portFPCCR ( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating point context control register. */
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122 #define portASPEN_AND_LSPEN_BITS ( 0x3UL << 30UL )
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124 /* Constants required to set up the initial stack. */
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125 #define portINITIAL_XPSR ( 0x01000000 )
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126 #define portINITIAL_EXEC_RETURN ( 0xfffffffd )
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128 /* The systick is a 24-bit counter. */
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129 #define portMAX_24_BIT_NUMBER ( 0xffffffUL )
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131 /* A fiddle factor to estimate the number of SysTick counts that would have
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132 occurred while the SysTick counter is stopped during tickless idle
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134 #define portMISSED_COUNTS_FACTOR ( 45UL )
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136 /* Let the user override the pre-loading of the initial LR with the address of
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137 prvTaskExitError() in case is messes up unwinding of the stack in the
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139 #ifdef configTASK_RETURN_ADDRESS
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140 #define portTASK_RETURN_ADDRESS configTASK_RETURN_ADDRESS
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142 #define portTASK_RETURN_ADDRESS prvTaskExitError
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145 /* Each task maintains its own interrupt status in the critical nesting
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147 static UBaseType_t uxCriticalNesting = 0xaaaaaaaa;
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150 * Setup the timer to generate the tick interrupts. The implementation in this
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151 * file is weak to allow application writers to change the timer used to
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152 * generate the tick interrupt.
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154 void vPortSetupTimerInterrupt( void );
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157 * Exception handlers.
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159 void xPortPendSVHandler( void ) __attribute__ (( naked ));
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160 void xPortSysTickHandler( void );
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161 void vPortSVCHandler( void ) __attribute__ (( naked ));
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164 * Start first task is a separate function so it can be tested in isolation.
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166 static void prvPortStartFirstTask( void ) __attribute__ (( naked ));
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169 * Function to enable the VFP.
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171 static void vPortEnableVFP( void ) __attribute__ (( naked ));
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174 * Used to catch tasks that attempt to return from their implementing function.
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176 static void prvTaskExitError( void );
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178 /*-----------------------------------------------------------*/
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181 * The number of SysTick increments that make up one tick period.
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183 #if configUSE_TICKLESS_IDLE == 1
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184 static uint32_t ulTimerCountsForOneTick = 0;
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185 #endif /* configUSE_TICKLESS_IDLE */
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188 * The maximum number of tick periods that can be suppressed is limited by the
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189 * 24 bit resolution of the SysTick timer.
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191 #if configUSE_TICKLESS_IDLE == 1
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192 static uint32_t xMaximumPossibleSuppressedTicks = 0;
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193 #endif /* configUSE_TICKLESS_IDLE */
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196 * Compensate for the CPU cycles that pass while the SysTick is stopped (low
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197 * power functionality only.
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199 #if configUSE_TICKLESS_IDLE == 1
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200 static uint32_t ulStoppedTimerCompensation = 0;
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201 #endif /* configUSE_TICKLESS_IDLE */
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204 * Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure
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205 * FreeRTOS API functions are not called from interrupts that have been assigned
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206 * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY.
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208 #if ( configASSERT_DEFINED == 1 )
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209 static uint8_t ucMaxSysCallPriority = 0;
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210 static uint32_t ulMaxPRIGROUPValue = 0;
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211 static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const volatile uint8_t * const ) portNVIC_IP_REGISTERS_OFFSET_16;
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212 #endif /* configASSERT_DEFINED */
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214 /*-----------------------------------------------------------*/
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217 * See header file for description.
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219 StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
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221 /* Simulate the stack frame as it would be created by a context switch
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224 /* Offset added to account for the way the MCU uses the stack on entry/exit
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225 of interrupts, and to ensure alignment. */
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228 *pxTopOfStack = portINITIAL_XPSR; /* xPSR */
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230 *pxTopOfStack = ( StackType_t ) pxCode; /* PC */
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232 *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */
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234 /* Save code space by skipping register initialisation. */
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235 pxTopOfStack -= 5; /* R12, R3, R2 and R1. */
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236 *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
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238 /* A save method is being used that requires each task to maintain its
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239 own exec return value. */
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241 *pxTopOfStack = portINITIAL_EXEC_RETURN;
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243 pxTopOfStack -= 8; /* R11, R10, R9, R8, R7, R6, R5 and R4. */
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245 return pxTopOfStack;
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247 /*-----------------------------------------------------------*/
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249 static void prvTaskExitError( void )
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251 /* A function that implements a task must not exit or attempt to return to
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252 its caller as there is nothing to return to. If a task wants to exit it
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253 should instead call vTaskDelete( NULL ).
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255 Artificially force an assert() to be triggered if configASSERT() is
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256 defined, then stop here so application writers can catch the error. */
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257 configASSERT( uxCriticalNesting == ~0UL );
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258 portDISABLE_INTERRUPTS();
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261 /*-----------------------------------------------------------*/
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263 void vPortSVCHandler( void )
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266 " ldr r3, pxCurrentTCBConst2 \n" /* Restore the context. */
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267 " ldr r1, [r3] \n" /* Use pxCurrentTCBConst to get the pxCurrentTCB address. */
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268 " ldr r0, [r1] \n" /* The first item in pxCurrentTCB is the task top of stack. */
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269 " ldmia r0!, {r4-r11, r14} \n" /* Pop the registers that are not automatically saved on exception entry and the critical nesting count. */
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270 " msr psp, r0 \n" /* Restore the task stack pointer. */
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273 " msr basepri, r0 \n"
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277 "pxCurrentTCBConst2: .word pxCurrentTCB \n"
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280 /*-----------------------------------------------------------*/
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282 static void prvPortStartFirstTask( void )
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285 " ldr r0, =0xE000ED08 \n" /* Use the NVIC offset register to locate the stack. */
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288 " msr msp, r0 \n" /* Set the msp back to the start of the stack. */
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289 " cpsie i \n" /* Globally enable interrupts. */
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293 " svc 0 \n" /* System call to start first task. */
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297 /*-----------------------------------------------------------*/
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300 * See header file for description.
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302 BaseType_t xPortStartScheduler( void )
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304 /* configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0.
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305 See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
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306 configASSERT( configMAX_SYSCALL_INTERRUPT_PRIORITY );
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308 #if( configASSERT_DEFINED == 1 )
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310 volatile uint32_t ulOriginalPriority;
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311 volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER );
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312 volatile uint8_t ucMaxPriorityValue;
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314 /* Determine the maximum priority from which ISR safe FreeRTOS API
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315 functions can be called. ISR safe functions are those that end in
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316 "FromISR". FreeRTOS maintains separate thread and ISR API functions to
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317 ensure interrupt entry is as fast and simple as possible.
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319 Save the interrupt priority value that is about to be clobbered. */
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320 ulOriginalPriority = *pucFirstUserPriorityRegister;
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322 /* Determine the number of priority bits available. First write to all
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324 *pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;
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326 /* Read the value back to see how many bits stuck. */
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327 ucMaxPriorityValue = *pucFirstUserPriorityRegister;
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329 /* Use the same mask on the maximum system call priority. */
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330 ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;
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332 /* Calculate the maximum acceptable priority group value for the number
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333 of bits read back. */
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334 ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;
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335 while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
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337 ulMaxPRIGROUPValue--;
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338 ucMaxPriorityValue <<= ( uint8_t ) 0x01;
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341 /* Shift the priority group value back to its position within the AIRCR
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343 ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;
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344 ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;
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346 /* Restore the clobbered interrupt priority register to its original
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348 *pucFirstUserPriorityRegister = ulOriginalPriority;
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350 #endif /* conifgASSERT_DEFINED */
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352 /* Make PendSV and SysTick the lowest priority interrupts. */
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353 portNVIC_SYSPRI2_REG |= portNVIC_PENDSV_PRI;
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354 portNVIC_SYSPRI2_REG |= portNVIC_SYSTICK_PRI;
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356 /* Start the timer that generates the tick ISR. Interrupts are disabled
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358 vPortSetupTimerInterrupt();
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360 /* Initialise the critical nesting count ready for the first task. */
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361 uxCriticalNesting = 0;
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363 /* Ensure the VFP is enabled - it should be anyway. */
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366 /* Lazy save always. */
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367 *( portFPCCR ) |= portASPEN_AND_LSPEN_BITS;
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369 /* Start the first task. */
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370 prvPortStartFirstTask();
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372 /* Should never get here as the tasks will now be executing! Call the task
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373 exit error function to prevent compiler warnings about a static function
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374 not being called in the case that the application writer overrides this
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375 functionality by defining configTASK_RETURN_ADDRESS. */
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376 prvTaskExitError();
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378 /* Should not get here! */
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381 /*-----------------------------------------------------------*/
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383 void vPortEndScheduler( void )
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385 /* Not implemented in ports where there is nothing to return to.
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386 Artificially force an assert. */
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387 configASSERT( uxCriticalNesting == 1000UL );
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389 /*-----------------------------------------------------------*/
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391 void vPortEnterCritical( void )
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393 portDISABLE_INTERRUPTS();
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394 uxCriticalNesting++;
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396 /* This is not the interrupt safe version of the enter critical function so
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397 assert() if it is being called from an interrupt context. Only API
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398 functions that end in "FromISR" can be used in an interrupt. Only assert if
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399 the critical nesting count is 1 to protect against recursive calls if the
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400 assert function also uses a critical section. */
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401 if( uxCriticalNesting == 1 )
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403 configASSERT( ( portNVIC_INT_CTRL_REG & portVECTACTIVE_MASK ) == 0 );
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406 /*-----------------------------------------------------------*/
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408 void vPortExitCritical( void )
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410 configASSERT( uxCriticalNesting );
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411 uxCriticalNesting--;
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412 if( uxCriticalNesting == 0 )
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414 portENABLE_INTERRUPTS();
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417 /*-----------------------------------------------------------*/
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419 void xPortPendSVHandler( void )
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421 /* This is a naked function. */
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428 " ldr r3, pxCurrentTCBConst \n" /* Get the location of the current TCB. */
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431 " tst r14, #0x10 \n" /* Is the task using the FPU context? If so, push high vfp registers. */
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433 " vstmdbeq r0!, {s16-s31} \n"
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435 " stmdb r0!, {r4-r11, r14} \n" /* Save the core registers. */
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437 " str r0, [r2] \n" /* Save the new top of stack into the first member of the TCB. */
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439 " stmdb sp!, {r3} \n"
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441 " cpsid i \n" /* Errata workaround. */
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442 " msr basepri, r0 \n"
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445 " cpsie i \n" /* Errata workaround. */
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446 " bl vTaskSwitchContext \n"
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448 " msr basepri, r0 \n"
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449 " ldmia sp!, {r3} \n"
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451 " ldr r1, [r3] \n" /* The first item in pxCurrentTCB is the task top of stack. */
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454 " ldmia r0!, {r4-r11, r14} \n" /* Pop the core registers. */
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456 " tst r14, #0x10 \n" /* Is the task using the FPU context? If so, pop the high vfp registers too. */
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458 " vldmiaeq r0!, {s16-s31} \n"
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463 #ifdef WORKAROUND_PMU_CM001 /* XMC4000 specific errata workaround. */
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464 #if WORKAROUND_PMU_CM001 == 1
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473 "pxCurrentTCBConst: .word pxCurrentTCB \n"
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474 ::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY)
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477 /*-----------------------------------------------------------*/
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479 void xPortSysTickHandler( void )
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481 /* The SysTick runs at the lowest interrupt priority, so when this interrupt
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482 executes all interrupts must be unmasked. There is therefore no need to
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483 save and then restore the interrupt mask value as its value is already
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485 ( void ) portSET_INTERRUPT_MASK_FROM_ISR();
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487 /* Increment the RTOS tick. */
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488 if( xTaskIncrementTick() != pdFALSE )
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490 /* A context switch is required. Context switching is performed in
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491 the PendSV interrupt. Pend the PendSV interrupt. */
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492 portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
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495 portCLEAR_INTERRUPT_MASK_FROM_ISR( 0 );
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497 /*-----------------------------------------------------------*/
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499 #if configUSE_TICKLESS_IDLE == 1
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501 __attribute__((weak)) void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )
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503 uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements, ulSysTickCTRL;
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504 TickType_t xModifiableIdleTime;
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506 /* Make sure the SysTick reload value does not overflow the counter. */
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507 if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks )
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509 xExpectedIdleTime = xMaximumPossibleSuppressedTicks;
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512 /* Stop the SysTick momentarily. The time the SysTick is stopped for
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513 is accounted for as best it can be, but using the tickless mode will
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514 inevitably result in some tiny drift of the time maintained by the
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515 kernel with respect to calendar time. */
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516 portNVIC_SYSTICK_CTRL_REG &= ~portNVIC_SYSTICK_ENABLE_BIT;
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518 /* Calculate the reload value required to wait xExpectedIdleTime
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519 tick periods. -1 is used because this code will execute part way
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520 through one of the tick periods. */
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521 ulReloadValue = portNVIC_SYSTICK_CURRENT_VALUE_REG + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) );
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522 if( ulReloadValue > ulStoppedTimerCompensation )
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524 ulReloadValue -= ulStoppedTimerCompensation;
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527 /* Enter a critical section but don't use the taskENTER_CRITICAL()
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528 method as that will mask interrupts that should exit sleep mode. */
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529 __asm volatile( "cpsid i" );
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531 /* If a context switch is pending or a task is waiting for the scheduler
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532 to be unsuspended then abandon the low power entry. */
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533 if( eTaskConfirmSleepModeStatus() == eAbortSleep )
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535 /* Restart from whatever is left in the count register to complete
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536 this tick period. */
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537 portNVIC_SYSTICK_LOAD_REG = portNVIC_SYSTICK_CURRENT_VALUE_REG;
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539 /* Restart SysTick. */
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540 portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
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542 /* Reset the reload register to the value required for normal tick
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544 portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
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546 /* Re-enable interrupts - see comments above the cpsid instruction()
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548 __asm volatile( "cpsie i" );
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552 /* Set the new reload value. */
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553 portNVIC_SYSTICK_LOAD_REG = ulReloadValue;
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555 /* Clear the SysTick count flag and set the count value back to
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557 portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
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559 /* Restart SysTick. */
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560 portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
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562 /* Sleep until something happens. configPRE_SLEEP_PROCESSING() can
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563 set its parameter to 0 to indicate that its implementation contains
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564 its own wait for interrupt or wait for event instruction, and so wfi
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565 should not be executed again. However, the original expected idle
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566 time variable must remain unmodified, so a copy is taken. */
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567 xModifiableIdleTime = xExpectedIdleTime;
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568 configPRE_SLEEP_PROCESSING( xModifiableIdleTime );
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569 if( xModifiableIdleTime > 0 )
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571 __asm volatile( "dsb" );
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572 __asm volatile( "wfi" );
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573 __asm volatile( "isb" );
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575 configPOST_SLEEP_PROCESSING( xExpectedIdleTime );
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577 /* Stop SysTick. Again, the time the SysTick is stopped for is
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578 accounted for as best it can be, but using the tickless mode will
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579 inevitably result in some tiny drift of the time maintained by the
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580 kernel with respect to calendar time. */
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581 ulSysTickCTRL = portNVIC_SYSTICK_CTRL_REG;
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582 portNVIC_SYSTICK_CTRL_REG = ( ulSysTickCTRL & ~portNVIC_SYSTICK_ENABLE_BIT );
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584 /* Re-enable interrupts - see comments above the cpsid instruction()
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586 __asm volatile( "cpsie i" );
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588 if( ( ulSysTickCTRL & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )
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590 uint32_t ulCalculatedLoadValue;
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592 /* The tick interrupt has already executed, and the SysTick
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593 count reloaded with ulReloadValue. Reset the
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594 portNVIC_SYSTICK_LOAD_REG with whatever remains of this tick
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596 ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG );
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598 /* Don't allow a tiny value, or values that have somehow
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599 underflowed because the post sleep hook did something
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600 that took too long. */
\r
601 if( ( ulCalculatedLoadValue < ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) )
\r
603 ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL );
\r
606 portNVIC_SYSTICK_LOAD_REG = ulCalculatedLoadValue;
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608 /* The tick interrupt handler will already have pended the tick
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609 processing in the kernel. As the pending tick will be
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610 processed as soon as this function exits, the tick value
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611 maintained by the tick is stepped forward by one less than the
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612 time spent waiting. */
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613 ulCompleteTickPeriods = xExpectedIdleTime - 1UL;
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617 /* Something other than the tick interrupt ended the sleep.
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618 Work out how long the sleep lasted rounded to complete tick
\r
619 periods (not the ulReload value which accounted for part
\r
621 ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - portNVIC_SYSTICK_CURRENT_VALUE_REG;
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623 /* How many complete tick periods passed while the processor
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625 ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick;
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627 /* The reload value is set to whatever fraction of a single tick
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629 portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1 ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements;
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632 /* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG
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633 again, then set portNVIC_SYSTICK_LOAD_REG back to its standard
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634 value. The critical section is used to ensure the tick interrupt
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635 can only execute once in the case that the reload register is near
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637 portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
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638 portENTER_CRITICAL();
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640 portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
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641 vTaskStepTick( ulCompleteTickPeriods );
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642 portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
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644 portEXIT_CRITICAL();
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648 #endif /* #if configUSE_TICKLESS_IDLE */
\r
649 /*-----------------------------------------------------------*/
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652 * Setup the systick timer to generate the tick interrupts at the required
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655 __attribute__(( weak )) void vPortSetupTimerInterrupt( void )
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657 /* Calculate the constants required to configure the tick interrupt. */
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658 #if configUSE_TICKLESS_IDLE == 1
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660 ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ );
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661 xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick;
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662 ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ );
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664 #endif /* configUSE_TICKLESS_IDLE */
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666 /* Configure SysTick to interrupt at the requested rate. */
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667 portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
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668 portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT );
\r
670 /*-----------------------------------------------------------*/
\r
672 /* This is a naked function. */
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673 static void vPortEnableVFP( void )
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677 " ldr.w r0, =0xE000ED88 \n" /* The FPU enable bits are in the CPACR. */
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680 " orr r1, r1, #( 0xf << 20 ) \n" /* Enable CP10 and CP11 coprocessors, then save back. */
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685 /*-----------------------------------------------------------*/
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687 #if( configASSERT_DEFINED == 1 )
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689 void vPortValidateInterruptPriority( void )
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691 uint32_t ulCurrentInterrupt;
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692 uint8_t ucCurrentPriority;
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694 /* Obtain the number of the currently executing interrupt. */
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695 __asm volatile( "mrs %0, ipsr" : "=r"( ulCurrentInterrupt ) );
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697 /* Is the interrupt number a user defined interrupt? */
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698 if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER )
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700 /* Look up the interrupt's priority. */
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701 ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ];
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703 /* The following assertion will fail if a service routine (ISR) for
\r
704 an interrupt that has been assigned a priority above
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705 configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API
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706 function. ISR safe FreeRTOS API functions must *only* be called
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707 from interrupts that have been assigned a priority at or below
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708 configMAX_SYSCALL_INTERRUPT_PRIORITY.
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710 Numerically low interrupt priority numbers represent logically high
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711 interrupt priorities, therefore the priority of the interrupt must
\r
712 be set to a value equal to or numerically *higher* than
\r
713 configMAX_SYSCALL_INTERRUPT_PRIORITY.
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715 Interrupts that use the FreeRTOS API must not be left at their
\r
716 default priority of zero as that is the highest possible priority,
\r
717 which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY,
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718 and therefore also guaranteed to be invalid.
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720 FreeRTOS maintains separate thread and ISR API functions to ensure
\r
721 interrupt entry is as fast and simple as possible.
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723 The following links provide detailed information:
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724 http://www.freertos.org/RTOS-Cortex-M3-M4.html
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725 http://www.freertos.org/FAQHelp.html */
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726 configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );
\r
729 /* Priority grouping: The interrupt controller (NVIC) allows the bits
\r
730 that define each interrupt's priority to be split between bits that
\r
731 define the interrupt's pre-emption priority bits and bits that define
\r
732 the interrupt's sub-priority. For simplicity all bits must be defined
\r
733 to be pre-emption priority bits. The following assertion will fail if
\r
734 this is not the case (if some bits represent a sub-priority).
\r
736 If the application only uses CMSIS libraries for interrupt
\r
737 configuration then the correct setting can be achieved on all Cortex-M
\r
738 devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the
\r
739 scheduler. Note however that some vendor specific peripheral libraries
\r
740 assume a non-zero priority group setting, in which cases using a value
\r
741 of zero will result in unpredicable behaviour. */
\r
742 configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );
\r
745 #endif /* configASSERT_DEFINED */
\r
projects / freertos / blob