1 /*This file has been prepared for Doxygen automatic documentation generation.*/
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2 /*! \file *********************************************************************
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4 * \brief FreeRTOS port source for AVR32 UC3.
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6 * - Compiler: GNU GCC for AVR32
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7 * - Supported devices: All AVR32 devices can be used.
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10 * \author Atmel Corporation: http://www.atmel.com \n
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11 * Support and FAQ: http://support.atmel.no/
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13 *****************************************************************************/
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16 * FreeRTOS Kernel V10.0.0
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17 * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved.
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19 * Permission is hereby granted, free of charge, to any person obtaining a copy of
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20 * this software and associated documentation files (the "Software"), to deal in
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21 * the Software without restriction, including without limitation the rights to
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22 * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
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23 * the Software, and to permit persons to whom the Software is furnished to do so,
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24 * subject to the following conditions:
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26 * The above copyright notice and this permission notice shall be included in all
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27 * copies or substantial portions of the Software. If you wish to use our Amazon
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28 * FreeRTOS name, please do so in a fair use way that does not cause confusion.
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30 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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31 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
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32 * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
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33 * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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34 * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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35 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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37 * http://www.FreeRTOS.org
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38 * http://aws.amazon.com/freertos
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40 * 1 tab == 4 spaces!
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47 /*-----------------------------------------------------------
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48 * Port specific definitions.
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50 * The settings in this file configure FreeRTOS correctly for the
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51 * given hardware and compiler.
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53 * These settings should not be altered.
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54 *-----------------------------------------------------------
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56 #include <avr32/io.h>
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58 #include "compiler.h"
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65 /* Type definitions. */
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66 #define portCHAR char
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67 #define portFLOAT float
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68 #define portDOUBLE double
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69 #define portLONG long
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70 #define portSHORT short
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71 #define portSTACK_TYPE uint32_t
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72 #define portBASE_TYPE long
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74 typedef portSTACK_TYPE StackType_t;
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75 typedef long BaseType_t;
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76 typedef unsigned long UBaseType_t;
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78 #define TASK_DELAY_MS(x) ( (x) /portTICK_PERIOD_MS )
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79 #define TASK_DELAY_S(x) ( (x)*1000 /portTICK_PERIOD_MS )
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80 #define TASK_DELAY_MIN(x) ( (x)*60*1000/portTICK_PERIOD_MS )
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82 #define configTICK_TC_IRQ ATPASTE2(AVR32_TC_IRQ, configTICK_TC_CHANNEL)
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84 #if( configUSE_16_BIT_TICKS == 1 )
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85 typedef uint16_t TickType_t;
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86 #define portMAX_DELAY ( TickType_t ) 0xffff
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88 typedef uint32_t TickType_t;
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89 #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
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91 /*-----------------------------------------------------------*/
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93 /* Architecture specifics. */
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94 #define portSTACK_GROWTH ( -1 )
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95 #define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
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96 #define portBYTE_ALIGNMENT 4
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97 #define portNOP() {__asm__ __volatile__ ("nop");}
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98 /*-----------------------------------------------------------*/
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101 /*-----------------------------------------------------------*/
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103 /* INTC-specific. */
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104 #define DISABLE_ALL_EXCEPTIONS() Disable_global_exception()
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105 #define ENABLE_ALL_EXCEPTIONS() Enable_global_exception()
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107 #define DISABLE_ALL_INTERRUPTS() Disable_global_interrupt()
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108 #define ENABLE_ALL_INTERRUPTS() Enable_global_interrupt()
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110 #define DISABLE_INT_LEVEL(int_lev) Disable_interrupt_level(int_lev)
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111 #define ENABLE_INT_LEVEL(int_lev) Enable_interrupt_level(int_lev)
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116 * Activated if and only if configDBG is nonzero.
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117 * Prints a formatted string to stdout.
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118 * The current source file name and line number are output with a colon before
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119 * the formatted string.
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120 * A carriage return and a linefeed are appended to the output.
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121 * stdout is redirected to the USART configured by configDBG_USART.
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122 * The parameters are the same as for the standard printf function.
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123 * There is no return value.
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124 * SHALL NOT BE CALLED FROM WITHIN AN INTERRUPT as fputs and printf use malloc,
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125 * which is interrupt-unsafe with the current __malloc_lock and __malloc_unlock.
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128 #define portDBG_TRACE(...) \
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130 fputs(__FILE__ ":" ASTRINGZ(__LINE__) ": ", stdout);\
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131 printf(__VA_ARGS__);\
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132 fputs("\r\n", stdout);\
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135 #define portDBG_TRACE(...)
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139 /* Critical section management. */
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140 #define portDISABLE_INTERRUPTS() DISABLE_ALL_INTERRUPTS()
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141 #define portENABLE_INTERRUPTS() ENABLE_ALL_INTERRUPTS()
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144 extern void vPortEnterCritical( void );
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145 extern void vPortExitCritical( void );
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147 #define portENTER_CRITICAL() vPortEnterCritical();
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148 #define portEXIT_CRITICAL() vPortExitCritical();
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151 /* Added as there is no such function in FreeRTOS. */
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152 extern void *pvPortRealloc( void *pv, size_t xSize );
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153 /*-----------------------------------------------------------*/
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156 /*=============================================================================================*/
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159 * Restore Context for cases other than INTi.
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161 #define portRESTORE_CONTEXT() \
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163 extern volatile uint32_t ulCriticalNesting; \
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164 extern volatile void *volatile pxCurrentTCB; \
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166 __asm__ __volatile__ ( \
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167 /* Set SP to point to new stack */ \
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168 "mov r8, LO(%[pxCurrentTCB]) \n\t"\
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169 "orh r8, HI(%[pxCurrentTCB]) \n\t"\
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170 "ld.w r0, r8[0] \n\t"\
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171 "ld.w sp, r0[0] \n\t"\
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173 /* Restore ulCriticalNesting variable */ \
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174 "ld.w r0, sp++ \n\t"\
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175 "mov r8, LO(%[ulCriticalNesting]) \n\t"\
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176 "orh r8, HI(%[ulCriticalNesting]) \n\t"\
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177 "st.w r8[0], r0 \n\t"\
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179 /* Restore R0..R7 */ \
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180 "ldm sp++, r0-r7 \n\t"\
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181 /* R0-R7 should not be used below this line */ \
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182 /* Skip PC and SR (will do it at the end) */ \
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183 "sub sp, -2*4 \n\t"\
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184 /* Restore R8..R12 and LR */ \
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185 "ldm sp++, r8-r12, lr \n\t"\
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187 "ld.w r0, sp[-8*4]\n\t" /* R0 is modified, is restored later. */ \
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188 "mtsr %[SR], r0 \n\t"\
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190 "ld.w r0, sp[-9*4] \n\t"\
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192 "ld.w pc, sp[-7*4]" /* Get PC from stack - PC is the 7th register saved */ \
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194 : [ulCriticalNesting] "i" (&ulCriticalNesting), \
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195 [pxCurrentTCB] "i" (&pxCurrentTCB), \
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196 [SR] "i" (AVR32_SR) \
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202 * portSAVE_CONTEXT_INT() and portRESTORE_CONTEXT_INT(): for INT0..3 exceptions.
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203 * portSAVE_CONTEXT_SCALL() and portRESTORE_CONTEXT_SCALL(): for the scall exception.
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205 * Had to make different versions because registers saved on the system stack
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206 * are not the same between INT0..3 exceptions and the scall exception.
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209 // Task context stack layout:
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226 // ulCriticalNesting
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227 // (*) automatically done for INT0..INT3, but not for SCALL
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230 * The ISR used for the scheduler tick depends on whether the cooperative or
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231 * the preemptive scheduler is being used.
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233 #if configUSE_PREEMPTION == 0
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236 * portSAVE_CONTEXT_OS_INT() for OS Tick exception.
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238 #define portSAVE_CONTEXT_OS_INT() \
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240 /* Save R0..R7 */ \
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241 __asm__ __volatile__ ("stm --sp, r0-r7"); \
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243 /* With the cooperative scheduler, as there is no context switch by interrupt, */ \
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244 /* there is also no context save. */ \
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248 * portRESTORE_CONTEXT_OS_INT() for Tick exception.
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250 #define portRESTORE_CONTEXT_OS_INT() \
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252 __asm__ __volatile__ ( \
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253 /* Restore R0..R7 */ \
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254 "ldm sp++, r0-r7\n\t" \
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256 /* With the cooperative scheduler, as there is no context switch by interrupt, */ \
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257 /* there is also no context restore. */ \
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265 * portSAVE_CONTEXT_OS_INT() for OS Tick exception.
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267 #define portSAVE_CONTEXT_OS_INT() \
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269 extern volatile uint32_t ulCriticalNesting; \
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270 extern volatile void *volatile pxCurrentTCB; \
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272 /* When we come here */ \
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273 /* Registers R8..R12, LR, PC and SR had already been pushed to system stack */ \
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275 __asm__ __volatile__ ( \
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276 /* Save R0..R7 */ \
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277 "stm --sp, r0-r7 \n\t"\
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279 /* Save ulCriticalNesting variable - R0 is overwritten */ \
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280 "mov r8, LO(%[ulCriticalNesting])\n\t" \
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281 "orh r8, HI(%[ulCriticalNesting])\n\t" \
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282 "ld.w r0, r8[0] \n\t"\
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283 "st.w --sp, r0 \n\t"\
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285 /* Check if INT0 or higher were being handled (case where the OS tick interrupted another */ \
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286 /* interrupt handler (which was of a higher priority level but decided to lower its priority */ \
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287 /* level and allow other lower interrupt level to occur). */ \
\r
288 /* In this case we don't want to do a task switch because we don't know what the stack */ \
\r
289 /* currently looks like (we don't know what the interrupted interrupt handler was doing). */ \
\r
290 /* Saving SP in pxCurrentTCB and then later restoring it (thinking restoring the task) */ \
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291 /* will just be restoring the interrupt handler, no way!!! */ \
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292 /* So, since we won't do a vTaskSwitchContext(), it's of no use to save SP. */ \
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293 "ld.w r0, sp[9*4]\n\t" /* Read SR in stack */ \
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294 "bfextu r0, r0, 22, 3\n\t" /* Extract the mode bits to R0. */ \
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295 "cp.w r0, 1\n\t" /* Compare the mode bits with supervisor mode(b'001) */ \
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296 "brhi LABEL_INT_SKIP_SAVE_CONTEXT_%[LINE] \n\t"\
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298 /* Store SP in the first member of the structure pointed to by pxCurrentTCB */ \
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299 /* NOTE: we don't enter a critical section here because all interrupt handlers */ \
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300 /* MUST perform a SAVE_CONTEXT/RESTORE_CONTEXT in the same way as */ \
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301 /* portSAVE_CONTEXT_OS_INT/port_RESTORE_CONTEXT_OS_INT if they call OS functions. */ \
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302 /* => all interrupt handlers must use portENTER_SWITCHING_ISR/portEXIT_SWITCHING_ISR. */ \
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303 "mov r8, LO(%[pxCurrentTCB])\n\t" \
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304 "orh r8, HI(%[pxCurrentTCB])\n\t" \
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305 "ld.w r0, r8[0]\n\t" \
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306 "st.w r0[0], sp\n" \
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308 "LABEL_INT_SKIP_SAVE_CONTEXT_%[LINE]:" \
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310 : [ulCriticalNesting] "i" (&ulCriticalNesting), \
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311 [pxCurrentTCB] "i" (&pxCurrentTCB), \
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312 [LINE] "i" (__LINE__) \
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317 * portRESTORE_CONTEXT_OS_INT() for Tick exception.
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319 #define portRESTORE_CONTEXT_OS_INT() \
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321 extern volatile uint32_t ulCriticalNesting; \
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322 extern volatile void *volatile pxCurrentTCB; \
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324 /* Check if INT0 or higher were being handled (case where the OS tick interrupted another */ \
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325 /* interrupt handler (which was of a higher priority level but decided to lower its priority */ \
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326 /* level and allow other lower interrupt level to occur). */ \
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327 /* In this case we don't want to do a task switch because we don't know what the stack */ \
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328 /* currently looks like (we don't know what the interrupted interrupt handler was doing). */ \
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329 /* Saving SP in pxCurrentTCB and then later restoring it (thinking restoring the task) */ \
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330 /* will just be restoring the interrupt handler, no way!!! */ \
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331 __asm__ __volatile__ ( \
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332 "ld.w r0, sp[9*4]\n\t" /* Read SR in stack */ \
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333 "bfextu r0, r0, 22, 3\n\t" /* Extract the mode bits to R0. */ \
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334 "cp.w r0, 1\n\t" /* Compare the mode bits with supervisor mode(b'001) */ \
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335 "brhi LABEL_INT_SKIP_RESTORE_CONTEXT_%[LINE]" \
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337 : [LINE] "i" (__LINE__) \
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341 /* because it is here safe, always call vTaskSwitchContext() since an OS tick occurred. */ \
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342 /* A critical section has to be used here because vTaskSwitchContext handles FreeRTOS linked lists. */\
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343 portENTER_CRITICAL(); \
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344 vTaskSwitchContext(); \
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345 portEXIT_CRITICAL(); \
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347 /* Restore all registers */ \
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349 __asm__ __volatile__ ( \
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350 /* Set SP to point to new stack */ \
\r
351 "mov r8, LO(%[pxCurrentTCB]) \n\t"\
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352 "orh r8, HI(%[pxCurrentTCB]) \n\t"\
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353 "ld.w r0, r8[0] \n\t"\
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354 "ld.w sp, r0[0] \n"\
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356 "LABEL_INT_SKIP_RESTORE_CONTEXT_%[LINE]: \n\t"\
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358 /* Restore ulCriticalNesting variable */ \
\r
359 "ld.w r0, sp++ \n\t" \
\r
360 "mov r8, LO(%[ulCriticalNesting]) \n\t"\
\r
361 "orh r8, HI(%[ulCriticalNesting]) \n\t"\
\r
362 "st.w r8[0], r0 \n\t"\
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364 /* Restore R0..R7 */ \
\r
365 "ldm sp++, r0-r7 \n\t"\
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367 /* Now, the stack should be R8..R12, LR, PC and SR */ \
\r
370 : [ulCriticalNesting] "i" (&ulCriticalNesting), \
\r
371 [pxCurrentTCB] "i" (&pxCurrentTCB), \
\r
372 [LINE] "i" (__LINE__) \
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380 * portSAVE_CONTEXT_SCALL() for SupervisorCALL exception.
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382 * NOTE: taskYIELD()(== SCALL) MUST NOT be called in a mode > supervisor mode.
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385 #define portSAVE_CONTEXT_SCALL() \
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387 extern volatile uint32_t ulCriticalNesting; \
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388 extern volatile void *volatile pxCurrentTCB; \
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390 /* Warning: the stack layout after SCALL doesn't match the one after an interrupt. */ \
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391 /* If SR[M2:M0] == 001 */ \
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392 /* PC and SR are on the stack. */ \
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393 /* Else (other modes) */ \
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394 /* Nothing on the stack. */ \
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396 /* WARNING NOTE: the else case cannot happen as it is strictly forbidden to call */ \
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397 /* vTaskDelay() and vTaskDelayUntil() OS functions (that result in a taskYield()) */ \
\r
398 /* in an interrupt|exception handler. */ \
\r
400 __asm__ __volatile__ ( \
\r
401 /* in order to save R0-R7 */ \
\r
402 "sub sp, 6*4 \n\t"\
\r
403 /* Save R0..R7 */ \
\r
404 "stm --sp, r0-r7 \n\t"\
\r
406 /* in order to save R8-R12 and LR */ \
\r
407 /* do not use SP if interrupts occurs, SP must be left at bottom of stack */ \
\r
408 "sub r7, sp,-16*4 \n\t"\
\r
409 /* Copy PC and SR in other places in the stack. */ \
\r
410 "ld.w r0, r7[-2*4] \n\t" /* Read SR */\
\r
411 "st.w r7[-8*4], r0 \n\t" /* Copy SR */\
\r
412 "ld.w r0, r7[-1*4] \n\t" /* Read PC */\
\r
413 "st.w r7[-7*4], r0 \n\t" /* Copy PC */\
\r
415 /* Save R8..R12 and LR on the stack. */ \
\r
416 "stm --r7, r8-r12, lr \n\t"\
\r
418 /* Arriving here we have the following stack organizations: */ \
\r
419 /* R8..R12, LR, PC, SR, R0..R7. */ \
\r
421 /* Now we can finalize the save. */ \
\r
423 /* Save ulCriticalNesting variable - R0 is overwritten */ \
\r
424 "mov r8, LO(%[ulCriticalNesting]) \n\t"\
\r
425 "orh r8, HI(%[ulCriticalNesting]) \n\t"\
\r
426 "ld.w r0, r8[0] \n\t"\
\r
429 : [ulCriticalNesting] "i" (&ulCriticalNesting) \
\r
432 /* Disable the its which may cause a context switch (i.e. cause a change of */ \
\r
433 /* pxCurrentTCB). */ \
\r
434 /* Basically, all accesses to the pxCurrentTCB structure should be put in a */ \
\r
435 /* critical section because it is a global structure. */ \
\r
436 portENTER_CRITICAL(); \
\r
438 /* Store SP in the first member of the structure pointed to by pxCurrentTCB */ \
\r
439 __asm__ __volatile__ ( \
\r
440 "mov r8, LO(%[pxCurrentTCB]) \n\t"\
\r
441 "orh r8, HI(%[pxCurrentTCB]) \n\t"\
\r
442 "ld.w r0, r8[0] \n\t"\
\r
445 : [pxCurrentTCB] "i" (&pxCurrentTCB) \
\r
450 * portRESTORE_CONTEXT() for SupervisorCALL exception.
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452 #define portRESTORE_CONTEXT_SCALL() \
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454 extern volatile uint32_t ulCriticalNesting; \
\r
455 extern volatile void *volatile pxCurrentTCB; \
\r
457 /* Restore all registers */ \
\r
459 /* Set SP to point to new stack */ \
\r
460 __asm__ __volatile__ ( \
\r
461 "mov r8, LO(%[pxCurrentTCB]) \n\t"\
\r
462 "orh r8, HI(%[pxCurrentTCB]) \n\t"\
\r
463 "ld.w r0, r8[0] \n\t"\
\r
466 : [pxCurrentTCB] "i" (&pxCurrentTCB) \
\r
469 /* Leave pxCurrentTCB variable access critical section */ \
\r
470 portEXIT_CRITICAL(); \
\r
472 __asm__ __volatile__ ( \
\r
473 /* Restore ulCriticalNesting variable */ \
\r
474 "ld.w r0, sp++ \n\t"\
\r
475 "mov r8, LO(%[ulCriticalNesting]) \n\t"\
\r
476 "orh r8, HI(%[ulCriticalNesting]) \n\t"\
\r
477 "st.w r8[0], r0 \n\t"\
\r
479 /* skip PC and SR */ \
\r
480 /* do not use SP if interrupts occurs, SP must be left at bottom of stack */ \
\r
481 "sub r7, sp, -10*4 \n\t"\
\r
482 /* Restore r8-r12 and LR */ \
\r
483 "ldm r7++, r8-r12, lr \n\t"\
\r
485 /* RETS will take care of the extra PC and SR restore. */ \
\r
486 /* So, we have to prepare the stack for this. */ \
\r
487 "ld.w r0, r7[-8*4] \n\t" /* Read SR */\
\r
488 "st.w r7[-2*4], r0 \n\t" /* Copy SR */\
\r
489 "ld.w r0, r7[-7*4] \n\t" /* Read PC */\
\r
490 "st.w r7[-1*4], r0 \n\t" /* Copy PC */\
\r
492 /* Restore R0..R7 */ \
\r
493 "ldm sp++, r0-r7 \n\t"\
\r
495 "sub sp, -6*4 \n\t"\
\r
499 : [ulCriticalNesting] "i" (&ulCriticalNesting) \
\r
505 * The ISR used depends on whether the cooperative or
\r
506 * the preemptive scheduler is being used.
\r
508 #if configUSE_PREEMPTION == 0
\r
511 * ISR entry and exit macros. These are only required if a task switch
\r
512 * is required from the ISR.
\r
514 #define portENTER_SWITCHING_ISR() \
\r
516 /* Save R0..R7 */ \
\r
517 __asm__ __volatile__ ("stm --sp, r0-r7"); \
\r
519 /* With the cooperative scheduler, as there is no context switch by interrupt, */ \
\r
520 /* there is also no context save. */ \
\r
524 * Input parameter: in R12, boolean. Perform a vTaskSwitchContext() if 1
\r
526 #define portEXIT_SWITCHING_ISR() \
\r
528 __asm__ __volatile__ ( \
\r
529 /* Restore R0..R7 */ \
\r
530 "ldm sp++, r0-r7 \n\t"\
\r
532 /* With the cooperative scheduler, as there is no context switch by interrupt, */ \
\r
533 /* there is also no context restore. */ \
\r
541 * ISR entry and exit macros. These are only required if a task switch
\r
542 * is required from the ISR.
\r
544 #define portENTER_SWITCHING_ISR() \
\r
546 extern volatile uint32_t ulCriticalNesting; \
\r
547 extern volatile void *volatile pxCurrentTCB; \
\r
549 /* When we come here */ \
\r
550 /* Registers R8..R12, LR, PC and SR had already been pushed to system stack */ \
\r
552 __asm__ __volatile__ ( \
\r
553 /* Save R0..R7 */ \
\r
554 "stm --sp, r0-r7 \n\t"\
\r
556 /* Save ulCriticalNesting variable - R0 is overwritten */ \
\r
557 "mov r8, LO(%[ulCriticalNesting]) \n\t"\
\r
558 "orh r8, HI(%[ulCriticalNesting]) \n\t"\
\r
559 "ld.w r0, r8[0] \n\t"\
\r
560 "st.w --sp, r0 \n\t"\
\r
562 /* Check if INT0 or higher were being handled (case where the OS tick interrupted another */ \
\r
563 /* interrupt handler (which was of a higher priority level but decided to lower its priority */ \
\r
564 /* level and allow other lower interrupt level to occur). */ \
\r
565 /* In this case we don't want to do a task switch because we don't know what the stack */ \
\r
566 /* currently looks like (we don't know what the interrupted interrupt handler was doing). */ \
\r
567 /* Saving SP in pxCurrentTCB and then later restoring it (thinking restoring the task) */ \
\r
568 /* will just be restoring the interrupt handler, no way!!! */ \
\r
569 /* So, since we won't do a vTaskSwitchContext(), it's of no use to save SP. */ \
\r
570 "ld.w r0, sp[9*4] \n\t" /* Read SR in stack */\
\r
571 "bfextu r0, r0, 22, 3 \n\t" /* Extract the mode bits to R0. */\
\r
572 "cp.w r0, 1 \n\t" /* Compare the mode bits with supervisor mode(b'001) */\
\r
573 "brhi LABEL_ISR_SKIP_SAVE_CONTEXT_%[LINE] \n\t"\
\r
575 /* Store SP in the first member of the structure pointed to by pxCurrentTCB */ \
\r
576 "mov r8, LO(%[pxCurrentTCB]) \n\t"\
\r
577 "orh r8, HI(%[pxCurrentTCB]) \n\t"\
\r
578 "ld.w r0, r8[0] \n\t"\
\r
579 "st.w r0[0], sp \n"\
\r
581 "LABEL_ISR_SKIP_SAVE_CONTEXT_%[LINE]:" \
\r
583 : [ulCriticalNesting] "i" (&ulCriticalNesting), \
\r
584 [pxCurrentTCB] "i" (&pxCurrentTCB), \
\r
585 [LINE] "i" (__LINE__) \
\r
590 * Input parameter: in R12, boolean. Perform a vTaskSwitchContext() if 1
\r
592 #define portEXIT_SWITCHING_ISR() \
\r
594 extern volatile uint32_t ulCriticalNesting; \
\r
595 extern volatile void *volatile pxCurrentTCB; \
\r
597 __asm__ __volatile__ ( \
\r
598 /* Check if INT0 or higher were being handled (case where the OS tick interrupted another */ \
\r
599 /* interrupt handler (which was of a higher priority level but decided to lower its priority */ \
\r
600 /* level and allow other lower interrupt level to occur). */ \
\r
601 /* In this case it's of no use to switch context and restore a new SP because we purposedly */ \
\r
602 /* did not previously save SP in its TCB. */ \
\r
603 "ld.w r0, sp[9*4] \n\t" /* Read SR in stack */\
\r
604 "bfextu r0, r0, 22, 3 \n\t" /* Extract the mode bits to R0. */\
\r
605 "cp.w r0, 1 \n\t" /* Compare the mode bits with supervisor mode(b'001) */\
\r
606 "brhi LABEL_ISR_SKIP_RESTORE_CONTEXT_%[LINE] \n\t"\
\r
608 /* If a switch is required then we just need to call */ \
\r
609 /* vTaskSwitchContext() as the context has already been */ \
\r
611 "cp.w r12, 1 \n\t" /* Check if Switch context is required. */\
\r
612 "brne LABEL_ISR_RESTORE_CONTEXT_%[LINE]" \
\r
614 : [LINE] "i" (__LINE__) \
\r
617 /* A critical section has to be used here because vTaskSwitchContext handles FreeRTOS linked lists. */ \
\r
618 portENTER_CRITICAL(); \
\r
619 vTaskSwitchContext(); \
\r
620 portEXIT_CRITICAL(); \
\r
622 __asm__ __volatile__ ( \
\r
623 "LABEL_ISR_RESTORE_CONTEXT_%[LINE]: \n\t"\
\r
624 /* Restore the context of which ever task is now the highest */ \
\r
625 /* priority that is ready to run. */ \
\r
627 /* Restore all registers */ \
\r
629 /* Set SP to point to new stack */ \
\r
630 "mov r8, LO(%[pxCurrentTCB]) \n\t"\
\r
631 "orh r8, HI(%[pxCurrentTCB]) \n\t"\
\r
632 "ld.w r0, r8[0] \n\t"\
\r
633 "ld.w sp, r0[0] \n"\
\r
635 "LABEL_ISR_SKIP_RESTORE_CONTEXT_%[LINE]: \n\t"\
\r
637 /* Restore ulCriticalNesting variable */ \
\r
638 "ld.w r0, sp++ \n\t"\
\r
639 "mov r8, LO(%[ulCriticalNesting]) \n\t"\
\r
640 "orh r8, HI(%[ulCriticalNesting]) \n\t"\
\r
641 "st.w r8[0], r0 \n\t"\
\r
643 /* Restore R0..R7 */ \
\r
644 "ldm sp++, r0-r7 \n\t"\
\r
646 /* Now, the stack should be R8..R12, LR, PC and SR */ \
\r
649 : [ulCriticalNesting] "i" (&ulCriticalNesting), \
\r
650 [pxCurrentTCB] "i" (&pxCurrentTCB), \
\r
651 [LINE] "i" (__LINE__) \
\r
658 #define portYIELD() {__asm__ __volatile__ ("scall");}
\r
660 /* Task function macros as described on the FreeRTOS.org WEB site. */
\r
661 #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
\r
662 #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
\r
668 #endif /* PORTMACRO_H */
\r
projects / freertos / blob