1 /*This file has been prepared for Doxygen automatic documentation generation.*/
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2 /*! \file *********************************************************************
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4 * \brief FreeRTOS port source for AVR32 UC3.
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6 * - Compiler: GNU GCC for AVR32
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7 * - Supported devices: All AVR32 devices can be used.
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10 * \author Atmel Corporation: http://www.atmel.com \n
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11 * Support and FAQ: http://support.atmel.no/
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13 *****************************************************************************/
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16 FreeRTOS V8.1.1 - Copyright (C) 2014 Real Time Engineers Ltd.
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19 VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
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21 ***************************************************************************
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23 * FreeRTOS provides completely free yet professionally developed, *
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24 * robust, strictly quality controlled, supported, and cross *
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25 * platform software that has become a de facto standard. *
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27 * Help yourself get started quickly and support the FreeRTOS *
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28 * project by purchasing a FreeRTOS tutorial book, reference *
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29 * manual, or both from: http://www.FreeRTOS.org/Documentation *
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33 ***************************************************************************
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35 This file is part of the FreeRTOS distribution.
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37 FreeRTOS is free software; you can redistribute it and/or modify it under
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38 the terms of the GNU General Public License (version 2) as published by the
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39 Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.
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41 >>! NOTE: The modification to the GPL is included to allow you to !<<
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42 >>! distribute a combined work that includes FreeRTOS without being !<<
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43 >>! obliged to provide the source code for proprietary components !<<
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44 >>! outside of the FreeRTOS kernel. !<<
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46 FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
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47 WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
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48 FOR A PARTICULAR PURPOSE. Full license text is available from the following
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49 link: http://www.freertos.org/a00114.html
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53 ***************************************************************************
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55 * Having a problem? Start by reading the FAQ "My application does *
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56 * not run, what could be wrong?" *
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58 * http://www.FreeRTOS.org/FAQHelp.html *
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60 ***************************************************************************
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62 http://www.FreeRTOS.org - Documentation, books, training, latest versions,
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63 license and Real Time Engineers Ltd. contact details.
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65 http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
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66 including FreeRTOS+Trace - an indispensable productivity tool, a DOS
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67 compatible FAT file system, and our tiny thread aware UDP/IP stack.
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69 http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High
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70 Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS
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71 licenses offer ticketed support, indemnification and middleware.
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73 http://www.SafeRTOS.com - High Integrity Systems also provide a safety
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74 engineered and independently SIL3 certified version for use in safety and
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75 mission critical applications that require provable dependability.
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84 /*-----------------------------------------------------------
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85 * Port specific definitions.
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87 * The settings in this file configure FreeRTOS correctly for the
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88 * given hardware and compiler.
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90 * These settings should not be altered.
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91 *-----------------------------------------------------------
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93 #include <avr32/io.h>
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95 #include "compiler.h"
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102 /* Type definitions. */
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103 #define portCHAR char
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104 #define portFLOAT float
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105 #define portDOUBLE double
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106 #define portLONG long
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107 #define portSHORT short
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108 #define portSTACK_TYPE uint32_t
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109 #define portBASE_TYPE long
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111 typedef portSTACK_TYPE StackType_t;
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112 typedef long BaseType_t;
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113 typedef unsigned long UBaseType_t;
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115 #define TASK_DELAY_MS(x) ( (x) /portTICK_PERIOD_MS )
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116 #define TASK_DELAY_S(x) ( (x)*1000 /portTICK_PERIOD_MS )
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117 #define TASK_DELAY_MIN(x) ( (x)*60*1000/portTICK_PERIOD_MS )
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119 #define configTICK_TC_IRQ ATPASTE2(AVR32_TC_IRQ, configTICK_TC_CHANNEL)
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121 #if( configUSE_16_BIT_TICKS == 1 )
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122 typedef uint16_t TickType_t;
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123 #define portMAX_DELAY ( TickType_t ) 0xffff
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125 typedef uint32_t TickType_t;
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126 #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
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128 /*-----------------------------------------------------------*/
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130 /* Architecture specifics. */
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131 #define portSTACK_GROWTH ( -1 )
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132 #define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
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133 #define portBYTE_ALIGNMENT 4
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134 #define portNOP() {__asm__ __volatile__ ("nop");}
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135 /*-----------------------------------------------------------*/
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138 /*-----------------------------------------------------------*/
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140 /* INTC-specific. */
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141 #define DISABLE_ALL_EXCEPTIONS() Disable_global_exception()
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142 #define ENABLE_ALL_EXCEPTIONS() Enable_global_exception()
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144 #define DISABLE_ALL_INTERRUPTS() Disable_global_interrupt()
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145 #define ENABLE_ALL_INTERRUPTS() Enable_global_interrupt()
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147 #define DISABLE_INT_LEVEL(int_lev) Disable_interrupt_level(int_lev)
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148 #define ENABLE_INT_LEVEL(int_lev) Enable_interrupt_level(int_lev)
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153 * Activated if and only if configDBG is nonzero.
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154 * Prints a formatted string to stdout.
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155 * The current source file name and line number are output with a colon before
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156 * the formatted string.
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157 * A carriage return and a linefeed are appended to the output.
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158 * stdout is redirected to the USART configured by configDBG_USART.
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159 * The parameters are the same as for the standard printf function.
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160 * There is no return value.
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161 * SHALL NOT BE CALLED FROM WITHIN AN INTERRUPT as fputs and printf use malloc,
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162 * which is interrupt-unsafe with the current __malloc_lock and __malloc_unlock.
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165 #define portDBG_TRACE(...) \
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167 fputs(__FILE__ ":" ASTRINGZ(__LINE__) ": ", stdout);\
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168 printf(__VA_ARGS__);\
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169 fputs("\r\n", stdout);\
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172 #define portDBG_TRACE(...)
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176 /* Critical section management. */
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177 #define portDISABLE_INTERRUPTS() DISABLE_ALL_INTERRUPTS()
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178 #define portENABLE_INTERRUPTS() ENABLE_ALL_INTERRUPTS()
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181 extern void vPortEnterCritical( void );
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182 extern void vPortExitCritical( void );
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184 #define portENTER_CRITICAL() vPortEnterCritical();
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185 #define portEXIT_CRITICAL() vPortExitCritical();
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188 /* Added as there is no such function in FreeRTOS. */
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189 extern void *pvPortRealloc( void *pv, size_t xSize );
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190 /*-----------------------------------------------------------*/
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193 /*=============================================================================================*/
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196 * Restore Context for cases other than INTi.
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198 #define portRESTORE_CONTEXT() \
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200 extern volatile uint32_t ulCriticalNesting; \
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201 extern volatile void *volatile pxCurrentTCB; \
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203 __asm__ __volatile__ ( \
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204 /* Set SP to point to new stack */ \
\r
205 "mov r8, LO(%[pxCurrentTCB]) \n\t"\
\r
206 "orh r8, HI(%[pxCurrentTCB]) \n\t"\
\r
207 "ld.w r0, r8[0] \n\t"\
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208 "ld.w sp, r0[0] \n\t"\
\r
210 /* Restore ulCriticalNesting variable */ \
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211 "ld.w r0, sp++ \n\t"\
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212 "mov r8, LO(%[ulCriticalNesting]) \n\t"\
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213 "orh r8, HI(%[ulCriticalNesting]) \n\t"\
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214 "st.w r8[0], r0 \n\t"\
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216 /* Restore R0..R7 */ \
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217 "ldm sp++, r0-r7 \n\t"\
\r
218 /* R0-R7 should not be used below this line */ \
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219 /* Skip PC and SR (will do it at the end) */ \
\r
220 "sub sp, -2*4 \n\t"\
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221 /* Restore R8..R12 and LR */ \
\r
222 "ldm sp++, r8-r12, lr \n\t"\
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224 "ld.w r0, sp[-8*4]\n\t" /* R0 is modified, is restored later. */ \
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225 "mtsr %[SR], r0 \n\t"\
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227 "ld.w r0, sp[-9*4] \n\t"\
\r
229 "ld.w pc, sp[-7*4]" /* Get PC from stack - PC is the 7th register saved */ \
\r
231 : [ulCriticalNesting] "i" (&ulCriticalNesting), \
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232 [pxCurrentTCB] "i" (&pxCurrentTCB), \
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233 [SR] "i" (AVR32_SR) \
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239 * portSAVE_CONTEXT_INT() and portRESTORE_CONTEXT_INT(): for INT0..3 exceptions.
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240 * portSAVE_CONTEXT_SCALL() and portRESTORE_CONTEXT_SCALL(): for the scall exception.
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242 * Had to make different versions because registers saved on the system stack
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243 * are not the same between INT0..3 exceptions and the scall exception.
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246 // Task context stack layout:
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263 // ulCriticalNesting
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264 // (*) automatically done for INT0..INT3, but not for SCALL
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267 * The ISR used for the scheduler tick depends on whether the cooperative or
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268 * the preemptive scheduler is being used.
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270 #if configUSE_PREEMPTION == 0
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273 * portSAVE_CONTEXT_OS_INT() for OS Tick exception.
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275 #define portSAVE_CONTEXT_OS_INT() \
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277 /* Save R0..R7 */ \
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278 __asm__ __volatile__ ("stm --sp, r0-r7"); \
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280 /* With the cooperative scheduler, as there is no context switch by interrupt, */ \
\r
281 /* there is also no context save. */ \
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285 * portRESTORE_CONTEXT_OS_INT() for Tick exception.
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287 #define portRESTORE_CONTEXT_OS_INT() \
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289 __asm__ __volatile__ ( \
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290 /* Restore R0..R7 */ \
\r
291 "ldm sp++, r0-r7\n\t" \
\r
293 /* With the cooperative scheduler, as there is no context switch by interrupt, */ \
\r
294 /* there is also no context restore. */ \
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302 * portSAVE_CONTEXT_OS_INT() for OS Tick exception.
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304 #define portSAVE_CONTEXT_OS_INT() \
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306 extern volatile uint32_t ulCriticalNesting; \
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307 extern volatile void *volatile pxCurrentTCB; \
\r
309 /* When we come here */ \
\r
310 /* Registers R8..R12, LR, PC and SR had already been pushed to system stack */ \
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312 __asm__ __volatile__ ( \
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313 /* Save R0..R7 */ \
\r
314 "stm --sp, r0-r7 \n\t"\
\r
316 /* Save ulCriticalNesting variable - R0 is overwritten */ \
\r
317 "mov r8, LO(%[ulCriticalNesting])\n\t" \
\r
318 "orh r8, HI(%[ulCriticalNesting])\n\t" \
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319 "ld.w r0, r8[0] \n\t"\
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320 "st.w --sp, r0 \n\t"\
\r
322 /* Check if INT0 or higher were being handled (case where the OS tick interrupted another */ \
\r
323 /* interrupt handler (which was of a higher priority level but decided to lower its priority */ \
\r
324 /* level and allow other lower interrupt level to occur). */ \
\r
325 /* In this case we don't want to do a task switch because we don't know what the stack */ \
\r
326 /* currently looks like (we don't know what the interrupted interrupt handler was doing). */ \
\r
327 /* Saving SP in pxCurrentTCB and then later restoring it (thinking restoring the task) */ \
\r
328 /* will just be restoring the interrupt handler, no way!!! */ \
\r
329 /* So, since we won't do a vTaskSwitchContext(), it's of no use to save SP. */ \
\r
330 "ld.w r0, sp[9*4]\n\t" /* Read SR in stack */ \
\r
331 "bfextu r0, r0, 22, 3\n\t" /* Extract the mode bits to R0. */ \
\r
332 "cp.w r0, 1\n\t" /* Compare the mode bits with supervisor mode(b'001) */ \
\r
333 "brhi LABEL_INT_SKIP_SAVE_CONTEXT_%[LINE] \n\t"\
\r
335 /* Store SP in the first member of the structure pointed to by pxCurrentTCB */ \
\r
336 /* NOTE: we don't enter a critical section here because all interrupt handlers */ \
\r
337 /* MUST perform a SAVE_CONTEXT/RESTORE_CONTEXT in the same way as */ \
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338 /* portSAVE_CONTEXT_OS_INT/port_RESTORE_CONTEXT_OS_INT if they call OS functions. */ \
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339 /* => all interrupt handlers must use portENTER_SWITCHING_ISR/portEXIT_SWITCHING_ISR. */ \
\r
340 "mov r8, LO(%[pxCurrentTCB])\n\t" \
\r
341 "orh r8, HI(%[pxCurrentTCB])\n\t" \
\r
342 "ld.w r0, r8[0]\n\t" \
\r
343 "st.w r0[0], sp\n" \
\r
345 "LABEL_INT_SKIP_SAVE_CONTEXT_%[LINE]:" \
\r
347 : [ulCriticalNesting] "i" (&ulCriticalNesting), \
\r
348 [pxCurrentTCB] "i" (&pxCurrentTCB), \
\r
349 [LINE] "i" (__LINE__) \
\r
354 * portRESTORE_CONTEXT_OS_INT() for Tick exception.
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356 #define portRESTORE_CONTEXT_OS_INT() \
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358 extern volatile uint32_t ulCriticalNesting; \
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359 extern volatile void *volatile pxCurrentTCB; \
\r
361 /* Check if INT0 or higher were being handled (case where the OS tick interrupted another */ \
\r
362 /* interrupt handler (which was of a higher priority level but decided to lower its priority */ \
\r
363 /* level and allow other lower interrupt level to occur). */ \
\r
364 /* In this case we don't want to do a task switch because we don't know what the stack */ \
\r
365 /* currently looks like (we don't know what the interrupted interrupt handler was doing). */ \
\r
366 /* Saving SP in pxCurrentTCB and then later restoring it (thinking restoring the task) */ \
\r
367 /* will just be restoring the interrupt handler, no way!!! */ \
\r
368 __asm__ __volatile__ ( \
\r
369 "ld.w r0, sp[9*4]\n\t" /* Read SR in stack */ \
\r
370 "bfextu r0, r0, 22, 3\n\t" /* Extract the mode bits to R0. */ \
\r
371 "cp.w r0, 1\n\t" /* Compare the mode bits with supervisor mode(b'001) */ \
\r
372 "brhi LABEL_INT_SKIP_RESTORE_CONTEXT_%[LINE]" \
\r
374 : [LINE] "i" (__LINE__) \
\r
378 /* because it is here safe, always call vTaskSwitchContext() since an OS tick occurred. */ \
\r
379 /* A critical section has to be used here because vTaskSwitchContext handles FreeRTOS linked lists. */\
\r
380 portENTER_CRITICAL(); \
\r
381 vTaskSwitchContext(); \
\r
382 portEXIT_CRITICAL(); \
\r
384 /* Restore all registers */ \
\r
386 __asm__ __volatile__ ( \
\r
387 /* Set SP to point to new stack */ \
\r
388 "mov r8, LO(%[pxCurrentTCB]) \n\t"\
\r
389 "orh r8, HI(%[pxCurrentTCB]) \n\t"\
\r
390 "ld.w r0, r8[0] \n\t"\
\r
391 "ld.w sp, r0[0] \n"\
\r
393 "LABEL_INT_SKIP_RESTORE_CONTEXT_%[LINE]: \n\t"\
\r
395 /* Restore ulCriticalNesting variable */ \
\r
396 "ld.w r0, sp++ \n\t" \
\r
397 "mov r8, LO(%[ulCriticalNesting]) \n\t"\
\r
398 "orh r8, HI(%[ulCriticalNesting]) \n\t"\
\r
399 "st.w r8[0], r0 \n\t"\
\r
401 /* Restore R0..R7 */ \
\r
402 "ldm sp++, r0-r7 \n\t"\
\r
404 /* Now, the stack should be R8..R12, LR, PC and SR */ \
\r
407 : [ulCriticalNesting] "i" (&ulCriticalNesting), \
\r
408 [pxCurrentTCB] "i" (&pxCurrentTCB), \
\r
409 [LINE] "i" (__LINE__) \
\r
417 * portSAVE_CONTEXT_SCALL() for SupervisorCALL exception.
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419 * NOTE: taskYIELD()(== SCALL) MUST NOT be called in a mode > supervisor mode.
\r
422 #define portSAVE_CONTEXT_SCALL() \
\r
424 extern volatile uint32_t ulCriticalNesting; \
\r
425 extern volatile void *volatile pxCurrentTCB; \
\r
427 /* Warning: the stack layout after SCALL doesn't match the one after an interrupt. */ \
\r
428 /* If SR[M2:M0] == 001 */ \
\r
429 /* PC and SR are on the stack. */ \
\r
430 /* Else (other modes) */ \
\r
431 /* Nothing on the stack. */ \
\r
433 /* WARNING NOTE: the else case cannot happen as it is strictly forbidden to call */ \
\r
434 /* vTaskDelay() and vTaskDelayUntil() OS functions (that result in a taskYield()) */ \
\r
435 /* in an interrupt|exception handler. */ \
\r
437 __asm__ __volatile__ ( \
\r
438 /* in order to save R0-R7 */ \
\r
439 "sub sp, 6*4 \n\t"\
\r
440 /* Save R0..R7 */ \
\r
441 "stm --sp, r0-r7 \n\t"\
\r
443 /* in order to save R8-R12 and LR */ \
\r
444 /* do not use SP if interrupts occurs, SP must be left at bottom of stack */ \
\r
445 "sub r7, sp,-16*4 \n\t"\
\r
446 /* Copy PC and SR in other places in the stack. */ \
\r
447 "ld.w r0, r7[-2*4] \n\t" /* Read SR */\
\r
448 "st.w r7[-8*4], r0 \n\t" /* Copy SR */\
\r
449 "ld.w r0, r7[-1*4] \n\t" /* Read PC */\
\r
450 "st.w r7[-7*4], r0 \n\t" /* Copy PC */\
\r
452 /* Save R8..R12 and LR on the stack. */ \
\r
453 "stm --r7, r8-r12, lr \n\t"\
\r
455 /* Arriving here we have the following stack organizations: */ \
\r
456 /* R8..R12, LR, PC, SR, R0..R7. */ \
\r
458 /* Now we can finalize the save. */ \
\r
460 /* Save ulCriticalNesting variable - R0 is overwritten */ \
\r
461 "mov r8, LO(%[ulCriticalNesting]) \n\t"\
\r
462 "orh r8, HI(%[ulCriticalNesting]) \n\t"\
\r
463 "ld.w r0, r8[0] \n\t"\
\r
466 : [ulCriticalNesting] "i" (&ulCriticalNesting) \
\r
469 /* Disable the its which may cause a context switch (i.e. cause a change of */ \
\r
470 /* pxCurrentTCB). */ \
\r
471 /* Basically, all accesses to the pxCurrentTCB structure should be put in a */ \
\r
472 /* critical section because it is a global structure. */ \
\r
473 portENTER_CRITICAL(); \
\r
475 /* Store SP in the first member of the structure pointed to by pxCurrentTCB */ \
\r
476 __asm__ __volatile__ ( \
\r
477 "mov r8, LO(%[pxCurrentTCB]) \n\t"\
\r
478 "orh r8, HI(%[pxCurrentTCB]) \n\t"\
\r
479 "ld.w r0, r8[0] \n\t"\
\r
482 : [pxCurrentTCB] "i" (&pxCurrentTCB) \
\r
487 * portRESTORE_CONTEXT() for SupervisorCALL exception.
\r
489 #define portRESTORE_CONTEXT_SCALL() \
\r
491 extern volatile uint32_t ulCriticalNesting; \
\r
492 extern volatile void *volatile pxCurrentTCB; \
\r
494 /* Restore all registers */ \
\r
496 /* Set SP to point to new stack */ \
\r
497 __asm__ __volatile__ ( \
\r
498 "mov r8, LO(%[pxCurrentTCB]) \n\t"\
\r
499 "orh r8, HI(%[pxCurrentTCB]) \n\t"\
\r
500 "ld.w r0, r8[0] \n\t"\
\r
503 : [pxCurrentTCB] "i" (&pxCurrentTCB) \
\r
506 /* Leave pxCurrentTCB variable access critical section */ \
\r
507 portEXIT_CRITICAL(); \
\r
509 __asm__ __volatile__ ( \
\r
510 /* Restore ulCriticalNesting variable */ \
\r
511 "ld.w r0, sp++ \n\t"\
\r
512 "mov r8, LO(%[ulCriticalNesting]) \n\t"\
\r
513 "orh r8, HI(%[ulCriticalNesting]) \n\t"\
\r
514 "st.w r8[0], r0 \n\t"\
\r
516 /* skip PC and SR */ \
\r
517 /* do not use SP if interrupts occurs, SP must be left at bottom of stack */ \
\r
518 "sub r7, sp, -10*4 \n\t"\
\r
519 /* Restore r8-r12 and LR */ \
\r
520 "ldm r7++, r8-r12, lr \n\t"\
\r
522 /* RETS will take care of the extra PC and SR restore. */ \
\r
523 /* So, we have to prepare the stack for this. */ \
\r
524 "ld.w r0, r7[-8*4] \n\t" /* Read SR */\
\r
525 "st.w r7[-2*4], r0 \n\t" /* Copy SR */\
\r
526 "ld.w r0, r7[-7*4] \n\t" /* Read PC */\
\r
527 "st.w r7[-1*4], r0 \n\t" /* Copy PC */\
\r
529 /* Restore R0..R7 */ \
\r
530 "ldm sp++, r0-r7 \n\t"\
\r
532 "sub sp, -6*4 \n\t"\
\r
536 : [ulCriticalNesting] "i" (&ulCriticalNesting) \
\r
542 * The ISR used depends on whether the cooperative or
\r
543 * the preemptive scheduler is being used.
\r
545 #if configUSE_PREEMPTION == 0
\r
548 * ISR entry and exit macros. These are only required if a task switch
\r
549 * is required from the ISR.
\r
551 #define portENTER_SWITCHING_ISR() \
\r
553 /* Save R0..R7 */ \
\r
554 __asm__ __volatile__ ("stm --sp, r0-r7"); \
\r
556 /* With the cooperative scheduler, as there is no context switch by interrupt, */ \
\r
557 /* there is also no context save. */ \
\r
561 * Input parameter: in R12, boolean. Perform a vTaskSwitchContext() if 1
\r
563 #define portEXIT_SWITCHING_ISR() \
\r
565 __asm__ __volatile__ ( \
\r
566 /* Restore R0..R7 */ \
\r
567 "ldm sp++, r0-r7 \n\t"\
\r
569 /* With the cooperative scheduler, as there is no context switch by interrupt, */ \
\r
570 /* there is also no context restore. */ \
\r
578 * ISR entry and exit macros. These are only required if a task switch
\r
579 * is required from the ISR.
\r
581 #define portENTER_SWITCHING_ISR() \
\r
583 extern volatile uint32_t ulCriticalNesting; \
\r
584 extern volatile void *volatile pxCurrentTCB; \
\r
586 /* When we come here */ \
\r
587 /* Registers R8..R12, LR, PC and SR had already been pushed to system stack */ \
\r
589 __asm__ __volatile__ ( \
\r
590 /* Save R0..R7 */ \
\r
591 "stm --sp, r0-r7 \n\t"\
\r
593 /* Save ulCriticalNesting variable - R0 is overwritten */ \
\r
594 "mov r8, LO(%[ulCriticalNesting]) \n\t"\
\r
595 "orh r8, HI(%[ulCriticalNesting]) \n\t"\
\r
596 "ld.w r0, r8[0] \n\t"\
\r
597 "st.w --sp, r0 \n\t"\
\r
599 /* Check if INT0 or higher were being handled (case where the OS tick interrupted another */ \
\r
600 /* interrupt handler (which was of a higher priority level but decided to lower its priority */ \
\r
601 /* level and allow other lower interrupt level to occur). */ \
\r
602 /* In this case we don't want to do a task switch because we don't know what the stack */ \
\r
603 /* currently looks like (we don't know what the interrupted interrupt handler was doing). */ \
\r
604 /* Saving SP in pxCurrentTCB and then later restoring it (thinking restoring the task) */ \
\r
605 /* will just be restoring the interrupt handler, no way!!! */ \
\r
606 /* So, since we won't do a vTaskSwitchContext(), it's of no use to save SP. */ \
\r
607 "ld.w r0, sp[9*4] \n\t" /* Read SR in stack */\
\r
608 "bfextu r0, r0, 22, 3 \n\t" /* Extract the mode bits to R0. */\
\r
609 "cp.w r0, 1 \n\t" /* Compare the mode bits with supervisor mode(b'001) */\
\r
610 "brhi LABEL_ISR_SKIP_SAVE_CONTEXT_%[LINE] \n\t"\
\r
612 /* Store SP in the first member of the structure pointed to by pxCurrentTCB */ \
\r
613 "mov r8, LO(%[pxCurrentTCB]) \n\t"\
\r
614 "orh r8, HI(%[pxCurrentTCB]) \n\t"\
\r
615 "ld.w r0, r8[0] \n\t"\
\r
616 "st.w r0[0], sp \n"\
\r
618 "LABEL_ISR_SKIP_SAVE_CONTEXT_%[LINE]:" \
\r
620 : [ulCriticalNesting] "i" (&ulCriticalNesting), \
\r
621 [pxCurrentTCB] "i" (&pxCurrentTCB), \
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622 [LINE] "i" (__LINE__) \
\r
627 * Input parameter: in R12, boolean. Perform a vTaskSwitchContext() if 1
\r
629 #define portEXIT_SWITCHING_ISR() \
\r
631 extern volatile uint32_t ulCriticalNesting; \
\r
632 extern volatile void *volatile pxCurrentTCB; \
\r
634 __asm__ __volatile__ ( \
\r
635 /* Check if INT0 or higher were being handled (case where the OS tick interrupted another */ \
\r
636 /* interrupt handler (which was of a higher priority level but decided to lower its priority */ \
\r
637 /* level and allow other lower interrupt level to occur). */ \
\r
638 /* In this case it's of no use to switch context and restore a new SP because we purposedly */ \
\r
639 /* did not previously save SP in its TCB. */ \
\r
640 "ld.w r0, sp[9*4] \n\t" /* Read SR in stack */\
\r
641 "bfextu r0, r0, 22, 3 \n\t" /* Extract the mode bits to R0. */\
\r
642 "cp.w r0, 1 \n\t" /* Compare the mode bits with supervisor mode(b'001) */\
\r
643 "brhi LABEL_ISR_SKIP_RESTORE_CONTEXT_%[LINE] \n\t"\
\r
645 /* If a switch is required then we just need to call */ \
\r
646 /* vTaskSwitchContext() as the context has already been */ \
\r
648 "cp.w r12, 1 \n\t" /* Check if Switch context is required. */\
\r
649 "brne LABEL_ISR_RESTORE_CONTEXT_%[LINE]" \
\r
651 : [LINE] "i" (__LINE__) \
\r
654 /* A critical section has to be used here because vTaskSwitchContext handles FreeRTOS linked lists. */ \
\r
655 portENTER_CRITICAL(); \
\r
656 vTaskSwitchContext(); \
\r
657 portEXIT_CRITICAL(); \
\r
659 __asm__ __volatile__ ( \
\r
660 "LABEL_ISR_RESTORE_CONTEXT_%[LINE]: \n\t"\
\r
661 /* Restore the context of which ever task is now the highest */ \
\r
662 /* priority that is ready to run. */ \
\r
664 /* Restore all registers */ \
\r
666 /* Set SP to point to new stack */ \
\r
667 "mov r8, LO(%[pxCurrentTCB]) \n\t"\
\r
668 "orh r8, HI(%[pxCurrentTCB]) \n\t"\
\r
669 "ld.w r0, r8[0] \n\t"\
\r
670 "ld.w sp, r0[0] \n"\
\r
672 "LABEL_ISR_SKIP_RESTORE_CONTEXT_%[LINE]: \n\t"\
\r
674 /* Restore ulCriticalNesting variable */ \
\r
675 "ld.w r0, sp++ \n\t"\
\r
676 "mov r8, LO(%[ulCriticalNesting]) \n\t"\
\r
677 "orh r8, HI(%[ulCriticalNesting]) \n\t"\
\r
678 "st.w r8[0], r0 \n\t"\
\r
680 /* Restore R0..R7 */ \
\r
681 "ldm sp++, r0-r7 \n\t"\
\r
683 /* Now, the stack should be R8..R12, LR, PC and SR */ \
\r
686 : [ulCriticalNesting] "i" (&ulCriticalNesting), \
\r
687 [pxCurrentTCB] "i" (&pxCurrentTCB), \
\r
688 [LINE] "i" (__LINE__) \
\r
695 #define portYIELD() {__asm__ __volatile__ ("scall");}
\r
697 /* Task function macros as described on the FreeRTOS.org WEB site. */
\r
698 #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
\r
699 #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
\r
705 #endif /* PORTMACRO_H */
\r
projects / freertos / blob