2 * FreeRTOS Kernel V10.1.0
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3 * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved.
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5 * Permission is hereby granted, free of charge, to any person obtaining a copy of
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6 * this software and associated documentation files (the "Software"), to deal in
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7 * the Software without restriction, including without limitation the rights to
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8 * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
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9 * the Software, and to permit persons to whom the Software is furnished to do so,
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10 * subject to the following conditions:
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12 * The above copyright notice and this permission notice shall be included in all
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13 * copies or substantial portions of the Software.
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15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
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17 * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
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18 * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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19 * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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20 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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22 * http://www.FreeRTOS.org
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23 * http://aws.amazon.com/freertos
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25 * 1 tab == 4 spaces!
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28 /*-----------------------------------------------------------
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29 * Implementation of functions defined in portable.h for the MicroBlaze port.
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30 *----------------------------------------------------------*/
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33 /* Scheduler includes. */
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34 #include "FreeRTOS.h"
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37 /* Standard includes. */
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40 /* Hardware includes. */
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42 #include <xintc_i.h>
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43 #include <xtmrctr.h>
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45 #if( configSUPPORT_DYNAMIC_ALLOCATION == 0 )
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46 #error configSUPPORT_DYNAMIC_ALLOCATION must be set to 1 to use this port.
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49 /* Tasks are started with interrupts enabled. */
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50 #define portINITIAL_MSR_STATE ( ( StackType_t ) 0x02 )
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52 /* Tasks are started with a critical section nesting of 0 - however prior
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53 to the scheduler being commenced we don't want the critical nesting level
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54 to reach zero, so it is initialised to a high value. */
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55 #define portINITIAL_NESTING_VALUE ( 0xff )
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57 /* Our hardware setup only uses one counter. */
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58 #define portCOUNTER_0 0
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60 /* The stack used by the ISR is filled with a known value to assist in
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62 #define portISR_STACK_FILL_VALUE 0x55555555
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64 /* Counts the nesting depth of calls to portENTER_CRITICAL(). Each task
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65 maintains it's own count, so this variable is saved as part of the task
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67 volatile UBaseType_t uxCriticalNesting = portINITIAL_NESTING_VALUE;
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69 /* To limit the amount of stack required by each task, this port uses a
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70 separate stack for interrupts. */
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71 uint32_t *pulISRStack;
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73 /*-----------------------------------------------------------*/
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76 * Sets up the periodic ISR used for the RTOS tick. This uses timer 0, but
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77 * could have alternatively used the watchdog timer or timer 1.
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79 static void prvSetupTimerInterrupt( void );
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80 /*-----------------------------------------------------------*/
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83 * Initialise the stack of a task to look exactly as if a call to
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84 * portSAVE_CONTEXT had been made.
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86 * See the header file portable.h.
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88 StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
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90 extern void *_SDA2_BASE_, *_SDA_BASE_;
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91 const uint32_t ulR2 = ( uint32_t ) &_SDA2_BASE_;
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92 const uint32_t ulR13 = ( uint32_t ) &_SDA_BASE_;
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94 /* Place a few bytes of known values on the bottom of the stack.
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95 This is essential for the Microblaze port and these lines must
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96 not be omitted. The parameter value will overwrite the
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97 0x22222222 value during the function prologue. */
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98 *pxTopOfStack = ( StackType_t ) 0x11111111;
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100 *pxTopOfStack = ( StackType_t ) 0x22222222;
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102 *pxTopOfStack = ( StackType_t ) 0x33333333;
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105 /* First stack an initial value for the critical section nesting. This
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106 is initialised to zero as tasks are started with interrupts enabled. */
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107 *pxTopOfStack = ( StackType_t ) 0x00; /* R0. */
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109 /* Place an initial value for all the general purpose registers. */
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111 *pxTopOfStack = ( StackType_t ) ulR2; /* R2 - small data area. */
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113 *pxTopOfStack = ( StackType_t ) 0x03; /* R3. */
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115 *pxTopOfStack = ( StackType_t ) 0x04; /* R4. */
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117 *pxTopOfStack = ( StackType_t ) pvParameters;/* R5 contains the function call parameters. */
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119 *pxTopOfStack = ( StackType_t ) 0x06; /* R6. */
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121 *pxTopOfStack = ( StackType_t ) 0x07; /* R7. */
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123 *pxTopOfStack = ( StackType_t ) 0x08; /* R8. */
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125 *pxTopOfStack = ( StackType_t ) 0x09; /* R9. */
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127 *pxTopOfStack = ( StackType_t ) 0x0a; /* R10. */
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129 *pxTopOfStack = ( StackType_t ) 0x0b; /* R11. */
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131 *pxTopOfStack = ( StackType_t ) 0x0c; /* R12. */
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133 *pxTopOfStack = ( StackType_t ) ulR13; /* R13 - small data read write area. */
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135 *pxTopOfStack = ( StackType_t ) pxCode; /* R14. */
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137 *pxTopOfStack = ( StackType_t ) 0x0f; /* R15. */
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139 *pxTopOfStack = ( StackType_t ) 0x10; /* R16. */
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141 *pxTopOfStack = ( StackType_t ) 0x11; /* R17. */
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143 *pxTopOfStack = ( StackType_t ) 0x12; /* R18. */
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145 *pxTopOfStack = ( StackType_t ) 0x13; /* R19. */
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147 *pxTopOfStack = ( StackType_t ) 0x14; /* R20. */
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149 *pxTopOfStack = ( StackType_t ) 0x15; /* R21. */
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151 *pxTopOfStack = ( StackType_t ) 0x16; /* R22. */
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153 *pxTopOfStack = ( StackType_t ) 0x17; /* R23. */
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155 *pxTopOfStack = ( StackType_t ) 0x18; /* R24. */
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157 *pxTopOfStack = ( StackType_t ) 0x19; /* R25. */
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159 *pxTopOfStack = ( StackType_t ) 0x1a; /* R26. */
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161 *pxTopOfStack = ( StackType_t ) 0x1b; /* R27. */
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163 *pxTopOfStack = ( StackType_t ) 0x1c; /* R28. */
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165 *pxTopOfStack = ( StackType_t ) 0x1d; /* R29. */
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167 *pxTopOfStack = ( StackType_t ) 0x1e; /* R30. */
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170 /* The MSR is stacked between R30 and R31. */
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171 *pxTopOfStack = portINITIAL_MSR_STATE;
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174 *pxTopOfStack = ( StackType_t ) 0x1f; /* R31. */
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177 /* Return a pointer to the top of the stack we have generated so this can
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178 be stored in the task control block for the task. */
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179 return pxTopOfStack;
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181 /*-----------------------------------------------------------*/
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183 BaseType_t xPortStartScheduler( void )
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185 extern void ( __FreeRTOS_interrupt_Handler )( void );
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186 extern void ( vStartFirstTask )( void );
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189 /* Setup the FreeRTOS interrupt handler. Code copied from crt0.s. */
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190 asm volatile ( "la r6, r0, __FreeRTOS_interrupt_handler \n\t" \
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191 "sw r6, r1, r0 \n\t" \
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192 "lhu r7, r1, r0 \n\t" \
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193 "shi r7, r0, 0x12 \n\t" \
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194 "shi r6, r0, 0x16 " );
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196 /* Setup the hardware to generate the tick. Interrupts are disabled when
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197 this function is called. */
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198 prvSetupTimerInterrupt();
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200 /* Allocate the stack to be used by the interrupt handler. */
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201 pulISRStack = ( uint32_t * ) pvPortMalloc( configMINIMAL_STACK_SIZE * sizeof( StackType_t ) );
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203 /* Restore the context of the first task that is going to run. */
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204 if( pulISRStack != NULL )
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206 /* Fill the ISR stack with a known value to facilitate debugging. */
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207 memset( pulISRStack, portISR_STACK_FILL_VALUE, configMINIMAL_STACK_SIZE * sizeof( StackType_t ) );
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208 pulISRStack += ( configMINIMAL_STACK_SIZE - 1 );
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210 /* Kick off the first task. */
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214 /* Should not get here as the tasks are now running! */
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217 /*-----------------------------------------------------------*/
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219 void vPortEndScheduler( void )
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221 /* Not implemented. */
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223 /*-----------------------------------------------------------*/
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226 * Manual context switch called by portYIELD or taskYIELD.
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228 void vPortYield( void )
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230 extern void VPortYieldASM( void );
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232 /* Perform the context switch in a critical section to assure it is
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233 not interrupted by the tick ISR. It is not a problem to do this as
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234 each task maintains it's own interrupt status. */
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235 portENTER_CRITICAL();
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236 /* Jump directly to the yield function to ensure there is no
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237 compiler generated prologue code. */
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238 asm volatile ( "bralid r14, VPortYieldASM \n\t" \
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239 "or r0, r0, r0 \n\t" );
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240 portEXIT_CRITICAL();
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242 /*-----------------------------------------------------------*/
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245 * Hardware initialisation to generate the RTOS tick.
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247 static void prvSetupTimerInterrupt( void )
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250 const uint32_t ulCounterValue = configCPU_CLOCK_HZ / configTICK_RATE_HZ;
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251 UBaseType_t uxMask;
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253 /* The OPB timer1 is used to generate the tick. Use the provided library
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254 functions to enable the timer and set the tick frequency. */
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255 XTmrCtr_mDisable( XPAR_OPB_TIMER_1_BASEADDR, XPAR_OPB_TIMER_1_DEVICE_ID );
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256 XTmrCtr_Initialize( &xTimer, XPAR_OPB_TIMER_1_DEVICE_ID );
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257 XTmrCtr_mSetLoadReg( XPAR_OPB_TIMER_1_BASEADDR, portCOUNTER_0, ulCounterValue );
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258 XTmrCtr_mSetControlStatusReg( XPAR_OPB_TIMER_1_BASEADDR, portCOUNTER_0, XTC_CSR_LOAD_MASK | XTC_CSR_INT_OCCURED_MASK );
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260 /* Set the timer interrupt enable bit while maintaining the other bit
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262 uxMask = XIntc_In32( ( XPAR_OPB_INTC_0_BASEADDR + XIN_IER_OFFSET ) );
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263 uxMask |= XPAR_OPB_TIMER_1_INTERRUPT_MASK;
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264 XIntc_Out32( ( XPAR_OPB_INTC_0_BASEADDR + XIN_IER_OFFSET ), ( uxMask ) );
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266 XTmrCtr_Start( &xTimer, XPAR_OPB_TIMER_1_DEVICE_ID );
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267 XTmrCtr_mSetControlStatusReg(XPAR_OPB_TIMER_1_BASEADDR, portCOUNTER_0, XTC_CSR_ENABLE_TMR_MASK | XTC_CSR_ENABLE_INT_MASK | XTC_CSR_AUTO_RELOAD_MASK | XTC_CSR_DOWN_COUNT_MASK | XTC_CSR_INT_OCCURED_MASK );
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268 XIntc_mAckIntr( XPAR_INTC_SINGLE_BASEADDR, 1 );
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270 /*-----------------------------------------------------------*/
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273 * The interrupt handler placed in the interrupt vector when the scheduler is
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274 * started. The task context has already been saved when this is called.
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275 * This handler determines the interrupt source and calls the relevant
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276 * peripheral handler.
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278 void vTaskISRHandler( void )
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280 static uint32_t ulPending;
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282 /* Which interrupts are pending? */
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283 ulPending = XIntc_In32( ( XPAR_INTC_SINGLE_BASEADDR + XIN_IVR_OFFSET ) );
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285 if( ulPending < XPAR_INTC_MAX_NUM_INTR_INPUTS )
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287 static XIntc_VectorTableEntry *pxTablePtr;
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288 static XIntc_Config *pxConfig;
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289 static uint32_t ulInterruptMask;
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291 ulInterruptMask = ( uint32_t ) 1 << ulPending;
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293 /* Get the configuration data using the device ID */
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294 pxConfig = &XIntc_ConfigTable[ ( uint32_t ) XPAR_INTC_SINGLE_DEVICE_ID ];
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296 pxTablePtr = &( pxConfig->HandlerTable[ ulPending ] );
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297 if( pxConfig->AckBeforeService & ( ulInterruptMask ) )
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299 XIntc_mAckIntr( pxConfig->BaseAddress, ulInterruptMask );
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300 pxTablePtr->Handler( pxTablePtr->CallBackRef );
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304 pxTablePtr->Handler( pxTablePtr->CallBackRef );
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305 XIntc_mAckIntr( pxConfig->BaseAddress, ulInterruptMask );
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309 /*-----------------------------------------------------------*/
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312 * Handler for the timer interrupt.
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314 void vTickISR( void *pvBaseAddress )
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318 /* Increment the RTOS tick - this might cause a task to unblock. */
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319 if( xTaskIncrementTick() != pdFALSE )
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321 vTaskSwitchContext();
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324 /* Clear the timer interrupt */
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325 ulCSR = XTmrCtr_mGetControlStatusReg(XPAR_OPB_TIMER_1_BASEADDR, 0);
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326 XTmrCtr_mSetControlStatusReg( XPAR_OPB_TIMER_1_BASEADDR, portCOUNTER_0, ulCSR );
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328 /*-----------------------------------------------------------*/
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