2 FreeRTOS V7.5.2 - Copyright (C) 2013 Real Time Engineers Ltd.
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4 VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
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6 ***************************************************************************
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8 * FreeRTOS provides completely free yet professionally developed, *
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9 * robust, strictly quality controlled, supported, and cross *
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10 * platform software that has become a de facto standard. *
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12 * Help yourself get started quickly and support the FreeRTOS *
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13 * project by purchasing a FreeRTOS tutorial book, reference *
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14 * manual, or both from: http://www.FreeRTOS.org/Documentation *
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18 ***************************************************************************
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20 This file is part of the FreeRTOS distribution.
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22 FreeRTOS is free software; you can redistribute it and/or modify it under
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23 the terms of the GNU General Public License (version 2) as published by the
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24 Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.
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26 >>! NOTE: The modification to the GPL is included to allow you to distribute
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27 >>! a combined work that includes FreeRTOS without being obliged to provide
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28 >>! the source code for proprietary components outside of the FreeRTOS
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31 FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
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32 WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
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33 FOR A PARTICULAR PURPOSE. Full license text is available from the following
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34 link: http://www.freertos.org/a00114.html
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38 ***************************************************************************
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40 * Having a problem? Start by reading the FAQ "My application does *
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41 * not run, what could be wrong?" *
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43 * http://www.FreeRTOS.org/FAQHelp.html *
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45 ***************************************************************************
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47 http://www.FreeRTOS.org - Documentation, books, training, latest versions,
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48 license and Real Time Engineers Ltd. contact details.
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50 http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
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51 including FreeRTOS+Trace - an indispensable productivity tool, a DOS
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52 compatible FAT file system, and our tiny thread aware UDP/IP stack.
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54 http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High
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55 Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS
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56 licenses offer ticketed support, indemnification and middleware.
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58 http://www.SafeRTOS.com - High Integrity Systems also provide a safety
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59 engineered and independently SIL3 certified version for use in safety and
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60 mission critical applications that require provable dependability.
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65 /*-----------------------------------------------------------
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66 * Implementation of functions defined in portable.h for the MicroBlaze port.
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67 *----------------------------------------------------------*/
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70 /* Scheduler includes. */
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71 #include "FreeRTOS.h"
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74 /* Standard includes. */
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77 /* Hardware includes. */
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79 #include <xintc_i.h>
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80 #include <xtmrctr.h>
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82 /* Tasks are started with interrupts enabled. */
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83 #define portINITIAL_MSR_STATE ( ( portSTACK_TYPE ) 0x02 )
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85 /* Tasks are started with a critical section nesting of 0 - however prior
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86 to the scheduler being commenced we don't want the critical nesting level
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87 to reach zero, so it is initialised to a high value. */
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88 #define portINITIAL_NESTING_VALUE ( 0xff )
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90 /* Our hardware setup only uses one counter. */
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91 #define portCOUNTER_0 0
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93 /* The stack used by the ISR is filled with a known value to assist in
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95 #define portISR_STACK_FILL_VALUE 0x55555555
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97 /* Counts the nesting depth of calls to portENTER_CRITICAL(). Each task
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98 maintains it's own count, so this variable is saved as part of the task
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100 volatile unsigned portBASE_TYPE uxCriticalNesting = portINITIAL_NESTING_VALUE;
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102 /* To limit the amount of stack required by each task, this port uses a
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103 separate stack for interrupts. */
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104 unsigned long *pulISRStack;
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106 /*-----------------------------------------------------------*/
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109 * Sets up the periodic ISR used for the RTOS tick. This uses timer 0, but
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110 * could have alternatively used the watchdog timer or timer 1.
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112 static void prvSetupTimerInterrupt( void );
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113 /*-----------------------------------------------------------*/
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116 * Initialise the stack of a task to look exactly as if a call to
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117 * portSAVE_CONTEXT had been made.
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119 * See the header file portable.h.
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121 portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters )
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123 extern void *_SDA2_BASE_, *_SDA_BASE_;
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124 const unsigned long ulR2 = ( unsigned long ) &_SDA2_BASE_;
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125 const unsigned long ulR13 = ( unsigned long ) &_SDA_BASE_;
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127 /* Place a few bytes of known values on the bottom of the stack.
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128 This is essential for the Microblaze port and these lines must
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129 not be omitted. The parameter value will overwrite the
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130 0x22222222 value during the function prologue. */
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131 *pxTopOfStack = ( portSTACK_TYPE ) 0x11111111;
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133 *pxTopOfStack = ( portSTACK_TYPE ) 0x22222222;
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135 *pxTopOfStack = ( portSTACK_TYPE ) 0x33333333;
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138 /* First stack an initial value for the critical section nesting. This
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139 is initialised to zero as tasks are started with interrupts enabled. */
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140 *pxTopOfStack = ( portSTACK_TYPE ) 0x00; /* R0. */
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142 /* Place an initial value for all the general purpose registers. */
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144 *pxTopOfStack = ( portSTACK_TYPE ) ulR2; /* R2 - small data area. */
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146 *pxTopOfStack = ( portSTACK_TYPE ) 0x03; /* R3. */
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148 *pxTopOfStack = ( portSTACK_TYPE ) 0x04; /* R4. */
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150 *pxTopOfStack = ( portSTACK_TYPE ) pvParameters;/* R5 contains the function call parameters. */
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152 *pxTopOfStack = ( portSTACK_TYPE ) 0x06; /* R6. */
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154 *pxTopOfStack = ( portSTACK_TYPE ) 0x07; /* R7. */
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156 *pxTopOfStack = ( portSTACK_TYPE ) 0x08; /* R8. */
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158 *pxTopOfStack = ( portSTACK_TYPE ) 0x09; /* R9. */
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160 *pxTopOfStack = ( portSTACK_TYPE ) 0x0a; /* R10. */
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162 *pxTopOfStack = ( portSTACK_TYPE ) 0x0b; /* R11. */
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164 *pxTopOfStack = ( portSTACK_TYPE ) 0x0c; /* R12. */
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166 *pxTopOfStack = ( portSTACK_TYPE ) ulR13; /* R13 - small data read write area. */
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168 *pxTopOfStack = ( portSTACK_TYPE ) pxCode; /* R14. */
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170 *pxTopOfStack = ( portSTACK_TYPE ) 0x0f; /* R15. */
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172 *pxTopOfStack = ( portSTACK_TYPE ) 0x10; /* R16. */
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174 *pxTopOfStack = ( portSTACK_TYPE ) 0x11; /* R17. */
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176 *pxTopOfStack = ( portSTACK_TYPE ) 0x12; /* R18. */
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178 *pxTopOfStack = ( portSTACK_TYPE ) 0x13; /* R19. */
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180 *pxTopOfStack = ( portSTACK_TYPE ) 0x14; /* R20. */
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182 *pxTopOfStack = ( portSTACK_TYPE ) 0x15; /* R21. */
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184 *pxTopOfStack = ( portSTACK_TYPE ) 0x16; /* R22. */
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186 *pxTopOfStack = ( portSTACK_TYPE ) 0x17; /* R23. */
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188 *pxTopOfStack = ( portSTACK_TYPE ) 0x18; /* R24. */
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190 *pxTopOfStack = ( portSTACK_TYPE ) 0x19; /* R25. */
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192 *pxTopOfStack = ( portSTACK_TYPE ) 0x1a; /* R26. */
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194 *pxTopOfStack = ( portSTACK_TYPE ) 0x1b; /* R27. */
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196 *pxTopOfStack = ( portSTACK_TYPE ) 0x1c; /* R28. */
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198 *pxTopOfStack = ( portSTACK_TYPE ) 0x1d; /* R29. */
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200 *pxTopOfStack = ( portSTACK_TYPE ) 0x1e; /* R30. */
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203 /* The MSR is stacked between R30 and R31. */
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204 *pxTopOfStack = portINITIAL_MSR_STATE;
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207 *pxTopOfStack = ( portSTACK_TYPE ) 0x1f; /* R31. */
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210 /* Return a pointer to the top of the stack we have generated so this can
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211 be stored in the task control block for the task. */
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212 return pxTopOfStack;
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214 /*-----------------------------------------------------------*/
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216 portBASE_TYPE xPortStartScheduler( void )
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218 extern void ( __FreeRTOS_interrupt_Handler )( void );
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219 extern void ( vStartFirstTask )( void );
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222 /* Setup the FreeRTOS interrupt handler. Code copied from crt0.s. */
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223 asm volatile ( "la r6, r0, __FreeRTOS_interrupt_handler \n\t" \
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224 "sw r6, r1, r0 \n\t" \
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225 "lhu r7, r1, r0 \n\t" \
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226 "shi r7, r0, 0x12 \n\t" \
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227 "shi r6, r0, 0x16 " );
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229 /* Setup the hardware to generate the tick. Interrupts are disabled when
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230 this function is called. */
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231 prvSetupTimerInterrupt();
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233 /* Allocate the stack to be used by the interrupt handler. */
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234 pulISRStack = ( unsigned long * ) pvPortMalloc( configMINIMAL_STACK_SIZE * sizeof( portSTACK_TYPE ) );
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236 /* Restore the context of the first task that is going to run. */
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237 if( pulISRStack != NULL )
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239 /* Fill the ISR stack with a known value to facilitate debugging. */
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240 memset( pulISRStack, portISR_STACK_FILL_VALUE, configMINIMAL_STACK_SIZE * sizeof( portSTACK_TYPE ) );
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241 pulISRStack += ( configMINIMAL_STACK_SIZE - 1 );
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243 /* Kick off the first task. */
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247 /* Should not get here as the tasks are now running! */
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250 /*-----------------------------------------------------------*/
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252 void vPortEndScheduler( void )
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254 /* Not implemented. */
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256 /*-----------------------------------------------------------*/
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259 * Manual context switch called by portYIELD or taskYIELD.
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261 void vPortYield( void )
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263 extern void VPortYieldASM( void );
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265 /* Perform the context switch in a critical section to assure it is
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266 not interrupted by the tick ISR. It is not a problem to do this as
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267 each task maintains it's own interrupt status. */
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268 portENTER_CRITICAL();
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269 /* Jump directly to the yield function to ensure there is no
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270 compiler generated prologue code. */
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271 asm volatile ( "bralid r14, VPortYieldASM \n\t" \
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272 "or r0, r0, r0 \n\t" );
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273 portEXIT_CRITICAL();
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275 /*-----------------------------------------------------------*/
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278 * Hardware initialisation to generate the RTOS tick.
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280 static void prvSetupTimerInterrupt( void )
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283 const unsigned long ulCounterValue = configCPU_CLOCK_HZ / configTICK_RATE_HZ;
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284 unsigned portBASE_TYPE uxMask;
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286 /* The OPB timer1 is used to generate the tick. Use the provided library
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287 functions to enable the timer and set the tick frequency. */
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288 XTmrCtr_mDisable( XPAR_OPB_TIMER_1_BASEADDR, XPAR_OPB_TIMER_1_DEVICE_ID );
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289 XTmrCtr_Initialize( &xTimer, XPAR_OPB_TIMER_1_DEVICE_ID );
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290 XTmrCtr_mSetLoadReg( XPAR_OPB_TIMER_1_BASEADDR, portCOUNTER_0, ulCounterValue );
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291 XTmrCtr_mSetControlStatusReg( XPAR_OPB_TIMER_1_BASEADDR, portCOUNTER_0, XTC_CSR_LOAD_MASK | XTC_CSR_INT_OCCURED_MASK );
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293 /* Set the timer interrupt enable bit while maintaining the other bit
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295 uxMask = XIntc_In32( ( XPAR_OPB_INTC_0_BASEADDR + XIN_IER_OFFSET ) );
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296 uxMask |= XPAR_OPB_TIMER_1_INTERRUPT_MASK;
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297 XIntc_Out32( ( XPAR_OPB_INTC_0_BASEADDR + XIN_IER_OFFSET ), ( uxMask ) );
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299 XTmrCtr_Start( &xTimer, XPAR_OPB_TIMER_1_DEVICE_ID );
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300 XTmrCtr_mSetControlStatusReg(XPAR_OPB_TIMER_1_BASEADDR, portCOUNTER_0, XTC_CSR_ENABLE_TMR_MASK | XTC_CSR_ENABLE_INT_MASK | XTC_CSR_AUTO_RELOAD_MASK | XTC_CSR_DOWN_COUNT_MASK | XTC_CSR_INT_OCCURED_MASK );
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301 XIntc_mAckIntr( XPAR_INTC_SINGLE_BASEADDR, 1 );
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303 /*-----------------------------------------------------------*/
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306 * The interrupt handler placed in the interrupt vector when the scheduler is
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307 * started. The task context has already been saved when this is called.
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308 * This handler determines the interrupt source and calls the relevant
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309 * peripheral handler.
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311 void vTaskISRHandler( void )
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313 static unsigned long ulPending;
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315 /* Which interrupts are pending? */
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316 ulPending = XIntc_In32( ( XPAR_INTC_SINGLE_BASEADDR + XIN_IVR_OFFSET ) );
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318 if( ulPending < XPAR_INTC_MAX_NUM_INTR_INPUTS )
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320 static XIntc_VectorTableEntry *pxTablePtr;
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321 static XIntc_Config *pxConfig;
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322 static unsigned long ulInterruptMask;
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324 ulInterruptMask = ( unsigned long ) 1 << ulPending;
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326 /* Get the configuration data using the device ID */
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327 pxConfig = &XIntc_ConfigTable[ ( unsigned long ) XPAR_INTC_SINGLE_DEVICE_ID ];
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329 pxTablePtr = &( pxConfig->HandlerTable[ ulPending ] );
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330 if( pxConfig->AckBeforeService & ( ulInterruptMask ) )
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332 XIntc_mAckIntr( pxConfig->BaseAddress, ulInterruptMask );
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333 pxTablePtr->Handler( pxTablePtr->CallBackRef );
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337 pxTablePtr->Handler( pxTablePtr->CallBackRef );
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338 XIntc_mAckIntr( pxConfig->BaseAddress, ulInterruptMask );
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342 /*-----------------------------------------------------------*/
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345 * Handler for the timer interrupt.
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347 void vTickISR( void *pvBaseAddress )
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349 unsigned long ulCSR;
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351 /* Increment the RTOS tick - this might cause a task to unblock. */
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352 if( xTaskIncrementTick() != pdFALSE )
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354 vTaskSwitchContext();
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357 /* Clear the timer interrupt */
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358 ulCSR = XTmrCtr_mGetControlStatusReg(XPAR_OPB_TIMER_1_BASEADDR, 0);
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359 XTmrCtr_mSetControlStatusReg( XPAR_OPB_TIMER_1_BASEADDR, portCOUNTER_0, ulCSR );
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361 /*-----------------------------------------------------------*/
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