2 FreeRTOS V7.4.1 - Copyright (C) 2013 Real Time Engineers Ltd.
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4 FEATURES AND PORTS ARE ADDED TO FREERTOS ALL THE TIME. PLEASE VISIT
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5 http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
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7 ***************************************************************************
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9 * FreeRTOS tutorial books are available in pdf and paperback. *
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10 * Complete, revised, and edited pdf reference manuals are also *
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13 * Purchasing FreeRTOS documentation will not only help you, by *
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14 * ensuring you get running as quickly as possible and with an *
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15 * in-depth knowledge of how to use FreeRTOS, it will also help *
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16 * the FreeRTOS project to continue with its mission of providing *
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17 * professional grade, cross platform, de facto standard solutions *
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18 * for microcontrollers - completely free of charge! *
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20 * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *
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22 * Thank you for using FreeRTOS, and thank you for your support! *
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24 ***************************************************************************
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27 This file is part of the FreeRTOS distribution.
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29 FreeRTOS is free software; you can redistribute it and/or modify it under
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30 the terms of the GNU General Public License (version 2) as published by the
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31 Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
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33 >>>>>>NOTE<<<<<< The modification to the GPL is included to allow you to
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34 distribute a combined work that includes FreeRTOS without being obliged to
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35 provide the source code for proprietary components outside of the FreeRTOS
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38 FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
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39 WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
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40 FOR A PARTICULAR PURPOSE. See the GNU General Public License for more
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41 details. You should have received a copy of the GNU General Public License
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42 and the FreeRTOS license exception along with FreeRTOS; if not it can be
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43 viewed here: http://www.freertos.org/a00114.html and also obtained by
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44 writing to Real Time Engineers Ltd., contact details for whom are available
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45 on the FreeRTOS WEB site.
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49 ***************************************************************************
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51 * Having a problem? Start by reading the FAQ "My application does *
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52 * not run, what could be wrong?" *
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54 * http://www.FreeRTOS.org/FAQHelp.html *
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56 ***************************************************************************
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59 http://www.FreeRTOS.org - Documentation, books, training, latest versions,
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60 license and Real Time Engineers Ltd. contact details.
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62 http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
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63 including FreeRTOS+Trace - an indispensable productivity tool, and our new
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64 fully thread aware and reentrant UDP/IP stack.
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66 http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High
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67 Integrity Systems, who sell the code with commercial support,
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68 indemnification and middleware, under the OpenRTOS brand.
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70 http://www.SafeRTOS.com - High Integrity Systems also provide a safety
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71 engineered and independently SIL3 certified version for use in safety and
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72 mission critical applications that require provable dependability.
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75 /*-----------------------------------------------------------
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76 * Implementation of functions defined in portable.h for the MicroBlaze port.
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77 *----------------------------------------------------------*/
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80 /* Scheduler includes. */
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81 #include "FreeRTOS.h"
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84 /* Standard includes. */
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87 /* Hardware includes. */
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88 #include <xintc_i.h>
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89 #include <xil_exception.h>
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90 #include <microblaze_exceptions_g.h>
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92 /* Tasks are started with a critical section nesting of 0 - however, prior to
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93 the scheduler being commenced interrupts should not be enabled, so the critical
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94 nesting variable is initialised to a non-zero value. */
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95 #define portINITIAL_NESTING_VALUE ( 0xff )
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97 /* The bit within the MSR register that enabled/disables interrupts. */
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98 #define portMSR_IE ( 0x02U )
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100 /* If the floating point unit is included in the MicroBlaze build, then the
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101 FSR register is saved as part of the task context. portINITIAL_FSR is the value
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102 given to the FSR register when the initial context is set up for a task being
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104 #define portINITIAL_FSR ( 0U )
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105 /*-----------------------------------------------------------*/
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108 * Initialise the interrupt controller instance.
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110 static long prvInitialiseInterruptController( void );
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112 /* Ensure the interrupt controller instance variable is initialised before it is
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113 * used, and that the initialisation only happens once.
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115 static long prvEnsureInterruptControllerIsInitialised( void );
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117 /*-----------------------------------------------------------*/
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119 /* Counts the nesting depth of calls to portENTER_CRITICAL(). Each task
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120 maintains its own count, so this variable is saved as part of the task
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122 volatile unsigned portBASE_TYPE uxCriticalNesting = portINITIAL_NESTING_VALUE;
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124 /* This port uses a separate stack for interrupts. This prevents the stack of
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125 every task needing to be large enough to hold an entire interrupt stack on top
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126 of the task stack. */
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127 unsigned long *pulISRStack;
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129 /* If an interrupt requests a context switch, then ulTaskSwitchRequested will
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130 get set to 1. ulTaskSwitchRequested is inspected just before the main interrupt
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131 handler exits. If, at that time, ulTaskSwitchRequested is set to 1, the kernel
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132 will call vTaskSwitchContext() to ensure the task that runs immediately after
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133 the interrupt exists is the highest priority task that is able to run. This is
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134 an unusual mechanism, but is used for this port because a single interrupt can
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135 cause the servicing of multiple peripherals - and it is inefficient to call
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136 vTaskSwitchContext() multiple times as each peripheral is serviced. */
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137 volatile unsigned long ulTaskSwitchRequested = 0UL;
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139 /* The instance of the interrupt controller used by this port. This is required
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140 by the Xilinx library API functions. */
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141 static XIntc xInterruptControllerInstance;
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143 /*-----------------------------------------------------------*/
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146 * Initialise the stack of a task to look exactly as if a call to
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147 * portSAVE_CONTEXT had been made.
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149 * See the portable.h header file.
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151 portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters )
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153 extern void *_SDA2_BASE_, *_SDA_BASE_;
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154 const unsigned long ulR2 = ( unsigned long ) &_SDA2_BASE_;
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155 const unsigned long ulR13 = ( unsigned long ) &_SDA_BASE_;
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157 /* Place a few bytes of known values on the bottom of the stack.
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158 This is essential for the Microblaze port and these lines must
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160 *pxTopOfStack = ( portSTACK_TYPE ) 0x00000000;
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162 *pxTopOfStack = ( portSTACK_TYPE ) 0x00000000;
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164 *pxTopOfStack = ( portSTACK_TYPE ) 0x00000000;
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167 #if XPAR_MICROBLAZE_0_USE_FPU == 1
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168 /* The FSR value placed in the initial task context is just 0. */
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169 *pxTopOfStack = portINITIAL_FSR;
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173 /* The MSR value placed in the initial task context should have interrupts
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174 disabled. Each task will enable interrupts automatically when it enters
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175 the running state for the first time. */
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176 *pxTopOfStack = mfmsr() & ~portMSR_IE;
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179 /* First stack an initial value for the critical section nesting. This
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180 is initialised to zero. */
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181 *pxTopOfStack = ( portSTACK_TYPE ) 0x00;
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183 /* R0 is always zero. */
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184 /* R1 is the SP. */
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186 /* Place an initial value for all the general purpose registers. */
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188 *pxTopOfStack = ( portSTACK_TYPE ) ulR2; /* R2 - read only small data area. */
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190 *pxTopOfStack = ( portSTACK_TYPE ) 0x03; /* R3 - return values and temporaries. */
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192 *pxTopOfStack = ( portSTACK_TYPE ) 0x04; /* R4 - return values and temporaries. */
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194 *pxTopOfStack = ( portSTACK_TYPE ) pvParameters;/* R5 contains the function call parameters. */
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196 #ifdef portPRE_LOAD_STACK_FOR_DEBUGGING
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198 *pxTopOfStack = ( portSTACK_TYPE ) 0x06; /* R6 - other parameters and temporaries. Used as the return address from vPortTaskEntryPoint. */
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200 *pxTopOfStack = ( portSTACK_TYPE ) 0x07; /* R7 - other parameters and temporaries. */
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202 *pxTopOfStack = ( portSTACK_TYPE ) 0x08; /* R8 - other parameters and temporaries. */
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204 *pxTopOfStack = ( portSTACK_TYPE ) 0x09; /* R9 - other parameters and temporaries. */
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206 *pxTopOfStack = ( portSTACK_TYPE ) 0x0a; /* R10 - other parameters and temporaries. */
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208 *pxTopOfStack = ( portSTACK_TYPE ) 0x0b; /* R11 - temporaries. */
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210 *pxTopOfStack = ( portSTACK_TYPE ) 0x0c; /* R12 - temporaries. */
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216 *pxTopOfStack = ( portSTACK_TYPE ) ulR13; /* R13 - read/write small data area. */
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218 *pxTopOfStack = ( portSTACK_TYPE ) pxCode; /* R14 - return address for interrupt. */
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220 *pxTopOfStack = ( portSTACK_TYPE ) NULL; /* R15 - return address for subroutine. */
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222 #ifdef portPRE_LOAD_STACK_FOR_DEBUGGING
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224 *pxTopOfStack = ( portSTACK_TYPE ) 0x10; /* R16 - return address for trap (debugger). */
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226 *pxTopOfStack = ( portSTACK_TYPE ) 0x11; /* R17 - return address for exceptions, if configured. */
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228 *pxTopOfStack = ( portSTACK_TYPE ) 0x12; /* R18 - reserved for assembler and compiler temporaries. */
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234 *pxTopOfStack = ( portSTACK_TYPE ) 0x00; /* R19 - must be saved across function calls. Callee-save. Seems to be interpreted as the frame pointer. */
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236 #ifdef portPRE_LOAD_STACK_FOR_DEBUGGING
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238 *pxTopOfStack = ( portSTACK_TYPE ) 0x14; /* R20 - reserved for storing a pointer to the Global Offset Table (GOT) in Position Independent Code (PIC). Non-volatile in non-PIC code. Must be saved across function calls. Callee-save. Not used by FreeRTOS. */
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240 *pxTopOfStack = ( portSTACK_TYPE ) 0x15; /* R21 - must be saved across function calls. Callee-save. */
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242 *pxTopOfStack = ( portSTACK_TYPE ) 0x16; /* R22 - must be saved across function calls. Callee-save. */
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244 *pxTopOfStack = ( portSTACK_TYPE ) 0x17; /* R23 - must be saved across function calls. Callee-save. */
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246 *pxTopOfStack = ( portSTACK_TYPE ) 0x18; /* R24 - must be saved across function calls. Callee-save. */
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248 *pxTopOfStack = ( portSTACK_TYPE ) 0x19; /* R25 - must be saved across function calls. Callee-save. */
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250 *pxTopOfStack = ( portSTACK_TYPE ) 0x1a; /* R26 - must be saved across function calls. Callee-save. */
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252 *pxTopOfStack = ( portSTACK_TYPE ) 0x1b; /* R27 - must be saved across function calls. Callee-save. */
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254 *pxTopOfStack = ( portSTACK_TYPE ) 0x1c; /* R28 - must be saved across function calls. Callee-save. */
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256 *pxTopOfStack = ( portSTACK_TYPE ) 0x1d; /* R29 - must be saved across function calls. Callee-save. */
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258 *pxTopOfStack = ( portSTACK_TYPE ) 0x1e; /* R30 - must be saved across function calls. Callee-save. */
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260 *pxTopOfStack = ( portSTACK_TYPE ) 0x1f; /* R31 - must be saved across function calls. Callee-save. */
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263 pxTopOfStack -= 13;
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266 /* Return a pointer to the top of the stack that has been generated so this
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267 can be stored in the task control block for the task. */
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268 return pxTopOfStack;
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270 /*-----------------------------------------------------------*/
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272 portBASE_TYPE xPortStartScheduler( void )
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274 extern void ( vPortStartFirstTask )( void );
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275 extern unsigned long _stack[];
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277 /* Setup the hardware to generate the tick. Interrupts are disabled when
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278 this function is called.
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280 This port uses an application defined callback function to install the tick
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281 interrupt handler because the kernel will run on lots of different
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282 MicroBlaze and FPGA configurations - not all of which will have the same
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283 timer peripherals defined or available. An example definition of
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284 vApplicationSetupTimerInterrupt() is provided in the official demo
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285 application that accompanies this port. */
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286 vApplicationSetupTimerInterrupt();
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288 /* Reuse the stack from main() as the stack for the interrupts/exceptions. */
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289 pulISRStack = ( unsigned long * ) _stack;
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291 /* Ensure there is enough space for the functions called from the interrupt
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292 service routines to write back into the stack frame of the caller. */
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295 /* Restore the context of the first task that is going to run. From here
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296 on, the created tasks will be executing. */
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297 vPortStartFirstTask();
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299 /* Should not get here as the tasks are now running! */
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302 /*-----------------------------------------------------------*/
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304 void vPortEndScheduler( void )
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306 /* Not implemented. */
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308 /*-----------------------------------------------------------*/
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311 * Manual context switch called by portYIELD or taskYIELD.
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313 void vPortYield( void )
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315 extern void VPortYieldASM( void );
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317 /* Perform the context switch in a critical section to assure it is
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318 not interrupted by the tick ISR. It is not a problem to do this as
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319 each task maintains its own interrupt status. */
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320 portENTER_CRITICAL();
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322 /* Jump directly to the yield function to ensure there is no
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323 compiler generated prologue code. */
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324 asm volatile ( "bralid r14, VPortYieldASM \n\t" \
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325 "or r0, r0, r0 \n\t" );
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327 portEXIT_CRITICAL();
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329 /*-----------------------------------------------------------*/
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331 void vPortEnableInterrupt( unsigned char ucInterruptID )
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335 /* An API function is provided to enable an interrupt in the interrupt
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336 controller because the interrupt controller instance variable is private
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338 lReturn = prvEnsureInterruptControllerIsInitialised();
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339 if( lReturn == pdPASS )
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341 XIntc_Enable( &xInterruptControllerInstance, ucInterruptID );
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344 configASSERT( lReturn );
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346 /*-----------------------------------------------------------*/
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348 void vPortDisableInterrupt( unsigned char ucInterruptID )
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352 /* An API function is provided to disable an interrupt in the interrupt
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353 controller because the interrupt controller instance variable is private
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355 lReturn = prvEnsureInterruptControllerIsInitialised();
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357 if( lReturn == pdPASS )
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359 XIntc_Disable( &xInterruptControllerInstance, ucInterruptID );
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362 configASSERT( lReturn );
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364 /*-----------------------------------------------------------*/
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366 portBASE_TYPE xPortInstallInterruptHandler( unsigned char ucInterruptID, XInterruptHandler pxHandler, void *pvCallBackRef )
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370 /* An API function is provided to install an interrupt handler because the
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371 interrupt controller instance variable is private to this file. */
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373 lReturn = prvEnsureInterruptControllerIsInitialised();
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375 if( lReturn == pdPASS )
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377 lReturn = XIntc_Connect( &xInterruptControllerInstance, ucInterruptID, pxHandler, pvCallBackRef );
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380 if( lReturn == XST_SUCCESS )
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385 configASSERT( lReturn == pdPASS );
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389 /*-----------------------------------------------------------*/
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391 static long prvEnsureInterruptControllerIsInitialised( void )
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393 static long lInterruptControllerInitialised = pdFALSE;
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396 /* Ensure the interrupt controller instance variable is initialised before
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397 it is used, and that the initialisation only happens once. */
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398 if( lInterruptControllerInitialised != pdTRUE )
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400 lReturn = prvInitialiseInterruptController();
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402 if( lReturn == pdPASS )
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404 lInterruptControllerInitialised = pdTRUE;
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414 /*-----------------------------------------------------------*/
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417 * Handler for the timer interrupt. This is the handler that the application
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418 * defined callback function vApplicationSetupTimerInterrupt() should install.
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420 void vPortTickISR( void *pvUnused )
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422 extern void vApplicationClearTimerInterrupt( void );
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424 /* Ensure the unused parameter does not generate a compiler warning. */
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427 /* This port uses an application defined callback function to clear the tick
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428 interrupt because the kernel will run on lots of different MicroBlaze and
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429 FPGA configurations - not all of which will have the same timer peripherals
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430 defined or available. An example definition of
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431 vApplicationClearTimerInterrupt() is provided in the official demo
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432 application that accompanies this port. */
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433 vApplicationClearTimerInterrupt();
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435 /* Increment the RTOS tick - this might cause a task to unblock. */
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436 vTaskIncrementTick();
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438 /* If the preemptive scheduler is being used then a context switch should be
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439 requested in case incrementing the tick unblocked a task, or a time slice
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440 should cause another task to enter the Running state. */
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441 #if configUSE_PREEMPTION == 1
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442 /* Force vTaskSwitchContext() to be called as the interrupt exits. */
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443 ulTaskSwitchRequested = 1;
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446 /*-----------------------------------------------------------*/
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448 static long prvInitialiseInterruptController( void )
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452 lStatus = XIntc_Initialize( &xInterruptControllerInstance, configINTERRUPT_CONTROLLER_TO_USE );
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454 if( lStatus == XST_SUCCESS )
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456 /* Initialise the exception table. */
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457 Xil_ExceptionInit();
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459 /* Service all pending interrupts each time the handler is entered. */
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460 XIntc_SetIntrSvcOption( xInterruptControllerInstance.BaseAddress, XIN_SVC_ALL_ISRS_OPTION );
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462 /* Install exception handlers if the MicroBlaze is configured to handle
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463 exceptions, and the application defined constant
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464 configINSTALL_EXCEPTION_HANDLERS is set to 1. */
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465 #if ( MICROBLAZE_EXCEPTIONS_ENABLED == 1 ) && ( configINSTALL_EXCEPTION_HANDLERS == 1 )
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467 vPortExceptionsInstallHandlers();
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469 #endif /* MICROBLAZE_EXCEPTIONS_ENABLED */
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471 /* Start the interrupt controller. Interrupts are enabled when the
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472 scheduler starts. */
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473 lStatus = XIntc_Start( &xInterruptControllerInstance, XIN_REAL_MODE );
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475 if( lStatus == XST_SUCCESS )
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485 configASSERT( lStatus == pdPASS );
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489 /*-----------------------------------------------------------*/
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