2 * FreeRTOS Kernel V10.1.0
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3 * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved.
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5 * Permission is hereby granted, free of charge, to any person obtaining a copy of
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6 * this software and associated documentation files (the "Software"), to deal in
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7 * the Software without restriction, including without limitation the rights to
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8 * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
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9 * the Software, and to permit persons to whom the Software is furnished to do so,
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10 * subject to the following conditions:
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12 * The above copyright notice and this permission notice shall be included in all
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13 * copies or substantial portions of the Software.
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15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
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17 * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
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18 * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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19 * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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20 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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22 * http://www.FreeRTOS.org
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23 * http://aws.amazon.com/freertos
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25 * 1 tab == 4 spaces!
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28 /*-----------------------------------------------------------
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29 * Implementation of functions defined in portable.h for the MicroBlaze port.
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30 *----------------------------------------------------------*/
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33 /* Scheduler includes. */
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34 #include "FreeRTOS.h"
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37 /* Standard includes. */
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40 /* Hardware includes. */
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41 #include <xintc_i.h>
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42 #include <xil_exception.h>
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43 #include <microblaze_exceptions_g.h>
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45 /* Tasks are started with a critical section nesting of 0 - however, prior to
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46 the scheduler being commenced interrupts should not be enabled, so the critical
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47 nesting variable is initialised to a non-zero value. */
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48 #define portINITIAL_NESTING_VALUE ( 0xff )
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50 /* The bit within the MSR register that enabled/disables interrupts and
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51 exceptions respectively. */
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52 #define portMSR_IE ( 0x02U )
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53 #define portMSR_EE ( 0x100U )
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55 /* If the floating point unit is included in the MicroBlaze build, then the
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56 FSR register is saved as part of the task context. portINITIAL_FSR is the value
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57 given to the FSR register when the initial context is set up for a task being
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59 #define portINITIAL_FSR ( 0U )
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61 /*-----------------------------------------------------------*/
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64 * Initialise the interrupt controller instance.
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66 static int32_t prvInitialiseInterruptController( void );
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68 /* Ensure the interrupt controller instance variable is initialised before it is
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69 * used, and that the initialisation only happens once.
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71 static int32_t prvEnsureInterruptControllerIsInitialised( void );
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73 /*-----------------------------------------------------------*/
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75 /* Counts the nesting depth of calls to portENTER_CRITICAL(). Each task
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76 maintains its own count, so this variable is saved as part of the task
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78 volatile UBaseType_t uxCriticalNesting = portINITIAL_NESTING_VALUE;
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80 /* This port uses a separate stack for interrupts. This prevents the stack of
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81 every task needing to be large enough to hold an entire interrupt stack on top
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82 of the task stack. */
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83 uint32_t *pulISRStack;
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85 /* If an interrupt requests a context switch, then ulTaskSwitchRequested will
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86 get set to 1. ulTaskSwitchRequested is inspected just before the main interrupt
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87 handler exits. If, at that time, ulTaskSwitchRequested is set to 1, the kernel
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88 will call vTaskSwitchContext() to ensure the task that runs immediately after
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89 the interrupt exists is the highest priority task that is able to run. This is
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90 an unusual mechanism, but is used for this port because a single interrupt can
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91 cause the servicing of multiple peripherals - and it is inefficient to call
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92 vTaskSwitchContext() multiple times as each peripheral is serviced. */
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93 volatile uint32_t ulTaskSwitchRequested = 0UL;
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95 /* The instance of the interrupt controller used by this port. This is required
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96 by the Xilinx library API functions. */
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97 static XIntc xInterruptControllerInstance;
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99 /*-----------------------------------------------------------*/
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102 * Initialise the stack of a task to look exactly as if a call to
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103 * portSAVE_CONTEXT had been made.
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105 * See the portable.h header file.
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107 StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
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109 extern void *_SDA2_BASE_, *_SDA_BASE_;
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110 const uint32_t ulR2 = ( uint32_t ) &_SDA2_BASE_;
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111 const uint32_t ulR13 = ( uint32_t ) &_SDA_BASE_;
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112 extern void _start1( void );
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114 /* Place a few bytes of known values on the bottom of the stack.
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115 This is essential for the Microblaze port and these lines must
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117 *pxTopOfStack = ( StackType_t ) 0x00000000;
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119 *pxTopOfStack = ( StackType_t ) 0x00000000;
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121 *pxTopOfStack = ( StackType_t ) 0x00000000;
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124 #if( XPAR_MICROBLAZE_USE_FPU != 0 )
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125 /* The FSR value placed in the initial task context is just 0. */
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126 *pxTopOfStack = portINITIAL_FSR;
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130 /* The MSR value placed in the initial task context should have interrupts
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131 disabled. Each task will enable interrupts automatically when it enters
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132 the running state for the first time. */
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133 *pxTopOfStack = mfmsr() & ~portMSR_IE;
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135 #if( MICROBLAZE_EXCEPTIONS_ENABLED == 1 )
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137 /* Ensure exceptions are enabled for the task. */
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138 *pxTopOfStack |= portMSR_EE;
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144 /* First stack an initial value for the critical section nesting. This
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145 is initialised to zero. */
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146 *pxTopOfStack = ( StackType_t ) 0x00;
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148 /* R0 is always zero. */
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149 /* R1 is the SP. */
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151 /* Place an initial value for all the general purpose registers. */
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153 *pxTopOfStack = ( StackType_t ) ulR2; /* R2 - read only small data area. */
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155 *pxTopOfStack = ( StackType_t ) 0x03; /* R3 - return values and temporaries. */
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157 *pxTopOfStack = ( StackType_t ) 0x04; /* R4 - return values and temporaries. */
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159 *pxTopOfStack = ( StackType_t ) pvParameters;/* R5 contains the function call parameters. */
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161 #ifdef portPRE_LOAD_STACK_FOR_DEBUGGING
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163 *pxTopOfStack = ( StackType_t ) 0x06; /* R6 - other parameters and temporaries. */
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165 *pxTopOfStack = ( StackType_t ) 0x07; /* R7 - other parameters and temporaries. */
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167 *pxTopOfStack = ( StackType_t ) NULL; /* R8 - other parameters and temporaries. */
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169 *pxTopOfStack = ( StackType_t ) 0x09; /* R9 - other parameters and temporaries. */
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171 *pxTopOfStack = ( StackType_t ) 0x0a; /* R10 - other parameters and temporaries. */
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173 *pxTopOfStack = ( StackType_t ) 0x0b; /* R11 - temporaries. */
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175 *pxTopOfStack = ( StackType_t ) 0x0c; /* R12 - temporaries. */
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181 *pxTopOfStack = ( StackType_t ) ulR13; /* R13 - read/write small data area. */
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183 *pxTopOfStack = ( StackType_t ) pxCode; /* R14 - return address for interrupt. */
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185 *pxTopOfStack = ( StackType_t ) _start1; /* R15 - return address for subroutine. */
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187 #ifdef portPRE_LOAD_STACK_FOR_DEBUGGING
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189 *pxTopOfStack = ( StackType_t ) 0x10; /* R16 - return address for trap (debugger). */
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191 *pxTopOfStack = ( StackType_t ) 0x11; /* R17 - return address for exceptions, if configured. */
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193 *pxTopOfStack = ( StackType_t ) 0x12; /* R18 - reserved for assembler and compiler temporaries. */
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199 *pxTopOfStack = ( StackType_t ) 0x00; /* R19 - must be saved across function calls. Callee-save. Seems to be interpreted as the frame pointer. */
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201 #ifdef portPRE_LOAD_STACK_FOR_DEBUGGING
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203 *pxTopOfStack = ( StackType_t ) 0x14; /* R20 - reserved for storing a pointer to the Global Offset Table (GOT) in Position Independent Code (PIC). Non-volatile in non-PIC code. Must be saved across function calls. Callee-save. Not used by FreeRTOS. */
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205 *pxTopOfStack = ( StackType_t ) 0x15; /* R21 - must be saved across function calls. Callee-save. */
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207 *pxTopOfStack = ( StackType_t ) 0x16; /* R22 - must be saved across function calls. Callee-save. */
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209 *pxTopOfStack = ( StackType_t ) 0x17; /* R23 - must be saved across function calls. Callee-save. */
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211 *pxTopOfStack = ( StackType_t ) 0x18; /* R24 - must be saved across function calls. Callee-save. */
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213 *pxTopOfStack = ( StackType_t ) 0x19; /* R25 - must be saved across function calls. Callee-save. */
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215 *pxTopOfStack = ( StackType_t ) 0x1a; /* R26 - must be saved across function calls. Callee-save. */
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217 *pxTopOfStack = ( StackType_t ) 0x1b; /* R27 - must be saved across function calls. Callee-save. */
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219 *pxTopOfStack = ( StackType_t ) 0x1c; /* R28 - must be saved across function calls. Callee-save. */
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221 *pxTopOfStack = ( StackType_t ) 0x1d; /* R29 - must be saved across function calls. Callee-save. */
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223 *pxTopOfStack = ( StackType_t ) 0x1e; /* R30 - must be saved across function calls. Callee-save. */
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225 *pxTopOfStack = ( StackType_t ) 0x1f; /* R31 - must be saved across function calls. Callee-save. */
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228 pxTopOfStack -= 13;
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231 /* Return a pointer to the top of the stack that has been generated so this
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232 can be stored in the task control block for the task. */
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233 return pxTopOfStack;
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235 /*-----------------------------------------------------------*/
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237 BaseType_t xPortStartScheduler( void )
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239 extern void ( vPortStartFirstTask )( void );
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240 extern uint32_t _stack[];
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242 /* Setup the hardware to generate the tick. Interrupts are disabled when
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243 this function is called.
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245 This port uses an application defined callback function to install the tick
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246 interrupt handler because the kernel will run on lots of different
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247 MicroBlaze and FPGA configurations - not all of which will have the same
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248 timer peripherals defined or available. An example definition of
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249 vApplicationSetupTimerInterrupt() is provided in the official demo
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250 application that accompanies this port. */
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251 vApplicationSetupTimerInterrupt();
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253 /* Reuse the stack from main() as the stack for the interrupts/exceptions. */
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254 pulISRStack = ( uint32_t * ) _stack;
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256 /* Ensure there is enough space for the functions called from the interrupt
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257 service routines to write back into the stack frame of the caller. */
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260 /* Restore the context of the first task that is going to run. From here
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261 on, the created tasks will be executing. */
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262 vPortStartFirstTask();
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264 /* Should not get here as the tasks are now running! */
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267 /*-----------------------------------------------------------*/
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269 void vPortEndScheduler( void )
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271 /* Not implemented in ports where there is nothing to return to.
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272 Artificially force an assert. */
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273 configASSERT( uxCriticalNesting == 1000UL );
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275 /*-----------------------------------------------------------*/
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278 * Manual context switch called by portYIELD or taskYIELD.
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280 void vPortYield( void )
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282 extern void VPortYieldASM( void );
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284 /* Perform the context switch in a critical section to assure it is
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285 not interrupted by the tick ISR. It is not a problem to do this as
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286 each task maintains its own interrupt status. */
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287 portENTER_CRITICAL();
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289 /* Jump directly to the yield function to ensure there is no
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290 compiler generated prologue code. */
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291 asm volatile ( "bralid r14, VPortYieldASM \n\t" \
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292 "or r0, r0, r0 \n\t" );
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294 portEXIT_CRITICAL();
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296 /*-----------------------------------------------------------*/
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298 void vPortEnableInterrupt( uint8_t ucInterruptID )
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302 /* An API function is provided to enable an interrupt in the interrupt
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303 controller because the interrupt controller instance variable is private
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305 lReturn = prvEnsureInterruptControllerIsInitialised();
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306 if( lReturn == pdPASS )
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308 /* Critical section protects read/modify/writer operation inside
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310 portENTER_CRITICAL();
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312 XIntc_Enable( &xInterruptControllerInstance, ucInterruptID );
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314 portEXIT_CRITICAL();
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317 configASSERT( lReturn );
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319 /*-----------------------------------------------------------*/
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321 void vPortDisableInterrupt( uint8_t ucInterruptID )
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325 /* An API function is provided to disable an interrupt in the interrupt
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326 controller because the interrupt controller instance variable is private
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328 lReturn = prvEnsureInterruptControllerIsInitialised();
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330 if( lReturn == pdPASS )
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332 XIntc_Disable( &xInterruptControllerInstance, ucInterruptID );
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335 configASSERT( lReturn );
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337 /*-----------------------------------------------------------*/
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339 BaseType_t xPortInstallInterruptHandler( uint8_t ucInterruptID, XInterruptHandler pxHandler, void *pvCallBackRef )
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343 /* An API function is provided to install an interrupt handler because the
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344 interrupt controller instance variable is private to this file. */
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346 lReturn = prvEnsureInterruptControllerIsInitialised();
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348 if( lReturn == pdPASS )
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350 lReturn = XIntc_Connect( &xInterruptControllerInstance, ucInterruptID, pxHandler, pvCallBackRef );
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353 if( lReturn == XST_SUCCESS )
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358 configASSERT( lReturn == pdPASS );
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362 /*-----------------------------------------------------------*/
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364 static int32_t prvEnsureInterruptControllerIsInitialised( void )
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366 static int32_t lInterruptControllerInitialised = pdFALSE;
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369 /* Ensure the interrupt controller instance variable is initialised before
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370 it is used, and that the initialisation only happens once. */
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371 if( lInterruptControllerInitialised != pdTRUE )
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373 lReturn = prvInitialiseInterruptController();
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375 if( lReturn == pdPASS )
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377 lInterruptControllerInitialised = pdTRUE;
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387 /*-----------------------------------------------------------*/
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390 * Handler for the timer interrupt. This is the handler that the application
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391 * defined callback function vApplicationSetupTimerInterrupt() should install.
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393 void vPortTickISR( void *pvUnused )
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395 extern void vApplicationClearTimerInterrupt( void );
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397 /* Ensure the unused parameter does not generate a compiler warning. */
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400 /* This port uses an application defined callback function to clear the tick
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401 interrupt because the kernel will run on lots of different MicroBlaze and
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402 FPGA configurations - not all of which will have the same timer peripherals
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403 defined or available. An example definition of
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404 vApplicationClearTimerInterrupt() is provided in the official demo
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405 application that accompanies this port. */
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406 vApplicationClearTimerInterrupt();
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408 /* Increment the RTOS tick - this might cause a task to unblock. */
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409 if( xTaskIncrementTick() != pdFALSE )
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411 /* Force vTaskSwitchContext() to be called as the interrupt exits. */
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412 ulTaskSwitchRequested = 1;
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415 /*-----------------------------------------------------------*/
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417 static int32_t prvInitialiseInterruptController( void )
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421 lStatus = XIntc_Initialize( &xInterruptControllerInstance, configINTERRUPT_CONTROLLER_TO_USE );
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423 if( lStatus == XST_SUCCESS )
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425 /* Initialise the exception table. */
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426 Xil_ExceptionInit();
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428 /* Service all pending interrupts each time the handler is entered. */
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429 XIntc_SetIntrSvcOption( xInterruptControllerInstance.BaseAddress, XIN_SVC_ALL_ISRS_OPTION );
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431 /* Install exception handlers if the MicroBlaze is configured to handle
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432 exceptions, and the application defined constant
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433 configINSTALL_EXCEPTION_HANDLERS is set to 1. */
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434 #if ( MICROBLAZE_EXCEPTIONS_ENABLED == 1 ) && ( configINSTALL_EXCEPTION_HANDLERS == 1 )
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436 vPortExceptionsInstallHandlers();
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438 #endif /* MICROBLAZE_EXCEPTIONS_ENABLED */
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440 /* Start the interrupt controller. Interrupts are enabled when the
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441 scheduler starts. */
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442 lStatus = XIntc_Start( &xInterruptControllerInstance, XIN_REAL_MODE );
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444 if( lStatus == XST_SUCCESS )
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454 configASSERT( lStatus == pdPASS );
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458 /*-----------------------------------------------------------*/
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