2 * FreeRTOS Kernel V10.0.0
\r
3 * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved.
\r
5 * Permission is hereby granted, free of charge, to any person obtaining a copy of
\r
6 * this software and associated documentation files (the "Software"), to deal in
\r
7 * the Software without restriction, including without limitation the rights to
\r
8 * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
\r
9 * the Software, and to permit persons to whom the Software is furnished to do so,
\r
10 * subject to the following conditions:
\r
12 * The above copyright notice and this permission notice shall be included in all
\r
13 * copies or substantial portions of the Software. If you wish to use our Amazon
\r
14 * FreeRTOS name, please do so in a fair use way that does not cause confusion.
\r
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
\r
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
\r
18 * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
\r
19 * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
\r
20 * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
\r
21 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
\r
23 * http://www.FreeRTOS.org
\r
24 * http://aws.amazon.com/freertos
\r
26 * 1 tab == 4 spaces!
\r
29 /* Scheduler includes. */
\r
30 #include "FreeRTOS.h"
\r
33 /* Hardware includes. */
\r
34 #include <microblaze_exceptions_i.h>
\r
35 #include <microblaze_exceptions_g.h>
\r
37 /* The Xilinx library defined exception entry point stacks a number of
\r
38 registers. These definitions are offsets from the stack pointer to the various
\r
39 stacked register values. */
\r
40 #define portexR3_STACK_OFFSET 4
\r
41 #define portexR4_STACK_OFFSET 5
\r
42 #define portexR5_STACK_OFFSET 6
\r
43 #define portexR6_STACK_OFFSET 7
\r
44 #define portexR7_STACK_OFFSET 8
\r
45 #define portexR8_STACK_OFFSET 9
\r
46 #define portexR9_STACK_OFFSET 10
\r
47 #define portexR10_STACK_OFFSET 11
\r
48 #define portexR11_STACK_OFFSET 12
\r
49 #define portexR12_STACK_OFFSET 13
\r
50 #define portexR15_STACK_OFFSET 16
\r
51 #define portexR18_STACK_OFFSET 19
\r
52 #define portexMSR_STACK_OFFSET 20
\r
53 #define portexR19_STACK_OFFSET -1
\r
55 /* This is defined to equal the size, in bytes, of the stack frame generated by
\r
56 the Xilinx standard library exception entry point. It is required to determine
\r
57 the stack pointer value prior to the exception being entered. */
\r
58 #define portexASM_HANDLER_STACK_FRAME_SIZE 84UL
\r
60 /* The number of bytes a MicroBlaze instruction consumes. */
\r
61 #define portexINSTRUCTION_SIZE 4
\r
63 /* Exclude this entire file if the MicroBlaze is not configured to handle
\r
64 exceptions, or the application defined configuration constant
\r
65 configINSTALL_EXCEPTION_HANDLERS is not set to 1. */
\r
66 #if ( MICROBLAZE_EXCEPTIONS_ENABLED == 1 ) && ( configINSTALL_EXCEPTION_HANDLERS == 1 )
\r
68 /* This variable is set in the exception entry code, before
\r
69 vPortExceptionHandler is called. */
\r
70 uint32_t *pulStackPointerOnFunctionEntry = NULL;
\r
72 /* This is the structure that is filled with the MicroBlaze context as it
\r
73 existed immediately prior to the exception occurrence. A pointer to this
\r
74 structure is passed into the vApplicationExceptionRegisterDump() callback
\r
75 function, if one is defined. */
\r
76 static xPortRegisterDump xRegisterDump;
\r
78 /* This is the FreeRTOS exception handler that is installed for all exception
\r
79 types. It is called from vPortExceptionHanlderEntry() - which is itself defined
\r
81 void vPortExceptionHandler( void *pvExceptionID );
\r
82 extern void vPortExceptionHandlerEntry( void *pvExceptionID );
\r
84 /*-----------------------------------------------------------*/
\r
86 /* vApplicationExceptionRegisterDump() is a callback function that the
\r
87 application can optionally define to receive a populated xPortRegisterDump
\r
88 structure. If the application chooses not to define a version of
\r
89 vApplicationExceptionRegisterDump() then this weekly defined default
\r
90 implementation will be called instead. */
\r
91 extern void vApplicationExceptionRegisterDump( xPortRegisterDump *xRegisterDump ) __attribute__((weak));
\r
92 void vApplicationExceptionRegisterDump( xPortRegisterDump *xRegisterDump )
\r
94 ( void ) xRegisterDump;
\r
101 /*-----------------------------------------------------------*/
\r
103 void vPortExceptionHandler( void *pvExceptionID )
\r
105 extern void *pxCurrentTCB;
\r
107 /* Fill an xPortRegisterDump structure with the MicroBlaze context as it
\r
108 was immediately before the exception occurrence. */
\r
110 /* First fill in the name and handle of the task that was in the Running
\r
111 state when the exception occurred. */
\r
112 xRegisterDump.xCurrentTaskHandle = pxCurrentTCB;
\r
113 xRegisterDump.pcCurrentTaskName = pcTaskGetName( NULL );
\r
115 configASSERT( pulStackPointerOnFunctionEntry );
\r
117 /* Obtain the values of registers that were stacked prior to this function
\r
118 being called, and may have changed since they were stacked. */
\r
119 xRegisterDump.ulR3 = pulStackPointerOnFunctionEntry[ portexR3_STACK_OFFSET ];
\r
120 xRegisterDump.ulR4 = pulStackPointerOnFunctionEntry[ portexR4_STACK_OFFSET ];
\r
121 xRegisterDump.ulR5 = pulStackPointerOnFunctionEntry[ portexR5_STACK_OFFSET ];
\r
122 xRegisterDump.ulR6 = pulStackPointerOnFunctionEntry[ portexR6_STACK_OFFSET ];
\r
123 xRegisterDump.ulR7 = pulStackPointerOnFunctionEntry[ portexR7_STACK_OFFSET ];
\r
124 xRegisterDump.ulR8 = pulStackPointerOnFunctionEntry[ portexR8_STACK_OFFSET ];
\r
125 xRegisterDump.ulR9 = pulStackPointerOnFunctionEntry[ portexR9_STACK_OFFSET ];
\r
126 xRegisterDump.ulR10 = pulStackPointerOnFunctionEntry[ portexR10_STACK_OFFSET ];
\r
127 xRegisterDump.ulR11 = pulStackPointerOnFunctionEntry[ portexR11_STACK_OFFSET ];
\r
128 xRegisterDump.ulR12 = pulStackPointerOnFunctionEntry[ portexR12_STACK_OFFSET ];
\r
129 xRegisterDump.ulR15_return_address_from_subroutine = pulStackPointerOnFunctionEntry[ portexR15_STACK_OFFSET ];
\r
130 xRegisterDump.ulR18 = pulStackPointerOnFunctionEntry[ portexR18_STACK_OFFSET ];
\r
131 xRegisterDump.ulR19 = pulStackPointerOnFunctionEntry[ portexR19_STACK_OFFSET ];
\r
132 xRegisterDump.ulMSR = pulStackPointerOnFunctionEntry[ portexMSR_STACK_OFFSET ];
\r
134 /* Obtain the value of all other registers. */
\r
135 xRegisterDump.ulR2_small_data_area = mfgpr( R2 );
\r
136 xRegisterDump.ulR13_read_write_small_data_area = mfgpr( R13 );
\r
137 xRegisterDump.ulR14_return_address_from_interrupt = mfgpr( R14 );
\r
138 xRegisterDump.ulR16_return_address_from_trap = mfgpr( R16 );
\r
139 xRegisterDump.ulR17_return_address_from_exceptions = mfgpr( R17 );
\r
140 xRegisterDump.ulR20 = mfgpr( R20 );
\r
141 xRegisterDump.ulR21 = mfgpr( R21 );
\r
142 xRegisterDump.ulR22 = mfgpr( R22 );
\r
143 xRegisterDump.ulR23 = mfgpr( R23 );
\r
144 xRegisterDump.ulR24 = mfgpr( R24 );
\r
145 xRegisterDump.ulR25 = mfgpr( R25 );
\r
146 xRegisterDump.ulR26 = mfgpr( R26 );
\r
147 xRegisterDump.ulR27 = mfgpr( R27 );
\r
148 xRegisterDump.ulR28 = mfgpr( R28 );
\r
149 xRegisterDump.ulR29 = mfgpr( R29 );
\r
150 xRegisterDump.ulR30 = mfgpr( R30 );
\r
151 xRegisterDump.ulR31 = mfgpr( R31 );
\r
152 xRegisterDump.ulR1_SP = ( ( uint32_t ) pulStackPointerOnFunctionEntry ) + portexASM_HANDLER_STACK_FRAME_SIZE;
\r
153 xRegisterDump.ulEAR = mfear();
\r
154 xRegisterDump.ulESR = mfesr();
\r
155 xRegisterDump.ulEDR = mfedr();
\r
157 /* Move the saved program counter back to the instruction that was executed
\r
158 when the exception occurred. This is only valid for certain types of
\r
160 xRegisterDump.ulPC = xRegisterDump.ulR17_return_address_from_exceptions - portexINSTRUCTION_SIZE;
\r
162 #if( XPAR_MICROBLAZE_USE_FPU != 0 )
\r
164 xRegisterDump.ulFSR = mffsr();
\r
168 xRegisterDump.ulFSR = 0UL;
\r
172 /* Also fill in a string that describes what type of exception this is.
\r
173 The string uses the same ID names as defined in the MicroBlaze standard
\r
174 library exception header files. */
\r
175 switch( ( uint32_t ) pvExceptionID )
\r
178 xRegisterDump.pcExceptionCause = ( int8_t * const ) "XEXC_ID_FSL";
\r
181 case XEXC_ID_UNALIGNED_ACCESS :
\r
182 xRegisterDump.pcExceptionCause = ( int8_t * const ) "XEXC_ID_UNALIGNED_ACCESS";
\r
185 case XEXC_ID_ILLEGAL_OPCODE :
\r
186 xRegisterDump.pcExceptionCause = ( int8_t * const ) "XEXC_ID_ILLEGAL_OPCODE";
\r
189 case XEXC_ID_M_AXI_I_EXCEPTION :
\r
190 xRegisterDump.pcExceptionCause = ( int8_t * const ) "XEXC_ID_M_AXI_I_EXCEPTION or XEXC_ID_IPLB_EXCEPTION";
\r
193 case XEXC_ID_M_AXI_D_EXCEPTION :
\r
194 xRegisterDump.pcExceptionCause = ( int8_t * const ) "XEXC_ID_M_AXI_D_EXCEPTION or XEXC_ID_DPLB_EXCEPTION";
\r
197 case XEXC_ID_DIV_BY_ZERO :
\r
198 xRegisterDump.pcExceptionCause = ( int8_t * const ) "XEXC_ID_DIV_BY_ZERO";
\r
201 case XEXC_ID_STACK_VIOLATION :
\r
202 xRegisterDump.pcExceptionCause = ( int8_t * const ) "XEXC_ID_STACK_VIOLATION or XEXC_ID_MMU";
\r
205 #if( XPAR_MICROBLAZE_USE_FPU != 0 )
\r
208 xRegisterDump.pcExceptionCause = ( int8_t * const ) "XEXC_ID_FPU see ulFSR value";
\r
211 #endif /* XPAR_MICROBLAZE_USE_FPU */
\r
214 /* vApplicationExceptionRegisterDump() is a callback function that the
\r
215 application can optionally define to receive the populated xPortRegisterDump
\r
216 structure. If the application chooses not to define a version of
\r
217 vApplicationExceptionRegisterDump() then the weekly defined default
\r
218 implementation within this file will be called instead. */
\r
219 vApplicationExceptionRegisterDump( &xRegisterDump );
\r
221 /* Must not attempt to leave this function! */
\r
227 /*-----------------------------------------------------------*/
\r
229 void vPortExceptionsInstallHandlers( void )
\r
231 static uint32_t ulHandlersAlreadyInstalled = pdFALSE;
\r
233 if( ulHandlersAlreadyInstalled == pdFALSE )
\r
235 ulHandlersAlreadyInstalled = pdTRUE;
\r
237 #if XPAR_MICROBLAZE_UNALIGNED_EXCEPTIONS == 1
\r
238 microblaze_register_exception_handler( XEXC_ID_UNALIGNED_ACCESS, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_UNALIGNED_ACCESS );
\r
239 #endif /* XPAR_MICROBLAZE_UNALIGNED_EXCEPTIONS*/
\r
241 #if XPAR_MICROBLAZE_ILL_OPCODE_EXCEPTION == 1
\r
242 microblaze_register_exception_handler( XEXC_ID_ILLEGAL_OPCODE, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_ILLEGAL_OPCODE );
\r
243 #endif /* XPAR_MICROBLAZE_ILL_OPCODE_EXCEPTION */
\r
245 #if XPAR_MICROBLAZE_M_AXI_I_BUS_EXCEPTION == 1
\r
246 microblaze_register_exception_handler( XEXC_ID_M_AXI_I_EXCEPTION, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_M_AXI_I_EXCEPTION );
\r
247 #endif /* XPAR_MICROBLAZE_M_AXI_I_BUS_EXCEPTION */
\r
249 #if XPAR_MICROBLAZE_M_AXI_D_BUS_EXCEPTION == 1
\r
250 microblaze_register_exception_handler( XEXC_ID_M_AXI_D_EXCEPTION, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_M_AXI_D_EXCEPTION );
\r
251 #endif /* XPAR_MICROBLAZE_M_AXI_D_BUS_EXCEPTION */
\r
253 #if XPAR_MICROBLAZE_IPLB_BUS_EXCEPTION == 1
\r
254 microblaze_register_exception_handler( XEXC_ID_IPLB_EXCEPTION, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_IPLB_EXCEPTION );
\r
255 #endif /* XPAR_MICROBLAZE_IPLB_BUS_EXCEPTION */
\r
257 #if XPAR_MICROBLAZE_DPLB_BUS_EXCEPTION == 1
\r
258 microblaze_register_exception_handler( XEXC_ID_DPLB_EXCEPTION, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_DPLB_EXCEPTION );
\r
259 #endif /* XPAR_MICROBLAZE_DPLB_BUS_EXCEPTION */
\r
261 #if XPAR_MICROBLAZE_DIV_ZERO_EXCEPTION == 1
\r
262 microblaze_register_exception_handler( XEXC_ID_DIV_BY_ZERO, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_DIV_BY_ZERO );
\r
263 #endif /* XPAR_MICROBLAZE_DIV_ZERO_EXCEPTION */
\r
265 #if XPAR_MICROBLAZE_FPU_EXCEPTION == 1
\r
266 microblaze_register_exception_handler( XEXC_ID_FPU, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_FPU );
\r
267 #endif /* XPAR_MICROBLAZE_FPU_EXCEPTION */
\r
269 #if XPAR_MICROBLAZE_FSL_EXCEPTION == 1
\r
270 microblaze_register_exception_handler( XEXC_ID_FSL, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_FSL );
\r
271 #endif /* XPAR_MICROBLAZE_FSL_EXCEPTION */
\r
273 microblaze_enable_exceptions();
\r
277 /* Exclude the entire file if the MicroBlaze is not configured to handle
\r
278 exceptions, or the application defined configuration item
\r
279 configINSTALL_EXCEPTION_HANDLERS is not set to 1. */
\r
280 #endif /* ( MICROBLAZE_EXCEPTIONS_ENABLED == 1 ) && ( configINSTALL_EXCEPTION_HANDLERS == 1 ) */
\r