git.sur5r.net Git - freertos/blob - FreeRTOS/Source/portable/GCC/NiosII/port_asm.S

   1 /*\r
   2     FreeRTOS V7.5.0 - Copyright (C) 2013 Real Time Engineers Ltd.\r
   3 \r
   4     VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
   5 \r
   6     ***************************************************************************\r
   7      *                                                                       *\r
   8      *    FreeRTOS provides completely free yet professionally developed,    *\r
   9      *    robust, strictly quality controlled, supported, and cross          *\r
  10      *    platform software that has become a de facto standard.             *\r
  11      *                                                                       *\r
  12      *    Help yourself get started quickly and support the FreeRTOS         *\r
  13      *    project by purchasing a FreeRTOS tutorial book, reference          *\r
  14      *    manual, or both from: http://www.FreeRTOS.org/Documentation        *\r
  15      *                                                                       *\r
  16      *    Thank you!                                                         *\r
  17      *                                                                       *\r
  18     ***************************************************************************\r
  19 \r
  20     This file is part of the FreeRTOS distribution.\r
  21 \r
  22     FreeRTOS is free software; you can redistribute it and/or modify it under\r
  23     the terms of the GNU General Public License (version 2) as published by the\r
  24     Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.\r
  25 \r
  26     >>! NOTE: The modification to the GPL is included to allow you to distribute\r
  27     >>! a combined work that includes FreeRTOS without being obliged to provide\r
  28     >>! the source code for proprietary components outside of the FreeRTOS\r
  29     >>! kernel.\r
  30 \r
  31     FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
  32     WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
  33     FOR A PARTICULAR PURPOSE.  Full license text is available from the following\r
  34     link: http://www.freertos.org/a00114.html\r
  35 \r
  36     1 tab == 4 spaces!\r
  37 \r
  38     ***************************************************************************\r
  39      *                                                                       *\r
  40      *    Having a problem?  Start by reading the FAQ "My application does   *\r
  41      *    not run, what could be wrong?"                                     *\r
  42      *                                                                       *\r
  43      *    http://www.FreeRTOS.org/FAQHelp.html                               *\r
  44      *                                                                       *\r
  45     ***************************************************************************\r
  46 \r
  47     http://www.FreeRTOS.org - Documentation, books, training, latest versions,\r
  48     license and Real Time Engineers Ltd. contact details.\r
  49 \r
  50     http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
  51     including FreeRTOS+Trace - an indispensable productivity tool, a DOS\r
  52     compatible FAT file system, and our tiny thread aware UDP/IP stack.\r
  53 \r
  54     http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High\r
  55     Integrity Systems to sell under the OpenRTOS brand.  Low cost OpenRTOS\r
  56     licenses offer ticketed support, indemnification and middleware.\r
  57 \r
  58     http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
  59     engineered and independently SIL3 certified version for use in safety and\r
  60     mission critical applications that require provable dependability.\r
  61 \r
  62     1 tab == 4 spaces!\r
  63 */\r
  64 \r
  65 .extern         vTaskSwitchContext\r
  66         \r
  67 .set noat\r
  68 \r
  69 # Exported to start the first task.\r
  70 .globl restore_sp_from_pxCurrentTCB             \r
  71         \r
  72 # Entry point for exceptions.\r
  73 .section .exceptions.entry, "xa"                \r
  74 \r
  75 # Save the entire context of a task.\r
  76 save_context:\r
  77         addi    ea, ea, -4                      # Point to the next instruction.\r
  78         addi    sp,     sp, -116                # Create space on the stack.\r
  79         stw             ra, 0(sp)\r
  80                                                                 # Leave a gap for muldiv 0\r
  81         stw             at, 8(sp)                \r
  82         stw             r2, 12(sp)\r
  83         stw             r3, 16(sp)\r
  84         stw             r4, 20(sp)\r
  85         stw             r5, 24(sp) \r
  86         stw             r6, 28(sp) \r
  87         stw             r7, 32(sp) \r
  88         stw             r8, 36(sp) \r
  89         stw             r9, 40(sp) \r
  90         stw             r10, 44(sp)\r
  91         stw             r11, 48(sp)\r
  92         stw             r12, 52(sp)\r
  93         stw             r13, 56(sp)\r
  94         stw             r14, 60(sp)\r
  95         stw             r15, 64(sp)\r
  96         rdctl   r5, estatus             # Save the eStatus\r
  97         stw             r5, 68(sp)\r
  98         stw             ea, 72(sp)                      # Save the PC\r
  99         stw             r16, 76(sp)                     # Save the remaining registers\r
 100         stw             r17, 80(sp)\r
 101         stw             r18, 84(sp)\r
 102         stw             r19, 88(sp)\r
 103         stw             r20, 92(sp)\r
 104         stw             r21, 96(sp)\r
 105         stw             r22, 100(sp)\r
 106         stw             r23, 104(sp)\r
 107         stw             gp, 108(sp)\r
 108         stw             fp, 112(sp)\r
 109 \r
 110 save_sp_to_pxCurrentTCB:\r
 111         movia   et, pxCurrentTCB        # Load the address of the pxCurrentTCB pointer\r
 112         ldw             et, (et)                        # Load the value of the pxCurrentTCB pointer\r
 113         stw             sp, (et)                        # Store the stack pointer into the top of the TCB\r
 114         \r
 115         .section .exceptions.irqtest, "xa"      \r
 116 hw_irq_test:\r
 117         /*\r
 118      * Test to see if the exception was a software exception or caused \r
 119      * by an external interrupt, and vector accordingly.\r
 120      */\r
 121     rdctl       r4, ipending            # Load the Pending Interrupts indication\r
 122         rdctl   r5, estatus             # Load the eStatus (enabled interrupts).\r
 123     andi        r2, r5, 1                       # Are interrupts enabled globally.\r
 124     beq         r2, zero, soft_exceptions               # Interrupts are not enabled.\r
 125     beq         r4, zero, soft_exceptions               # There are no interrupts triggered.\r
 126 \r
 127         .section .exceptions.irqhandler, "xa"\r
 128 hw_irq_handler:\r
 129         call    alt_irq_handler                                 # Call the alt_irq_handler to deliver to the registered interrupt handler.\r
 130 \r
 131     .section .exceptions.irqreturn, "xa"\r
 132 restore_sp_from_pxCurrentTCB:\r
 133         movia   et, pxCurrentTCB                # Load the address of the pxCurrentTCB pointer\r
 134         ldw             et, (et)                                # Load the value of the pxCurrentTCB pointer\r
 135         ldw             sp, (et)                                # Load the stack pointer with the top value of the TCB\r
 136 \r
 137 restore_context:\r
 138         ldw             ra, 0(sp)               # Restore the registers.\r
 139                                                         # Leave a gap for muldiv 0.\r
 140         ldw             at, 8(sp)\r
 141         ldw             r2, 12(sp)\r
 142         ldw             r3, 16(sp)\r
 143         ldw             r4, 20(sp)\r
 144         ldw             r5, 24(sp) \r
 145         ldw             r6, 28(sp) \r
 146         ldw             r7, 32(sp) \r
 147         ldw             r8, 36(sp) \r
 148         ldw             r9, 40(sp) \r
 149         ldw             r10, 44(sp)\r
 150         ldw             r11, 48(sp)\r
 151         ldw             r12, 52(sp)\r
 152         ldw             r13, 56(sp)\r
 153         ldw             r14, 60(sp)\r
 154         ldw             r15, 64(sp)\r
 155         ldw             et, 68(sp)              # Load the eStatus\r
 156         wrctl   estatus, et     # Write the eStatus\r
 157         ldw             ea, 72(sp)              # Load the Program Counter\r
 158         ldw             r16, 76(sp)\r
 159         ldw             r17, 80(sp)\r
 160         ldw             r18, 84(sp)\r
 161         ldw             r19, 88(sp)\r
 162         ldw             r20, 92(sp)\r
 163         ldw             r21, 96(sp)\r
 164         ldw             r22, 100(sp)\r
 165         ldw             r23, 104(sp)\r
 166         ldw             gp, 108(sp)\r
 167         ldw             fp, 112(sp)\r
 168         addi    sp,     sp, 116         # Release stack space\r
 169 \r
 170     eret                                        # Return to address ea, loading eStatus into Status.\r
 171    \r
 172         .section .exceptions.soft, "xa"\r
 173 soft_exceptions:\r
 174         ldw             et, 0(ea)                               # Load the instruction where the interrupt occured.\r
 175         movhi   at, %hi(0x003B683A)             # Load the registers with the trap instruction code\r
 176         ori             at, at, %lo(0x003B683A)\r
 177         cmpne   et, et, at                              # Compare the trap instruction code to the last excuted instruction\r
 178         beq             et, r0, call_scheduler  # its a trap so switchcontext\r
 179         break                                                   # This is an un-implemented instruction or muldiv problem.\r
 180         br              restore_context                 # its something else\r
 181 \r
 182 call_scheduler:\r
 183         addi    ea, ea, 4                                               # A trap was called, increment the program counter so it is not called again.\r
 184         stw             ea, 72(sp)                                              # Save the new program counter to the context.\r
 185         call    vTaskSwitchContext                              # Pick the next context.\r
 186         br              restore_sp_from_pxCurrentTCB    # Switch in the task context and restore. \r