2 * FreeRTOS Kernel V10.0.0
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3 * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved.
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5 * Permission is hereby granted, free of charge, to any person obtaining a copy of
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6 * this software and associated documentation files (the "Software"), to deal in
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7 * the Software without restriction, including without limitation the rights to
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8 * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
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9 * the Software, and to permit persons to whom the Software is furnished to do so,
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10 * subject to the following conditions:
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12 * The above copyright notice and this permission notice shall be included in all
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13 * copies or substantial portions of the Software. If you wish to use our Amazon
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14 * FreeRTOS name, please do so in a fair use way that does not cause confusion.
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16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
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18 * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
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19 * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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20 * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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21 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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23 * http://www.FreeRTOS.org
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24 * http://aws.amazon.com/freertos
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26 * 1 tab == 4 spaces!
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29 /*-----------------------------------------------------------
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30 * Implementation of functions defined in portable.h for the PPC405 port.
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31 *----------------------------------------------------------*/
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34 /* Scheduler includes. */
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35 #include "FreeRTOS.h"
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38 /* Library includes. */
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39 #include "xtime_l.h"
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41 #include "xintc_i.h"
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43 /*-----------------------------------------------------------*/
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45 /* Definitions to set the initial MSR of each task. */
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46 #define portCRITICAL_INTERRUPT_ENABLE ( 1UL << 17UL )
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47 #define portEXTERNAL_INTERRUPT_ENABLE ( 1UL << 15UL )
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48 #define portMACHINE_CHECK_ENABLE ( 1UL << 12UL )
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50 #if configUSE_FPU == 1
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51 #define portAPU_PRESENT ( 1UL << 25UL )
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52 #define portFCM_FPU_PRESENT ( 1UL << 13UL )
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54 #define portAPU_PRESENT ( 0UL )
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55 #define portFCM_FPU_PRESENT ( 0UL )
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58 #define portINITIAL_MSR ( portCRITICAL_INTERRUPT_ENABLE | portEXTERNAL_INTERRUPT_ENABLE | portMACHINE_CHECK_ENABLE | portAPU_PRESENT | portFCM_FPU_PRESENT )
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61 extern const unsigned _SDA_BASE_;
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62 extern const unsigned _SDA2_BASE_;
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64 /*-----------------------------------------------------------*/
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67 * Setup the system timer to generate the tick interrupt.
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69 static void prvSetupTimerInterrupt( void );
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72 * The handler for the tick interrupt - defined in portasm.s.
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74 extern void vPortTickISR( void );
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77 * The handler for the yield function - defined in portasm.s.
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79 extern void vPortYield( void );
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82 * Function to start the scheduler running by starting the highest
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83 * priority task that has thus far been created.
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85 extern void vPortStartFirstTask( void );
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87 /*-----------------------------------------------------------*/
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89 /* Structure used to hold the state of the interrupt controller. */
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90 static XIntc xInterruptController;
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92 /*-----------------------------------------------------------*/
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95 * Initialise the stack of a task to look exactly as if the task had been
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98 * See the header file portable.h.
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100 StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
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102 /* Place a known value at the bottom of the stack for debugging. */
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103 *pxTopOfStack = 0xDEADBEEF;
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106 /* EABI stack frame. */
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107 pxTopOfStack -= 20; /* Previous backchain and LR, R31 to R4 inclusive. */
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109 /* Parameters in R13. */
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110 *pxTopOfStack = ( StackType_t ) &_SDA_BASE_; /* address of the first small data area */
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111 pxTopOfStack -= 10;
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113 /* Parameters in R3. */
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114 *pxTopOfStack = ( StackType_t ) pvParameters;
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117 /* Parameters in R2. */
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118 *pxTopOfStack = ( StackType_t ) &_SDA2_BASE_; /* address of the second small data area */
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121 /* R1 is the stack pointer so is omitted. */
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123 *pxTopOfStack = 0x10000001UL;; /* R0. */
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125 *pxTopOfStack = 0x00000000UL; /* USPRG0. */
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127 *pxTopOfStack = 0x00000000UL; /* CR. */
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129 *pxTopOfStack = 0x00000000UL; /* XER. */
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131 *pxTopOfStack = 0x00000000UL; /* CTR. */
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133 *pxTopOfStack = ( StackType_t ) vPortEndScheduler; /* LR. */
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135 *pxTopOfStack = ( StackType_t ) pxCode; /* SRR0. */
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137 *pxTopOfStack = portINITIAL_MSR;/* SRR1. */
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139 *pxTopOfStack = ( StackType_t ) vPortEndScheduler;/* Next LR. */
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141 *pxTopOfStack = 0x00000000UL;/* Backchain. */
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143 return pxTopOfStack;
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145 /*-----------------------------------------------------------*/
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147 BaseType_t xPortStartScheduler( void )
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149 prvSetupTimerInterrupt();
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150 XExc_RegisterHandler( XEXC_ID_SYSTEM_CALL, ( XExceptionHandler ) vPortYield, ( void * ) 0 );
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151 vPortStartFirstTask();
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153 /* Should not get here as the tasks are now running! */
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156 /*-----------------------------------------------------------*/
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158 void vPortEndScheduler( void )
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160 /* Not implemented. */
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163 /*-----------------------------------------------------------*/
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166 * Hardware initialisation to generate the RTOS tick.
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168 static void prvSetupTimerInterrupt( void )
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170 const uint32_t ulInterval = ( ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL );
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172 XTime_PITClearInterrupt();
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173 XTime_FITClearInterrupt();
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174 XTime_WDTClearInterrupt();
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175 XTime_WDTDisableInterrupt();
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176 XTime_FITDisableInterrupt();
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178 XExc_RegisterHandler( XEXC_ID_PIT_INT, ( XExceptionHandler ) vPortTickISR, ( void * ) 0 );
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180 XTime_PITEnableAutoReload();
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181 XTime_PITSetInterval( ulInterval );
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182 XTime_PITEnableInterrupt();
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184 /*-----------------------------------------------------------*/
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186 void vPortISRHandler( void *pvNullDoNotUse )
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188 uint32_t ulInterruptStatus, ulInterruptMask = 1UL;
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189 BaseType_t xInterruptNumber;
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190 XIntc_Config *pxInterruptController;
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191 XIntc_VectorTableEntry *pxTable;
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193 /* Just to remove compiler warning. */
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194 ( void ) pvNullDoNotUse;
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196 /* Get the configuration by using the device ID - in this case it is
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197 assumed that only one interrupt controller is being used. */
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198 pxInterruptController = &XIntc_ConfigTable[ XPAR_XPS_INTC_0_DEVICE_ID ];
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200 /* Which interrupts are pending? */
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201 ulInterruptStatus = XIntc_mGetIntrStatus( pxInterruptController->BaseAddress );
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203 for( xInterruptNumber = 0; xInterruptNumber < XPAR_INTC_MAX_NUM_INTR_INPUTS; xInterruptNumber++ )
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205 if( ulInterruptStatus & 0x01UL )
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207 /* Clear the pending interrupt. */
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208 XIntc_mAckIntr( pxInterruptController->BaseAddress, ulInterruptMask );
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210 /* Call the registered handler. */
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211 pxTable = &( pxInterruptController->HandlerTable[ xInterruptNumber ] );
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212 pxTable->Handler( pxTable->CallBackRef );
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215 /* Check the next interrupt. */
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216 ulInterruptMask <<= 0x01UL;
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217 ulInterruptStatus >>= 0x01UL;
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219 /* Have we serviced all interrupts? */
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220 if( ulInterruptStatus == 0UL )
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226 /*-----------------------------------------------------------*/
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228 void vPortSetupInterruptController( void )
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230 extern void vPortISRWrapper( void );
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232 /* Perform all library calls necessary to initialise the exception table
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233 and interrupt controller. This assumes only one interrupt controller is in
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235 XExc_mDisableExceptions( XEXC_NON_CRITICAL );
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238 /* The library functions save the context - we then jump to a wrapper to
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239 save the stack into the TCB. The wrapper then calls the handler defined
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241 XExc_RegisterHandler( XEXC_ID_NON_CRITICAL_INT, ( XExceptionHandler ) vPortISRWrapper, NULL );
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242 XIntc_Initialize( &xInterruptController, XPAR_XPS_INTC_0_DEVICE_ID );
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243 XIntc_Start( &xInterruptController, XIN_REAL_MODE );
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245 /*-----------------------------------------------------------*/
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247 BaseType_t xPortInstallInterruptHandler( uint8_t ucInterruptID, XInterruptHandler pxHandler, void *pvCallBackRef )
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249 BaseType_t xReturn = pdFAIL;
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251 /* This function is defined here so the scope of xInterruptController can
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252 remain within this file. */
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254 if( XST_SUCCESS == XIntc_Connect( &xInterruptController, ucInterruptID, pxHandler, pvCallBackRef ) )
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256 XIntc_Enable( &xInterruptController, ucInterruptID );
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