2 * FreeRTOS Kernel V10.0.0
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3 * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved.
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5 * Permission is hereby granted, free of charge, to any person obtaining a copy of
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6 * this software and associated documentation files (the "Software"), to deal in
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7 * the Software without restriction, including without limitation the rights to
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8 * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
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9 * the Software, and to permit persons to whom the Software is furnished to do so,
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10 * subject to the following conditions:
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12 * The above copyright notice and this permission notice shall be included in all
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13 * copies or substantial portions of the Software. If you wish to use our Amazon
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14 * FreeRTOS name, please do so in a fair use way that does not cause confusion.
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16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
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18 * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
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19 * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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20 * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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21 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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23 * http://www.FreeRTOS.org
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24 * http://aws.amazon.com/freertos
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26 * 1 tab == 4 spaces!
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29 /*-----------------------------------------------------------
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30 * Implementation of functions defined in portable.h for the SH2A port.
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31 *----------------------------------------------------------*/
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33 /* Standard C includes. */
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36 /* Scheduler includes. */
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37 #include "FreeRTOS.h"
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40 /* Library includes. */
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43 /* Hardware specifics. */
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44 #include "iodefine.h"
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46 /*-----------------------------------------------------------*/
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48 /* Tasks should start with interrupts enabled and in Supervisor mode, therefore
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49 PSW is set with U and I set, and PM and IPL clear. */
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50 #define portINITIAL_PSW ( ( StackType_t ) 0x00030000 )
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52 /* The peripheral clock is divided by this value before being supplying the
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54 #if ( configUSE_TICKLESS_IDLE == 0 )
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55 /* If tickless idle is not used then the divisor can be fixed. */
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56 #define portCLOCK_DIVISOR 8UL
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57 #elif ( configPERIPHERAL_CLOCK_HZ >= 12000000 )
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58 #define portCLOCK_DIVISOR 512UL
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59 #elif ( configPERIPHERAL_CLOCK_HZ >= 6000000 )
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60 #define portCLOCK_DIVISOR 128UL
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61 #elif ( configPERIPHERAL_CLOCK_HZ >= 1000000 )
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62 #define portCLOCK_DIVISOR 32UL
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64 #define portCLOCK_DIVISOR 8UL
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67 /* These macros allow a critical section to be added around the call to
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68 xTaskIncrementTick(), which is only ever called from interrupts at the kernel
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69 priority - ie a known priority. Therefore these local macros are a slight
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70 optimisation compared to calling the global SET/CLEAR_INTERRUPT_MASK macros,
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71 which would require the old IPL to be read first and stored in a local variable. */
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72 #define portDISABLE_INTERRUPTS_FROM_KERNEL_ISR() __asm volatile ( "MVTIPL %0" ::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY) )
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73 #define portENABLE_INTERRUPTS_FROM_KERNEL_ISR() __asm volatile ( "MVTIPL %0" ::"i"(configKERNEL_INTERRUPT_PRIORITY) )
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75 /* Keys required to lock and unlock access to certain system registers
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77 #define portUNLOCK_KEY 0xA50B
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78 #define portLOCK_KEY 0xA500
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80 /*-----------------------------------------------------------*/
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83 * Function to start the first task executing - written in asm code as direct
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84 * access to registers is required.
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86 static void prvStartFirstTask( void ) __attribute__((naked));
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89 * Software interrupt handler. Performs the actual context switch (saving and
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90 * restoring of registers). Written in asm code as direct register access is
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93 void vPortSoftwareInterruptISR( void ) __attribute__((naked));
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96 * The tick interrupt handler.
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98 void vPortTickISR( void ) __attribute__((interrupt));
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101 * Sets up the periodic ISR used for the RTOS tick using the CMT.
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102 * The application writer can define configSETUP_TICK_INTERRUPT() (in
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103 * FreeRTOSConfig.h) such that their own tick interrupt configuration is used
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104 * in place of prvSetupTimerInterrupt().
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106 static void prvSetupTimerInterrupt( void );
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107 #ifndef configSETUP_TICK_INTERRUPT
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108 /* The user has not provided their own tick interrupt configuration so use
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109 the definition in this file (which uses the interval timer). */
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110 #define configSETUP_TICK_INTERRUPT() prvSetupTimerInterrupt()
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111 #endif /* configSETUP_TICK_INTERRUPT */
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114 * Called after the sleep mode registers have been configured, prvSleep()
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115 * executes the pre and post sleep macros, and actually calls the wait
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118 #if configUSE_TICKLESS_IDLE == 1
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119 static void prvSleep( TickType_t xExpectedIdleTime );
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120 #endif /* configUSE_TICKLESS_IDLE */
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122 /*-----------------------------------------------------------*/
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124 /* Used in the context save and restore code. */
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125 extern void *pxCurrentTCB;
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127 /* Calculate how many clock increments make up a single tick period. */
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128 static const uint32_t ulMatchValueForOneTick = ( ( configPERIPHERAL_CLOCK_HZ / portCLOCK_DIVISOR ) / configTICK_RATE_HZ );
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130 #if configUSE_TICKLESS_IDLE == 1
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132 /* Holds the maximum number of ticks that can be suppressed - which is
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133 basically how far into the future an interrupt can be generated. Set
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134 during initialisation. This is the maximum possible value that the
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135 compare match register can hold divided by ulMatchValueForOneTick. */
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136 static const TickType_t xMaximumPossibleSuppressedTicks = USHRT_MAX / ( ( configPERIPHERAL_CLOCK_HZ / portCLOCK_DIVISOR ) / configTICK_RATE_HZ );
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138 /* Flag set from the tick interrupt to allow the sleep processing to know if
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139 sleep mode was exited because of a tick interrupt, or an interrupt
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140 generated by something else. */
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141 static volatile uint32_t ulTickFlag = pdFALSE;
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143 /* The CMT counter is stopped temporarily each time it is re-programmed.
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144 The following constant offsets the CMT counter match value by the number of
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145 CMT counts that would typically be missed while the counter was stopped to
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146 compensate for the lost time. The large difference between the divided CMT
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147 clock and the CPU clock means it is likely ulStoppedTimerCompensation will
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148 equal zero - and be optimised away. */
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149 static const uint32_t ulStoppedTimerCompensation = 100UL / ( configCPU_CLOCK_HZ / ( configPERIPHERAL_CLOCK_HZ / portCLOCK_DIVISOR ) );
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153 /*-----------------------------------------------------------*/
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156 * See header file for description.
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158 StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
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160 /* Offset to end up on 8 byte boundary. */
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163 /* R0 is not included as it is the stack pointer. */
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164 *pxTopOfStack = 0x00;
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166 *pxTopOfStack = 0x00;
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168 *pxTopOfStack = portINITIAL_PSW;
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170 *pxTopOfStack = ( StackType_t ) pxCode;
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172 /* When debugging it can be useful if every register is set to a known
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173 value. Otherwise code space can be saved by just setting the registers
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174 that need to be set. */
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175 #ifdef USE_FULL_REGISTER_INITIALISATION
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178 *pxTopOfStack = 0x12345678; /* r15. */
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180 *pxTopOfStack = 0xaaaabbbb;
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182 *pxTopOfStack = 0xdddddddd;
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184 *pxTopOfStack = 0xcccccccc;
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186 *pxTopOfStack = 0xbbbbbbbb;
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188 *pxTopOfStack = 0xaaaaaaaa;
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190 *pxTopOfStack = 0x99999999;
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192 *pxTopOfStack = 0x88888888;
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194 *pxTopOfStack = 0x77777777;
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196 *pxTopOfStack = 0x66666666;
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198 *pxTopOfStack = 0x55555555;
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200 *pxTopOfStack = 0x44444444;
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202 *pxTopOfStack = 0x33333333;
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204 *pxTopOfStack = 0x22222222;
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209 /* Leave space for the registers that will get popped from the stack
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210 when the task first starts executing. */
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211 pxTopOfStack -= 15;
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215 *pxTopOfStack = ( StackType_t ) pvParameters; /* R1 */
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217 *pxTopOfStack = 0x12345678; /* Accumulator. */
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219 *pxTopOfStack = 0x87654321; /* Accumulator. */
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221 return pxTopOfStack;
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223 /*-----------------------------------------------------------*/
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225 BaseType_t xPortStartScheduler( void )
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227 /* Use pxCurrentTCB just so it does not get optimised away. */
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228 if( pxCurrentTCB != NULL )
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230 /* Call an application function to set up the timer that will generate
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231 the tick interrupt. This way the application can decide which
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232 peripheral to use. If tickless mode is used then the default
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233 implementation defined in this file (which uses CMT0) should not be
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235 configSETUP_TICK_INTERRUPT();
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237 /* Enable the software interrupt. */
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238 _IEN( _ICU_SWINT ) = 1;
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240 /* Ensure the software interrupt is clear. */
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241 _IR( _ICU_SWINT ) = 0;
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243 /* Ensure the software interrupt is set to the kernel priority. */
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244 _IPR( _ICU_SWINT ) = configKERNEL_INTERRUPT_PRIORITY;
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246 /* Start the first task. */
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247 prvStartFirstTask();
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250 /* Execution should not reach here as the tasks are now running!
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251 prvSetupTimerInterrupt() is called here to prevent the compiler outputting
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252 a warning about a statically declared function not being referenced in the
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253 case that the application writer has provided their own tick interrupt
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254 configuration routine (and defined configSETUP_TICK_INTERRUPT() such that
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255 their own routine will be called in place of prvSetupTimerInterrupt()). */
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256 prvSetupTimerInterrupt();
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258 /* Should not get here. */
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261 /*-----------------------------------------------------------*/
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263 void vPortEndScheduler( void )
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265 /* Not implemented in ports where there is nothing to return to.
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266 Artificially force an assert. */
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267 configASSERT( pxCurrentTCB == NULL );
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269 /*-----------------------------------------------------------*/
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271 static void prvStartFirstTask( void )
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275 /* When starting the scheduler there is nothing that needs moving to the
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276 interrupt stack because the function is not called from an interrupt.
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277 Just ensure the current stack is the user stack. */
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280 /* Obtain the location of the stack associated with which ever task
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281 pxCurrentTCB is currently pointing to. */
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282 "MOV.L #_pxCurrentTCB, R15 \n" \
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283 "MOV.L [R15], R15 \n" \
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284 "MOV.L [R15], R0 \n" \
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286 /* Restore the registers from the stack of the task pointed to by
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290 /* Accumulator low 32 bits. */
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294 /* Accumulator high 32 bits. */
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297 /* R1 to R15 - R0 is not included as it is the SP. */
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300 /* This pops the remaining registers. */
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306 /*-----------------------------------------------------------*/
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308 void vPortSoftwareInterruptISR( void )
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312 /* Re-enable interrupts. */
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315 /* Move the data that was automatically pushed onto the interrupt stack when
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316 the interrupt occurred from the interrupt stack to the user stack.
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318 R15 is saved before it is clobbered. */
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321 /* Read the user stack pointer. */
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322 "MVFC USP, R15 \n" \
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324 /* Move the address down to the data being moved. */
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325 "SUB #12, R15 \n" \
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326 "MVTC R15, USP \n" \
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328 /* Copy the data across, R15, then PC, then PSW. */
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329 "MOV.L [ R0 ], [ R15 ] \n" \
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330 "MOV.L 4[ R0 ], 4[ R15 ] \n" \
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331 "MOV.L 8[ R0 ], 8[ R15 ] \n" \
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333 /* Move the interrupt stack pointer to its new correct position. */
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336 /* All the rest of the registers are saved directly to the user stack. */
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339 /* Save the rest of the general registers (R15 has been saved already). */
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340 "PUSHM R1-R14 \n" \
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342 /* Save the accumulator. */
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349 /* Shifted left as it is restored to the low order word. */
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350 "SHLL #16, R15 \n" \
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353 /* Save the stack pointer to the TCB. */
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354 "MOV.L #_pxCurrentTCB, R15 \n" \
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355 "MOV.L [ R15 ], R15 \n" \
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356 "MOV.L R0, [ R15 ] \n" \
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358 /* Ensure the interrupt mask is set to the syscall priority while the kernel
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359 structures are being accessed. */
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362 /* Select the next task to run. */
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363 "BSR.A _vTaskSwitchContext \n" \
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365 /* Reset the interrupt mask as no more data structure access is required. */
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368 /* Load the stack pointer of the task that is now selected as the Running
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369 state task from its TCB. */
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370 "MOV.L #_pxCurrentTCB,R15 \n" \
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371 "MOV.L [ R15 ], R15 \n" \
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372 "MOV.L [ R15 ], R0 \n" \
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374 /* Restore the context of the new task. The PSW (Program Status Word) and
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375 PC will be popped by the RTE instruction. */
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384 :: "i"(configMAX_SYSCALL_INTERRUPT_PRIORITY), "i"(configKERNEL_INTERRUPT_PRIORITY)
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387 /*-----------------------------------------------------------*/
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389 void vPortTickISR( void )
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391 /* Re-enabled interrupts. */
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392 __asm volatile( "SETPSW I" );
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394 /* Increment the tick, and perform any processing the new tick value
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395 necessitates. Ensure IPL is at the max syscall value first. */
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396 portDISABLE_INTERRUPTS_FROM_KERNEL_ISR();
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398 if( xTaskIncrementTick() != pdFALSE )
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403 portENABLE_INTERRUPTS_FROM_KERNEL_ISR();
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405 #if configUSE_TICKLESS_IDLE == 1
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407 /* The CPU woke because of a tick. */
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408 ulTickFlag = pdTRUE;
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410 /* If this is the first tick since exiting tickless mode then the CMT
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411 compare match value needs resetting. */
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412 CMT0.CMCOR = ( uint16_t ) ulMatchValueForOneTick;
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416 /*-----------------------------------------------------------*/
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418 uint32_t ulPortGetIPL( void )
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422 "MVFC PSW, R1 \n" \
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423 "SHLR #24, R1 \n" \
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427 /* This will never get executed, but keeps the compiler from complaining. */
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430 /*-----------------------------------------------------------*/
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432 void vPortSetIPL( uint32_t ulNewIPL )
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437 "MVFC PSW, R5 \n" \
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438 "SHLL #24, R1 \n" \
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439 "AND #-0F000001H, R5 \n" \
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441 "MVTC R5, PSW \n" \
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446 /*-----------------------------------------------------------*/
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448 static void prvSetupTimerInterrupt( void )
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451 SYSTEM.PRCR.WORD = portUNLOCK_KEY;
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457 SYSTEM.PRCR.WORD = portLOCK_KEY;
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459 /* Interrupt on compare match. */
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460 CMT0.CMCR.BIT.CMIE = 1;
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462 /* Set the compare match value. */
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463 CMT0.CMCOR = ( uint16_t ) ulMatchValueForOneTick;
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465 /* Divide the PCLK. */
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466 #if portCLOCK_DIVISOR == 512
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468 CMT0.CMCR.BIT.CKS = 3;
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470 #elif portCLOCK_DIVISOR == 128
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472 CMT0.CMCR.BIT.CKS = 2;
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474 #elif portCLOCK_DIVISOR == 32
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476 CMT0.CMCR.BIT.CKS = 1;
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478 #elif portCLOCK_DIVISOR == 8
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480 CMT0.CMCR.BIT.CKS = 0;
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484 #error Invalid portCLOCK_DIVISOR setting
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488 /* Enable the interrupt... */
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489 _IEN( _CMT0_CMI0 ) = 1;
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491 /* ...and set its priority to the application defined kernel priority. */
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492 _IPR( _CMT0_CMI0 ) = configKERNEL_INTERRUPT_PRIORITY;
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494 /* Start the timer. */
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495 CMT.CMSTR0.BIT.STR0 = 1;
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497 /*-----------------------------------------------------------*/
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499 #if configUSE_TICKLESS_IDLE == 1
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501 static void prvSleep( TickType_t xExpectedIdleTime )
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503 /* Allow the application to define some pre-sleep processing. */
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504 configPRE_SLEEP_PROCESSING( xExpectedIdleTime );
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506 /* xExpectedIdleTime being set to 0 by configPRE_SLEEP_PROCESSING()
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507 means the application defined code has already executed the WAIT
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509 if( xExpectedIdleTime > 0 )
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511 __asm volatile( "WAIT" );
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514 /* Allow the application to define some post sleep processing. */
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515 configPOST_SLEEP_PROCESSING( xExpectedIdleTime );
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518 #endif /* configUSE_TICKLESS_IDLE */
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519 /*-----------------------------------------------------------*/
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521 #if configUSE_TICKLESS_IDLE == 1
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523 void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )
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525 uint32_t ulMatchValue, ulCompleteTickPeriods, ulCurrentCount;
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526 eSleepModeStatus eSleepAction;
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528 /* THIS FUNCTION IS CALLED WITH THE SCHEDULER SUSPENDED. */
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530 /* Make sure the CMT reload value does not overflow the counter. */
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531 if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks )
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533 xExpectedIdleTime = xMaximumPossibleSuppressedTicks;
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536 /* Calculate the reload value required to wait xExpectedIdleTime tick
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538 ulMatchValue = ulMatchValueForOneTick * xExpectedIdleTime;
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539 if( ulMatchValue > ulStoppedTimerCompensation )
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541 /* Compensate for the fact that the CMT is going to be stopped
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543 ulMatchValue -= ulStoppedTimerCompensation;
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546 /* Stop the CMT momentarily. The time the CMT is stopped for is
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547 accounted for as best it can be, but using the tickless mode will
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548 inevitably result in some tiny drift of the time maintained by the
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549 kernel with respect to calendar time. */
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550 CMT.CMSTR0.BIT.STR0 = 0;
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551 while( CMT.CMSTR0.BIT.STR0 == 1 )
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553 /* Nothing to do here. */
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556 /* Critical section using the global interrupt bit as the i bit is
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557 automatically reset by the WAIT instruction. */
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558 __asm volatile( "CLRPSW i" );
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560 /* The tick flag is set to false before sleeping. If it is true when
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561 sleep mode is exited then sleep mode was probably exited because the
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562 tick was suppressed for the entire xExpectedIdleTime period. */
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563 ulTickFlag = pdFALSE;
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565 /* If a context switch is pending then abandon the low power entry as
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566 the context switch might have been pended by an external interrupt that
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567 requires processing. */
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568 eSleepAction = eTaskConfirmSleepModeStatus();
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569 if( eSleepAction == eAbortSleep )
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571 /* Restart tick. */
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572 CMT.CMSTR0.BIT.STR0 = 1;
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573 __asm volatile( "SETPSW i" );
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575 else if( eSleepAction == eNoTasksWaitingTimeout )
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577 /* Protection off. */
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578 SYSTEM.PRCR.WORD = portUNLOCK_KEY;
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580 /* Ready for software standby with all clocks stopped. */
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581 SYSTEM.SBYCR.BIT.SSBY = 1;
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583 /* Protection on. */
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584 SYSTEM.PRCR.WORD = portLOCK_KEY;
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586 /* Sleep until something happens. Calling prvSleep() will
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587 automatically reset the i bit in the PSW. */
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588 prvSleep( xExpectedIdleTime );
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590 /* Restart the CMT. */
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591 CMT.CMSTR0.BIT.STR0 = 1;
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595 /* Protection off. */
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596 SYSTEM.PRCR.WORD = portUNLOCK_KEY;
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598 /* Ready for deep sleep mode. */
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599 SYSTEM.MSTPCRC.BIT.DSLPE = 1;
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600 SYSTEM.MSTPCRA.BIT.MSTPA28 = 1;
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601 SYSTEM.SBYCR.BIT.SSBY = 0;
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603 /* Protection on. */
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604 SYSTEM.PRCR.WORD = portLOCK_KEY;
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606 /* Adjust the match value to take into account that the current
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607 time slice is already partially complete. */
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608 ulMatchValue -= ( uint32_t ) CMT0.CMCNT;
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609 CMT0.CMCOR = ( uint16_t ) ulMatchValue;
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611 /* Restart the CMT to count up to the new match value. */
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613 CMT.CMSTR0.BIT.STR0 = 1;
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615 /* Sleep until something happens. Calling prvSleep() will
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616 automatically reset the i bit in the PSW. */
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617 prvSleep( xExpectedIdleTime );
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619 /* Stop CMT. Again, the time the SysTick is stopped for is
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620 accounted for as best it can be, but using the tickless mode will
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621 inevitably result in some tiny drift of the time maintained by the
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622 kernel with respect to calendar time. */
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623 CMT.CMSTR0.BIT.STR0 = 0;
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624 while( CMT.CMSTR0.BIT.STR0 == 1 )
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626 /* Nothing to do here. */
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629 ulCurrentCount = ( uint32_t ) CMT0.CMCNT;
\r
631 if( ulTickFlag != pdFALSE )
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633 /* The tick interrupt has already executed, although because
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634 this function is called with the scheduler suspended the actual
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635 tick processing will not occur until after this function has
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636 exited. Reset the match value with whatever remains of this
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638 ulMatchValue = ulMatchValueForOneTick - ulCurrentCount;
\r
639 CMT0.CMCOR = ( uint16_t ) ulMatchValue;
\r
641 /* The tick interrupt handler will already have pended the tick
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642 processing in the kernel. As the pending tick will be
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643 processed as soon as this function exits, the tick value
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644 maintained by the tick is stepped forward by one less than the
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645 time spent sleeping. The actual stepping of the tick appears
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646 later in this function. */
\r
647 ulCompleteTickPeriods = xExpectedIdleTime - 1UL;
\r
651 /* Something other than the tick interrupt ended the sleep.
\r
652 How many complete tick periods passed while the processor was
\r
654 ulCompleteTickPeriods = ulCurrentCount / ulMatchValueForOneTick;
\r
656 /* The match value is set to whatever fraction of a single tick
\r
658 ulMatchValue = ulCurrentCount - ( ulCompleteTickPeriods * ulMatchValueForOneTick );
\r
659 CMT0.CMCOR = ( uint16_t ) ulMatchValue;
\r
662 /* Restart the CMT so it runs up to the match value. The match value
\r
663 will get set to the value required to generate exactly one tick period
\r
664 the next time the CMT interrupt executes. */
\r
666 CMT.CMSTR0.BIT.STR0 = 1;
\r
668 /* Wind the tick forward by the number of tick periods that the CPU
\r
669 remained in a low power state. */
\r
670 vTaskStepTick( ulCompleteTickPeriods );
\r
674 #endif /* configUSE_TICKLESS_IDLE */
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