2 FreeRTOS V7.5.0 - Copyright (C) 2013 Real Time Engineers Ltd.
\r
4 VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
\r
6 ***************************************************************************
\r
8 * FreeRTOS provides completely free yet professionally developed, *
\r
9 * robust, strictly quality controlled, supported, and cross *
\r
10 * platform software that has become a de facto standard. *
\r
12 * Help yourself get started quickly and support the FreeRTOS *
\r
13 * project by purchasing a FreeRTOS tutorial book, reference *
\r
14 * manual, or both from: http://www.FreeRTOS.org/Documentation *
\r
18 ***************************************************************************
\r
20 This file is part of the FreeRTOS distribution.
\r
22 FreeRTOS is free software; you can redistribute it and/or modify it under
\r
23 the terms of the GNU General Public License (version 2) as published by the
\r
24 Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.
\r
26 >>! NOTE: The modification to the GPL is included to allow you to distribute
\r
27 >>! a combined work that includes FreeRTOS without being obliged to provide
\r
28 >>! the source code for proprietary components outside of the FreeRTOS
\r
31 FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
\r
32 WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
\r
33 FOR A PARTICULAR PURPOSE. Full license text is available from the following
\r
34 link: http://www.freertos.org/a00114.html
\r
38 ***************************************************************************
\r
40 * Having a problem? Start by reading the FAQ "My application does *
\r
41 * not run, what could be wrong?" *
\r
43 * http://www.FreeRTOS.org/FAQHelp.html *
\r
45 ***************************************************************************
\r
47 http://www.FreeRTOS.org - Documentation, books, training, latest versions,
\r
48 license and Real Time Engineers Ltd. contact details.
\r
50 http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
\r
51 including FreeRTOS+Trace - an indispensable productivity tool, a DOS
\r
52 compatible FAT file system, and our tiny thread aware UDP/IP stack.
\r
54 http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High
\r
55 Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS
\r
56 licenses offer ticketed support, indemnification and middleware.
\r
58 http://www.SafeRTOS.com - High Integrity Systems also provide a safety
\r
59 engineered and independently SIL3 certified version for use in safety and
\r
60 mission critical applications that require provable dependability.
\r
65 /*-----------------------------------------------------------
\r
66 * Implementation of functions defined in portable.h for the SH2A port.
\r
67 *----------------------------------------------------------*/
\r
69 /* Standard C includes. */
\r
72 /* Scheduler includes. */
\r
73 #include "FreeRTOS.h"
\r
76 /* Library includes. */
\r
79 /* Hardware specifics. */
\r
80 #include "iodefine.h"
\r
82 /*-----------------------------------------------------------*/
\r
84 /* Tasks should start with interrupts enabled and in Supervisor mode, therefore
\r
85 PSW is set with U and I set, and PM and IPL clear. */
\r
86 #define portINITIAL_PSW ( ( portSTACK_TYPE ) 0x00030000 )
\r
88 /* The peripheral clock is divided by this value before being supplying the
\r
90 #if ( configUSE_TICKLESS_IDLE == 0 )
\r
91 /* If tickless idle is not used then the divisor can be fixed. */
\r
92 #define portCLOCK_DIVISOR 8UL
\r
93 #elif ( configPERIPHERAL_CLOCK_HZ >= 12000000 )
\r
94 #define portCLOCK_DIVISOR 512UL
\r
95 #elif ( configPERIPHERAL_CLOCK_HZ >= 6000000 )
\r
96 #define portCLOCK_DIVISOR 128UL
\r
97 #elif ( configPERIPHERAL_CLOCK_HZ >= 1000000 )
\r
98 #define portCLOCK_DIVISOR 32UL
\r
100 #define portCLOCK_DIVISOR 8UL
\r
103 /* These macros allow a critical section to be added around the call to
\r
104 xTaskIncrementTick(), which is only ever called from interrupts at the kernel
\r
105 priority - ie a known priority. Therefore these local macros are a slight
\r
106 optimisation compared to calling the global SET/CLEAR_INTERRUPT_MASK macros,
\r
107 which would require the old IPL to be read first and stored in a local variable. */
\r
108 #define portDISABLE_INTERRUPTS_FROM_KERNEL_ISR() __asm volatile ( "MVTIPL %0" ::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY) )
\r
109 #define portENABLE_INTERRUPTS_FROM_KERNEL_ISR() __asm volatile ( "MVTIPL %0" ::"i"(configKERNEL_INTERRUPT_PRIORITY) )
\r
111 /* Keys required to lock and unlock access to certain system registers
\r
113 #define portUNLOCK_KEY 0xA50B
\r
114 #define portLOCK_KEY 0xA500
\r
116 /*-----------------------------------------------------------*/
\r
119 * Function to start the first task executing - written in asm code as direct
\r
120 * access to registers is required.
\r
122 static void prvStartFirstTask( void ) __attribute__((naked));
\r
125 * Software interrupt handler. Performs the actual context switch (saving and
\r
126 * restoring of registers). Written in asm code as direct register access is
\r
129 void vPortSoftwareInterruptISR( void ) __attribute__((naked));
\r
132 * The tick interrupt handler.
\r
134 void vPortTickISR( void ) __attribute__((interrupt));
\r
137 * Sets up the periodic ISR used for the RTOS tick using the CMT.
\r
138 * The application writer can define configSETUP_TICK_INTERRUPT() (in
\r
139 * FreeRTOSConfig.h) such that their own tick interrupt configuration is used
\r
140 * in place of prvSetupTimerInterrupt().
\r
142 static void prvSetupTimerInterrupt( void );
\r
143 #ifndef configSETUP_TICK_INTERRUPT
\r
144 /* The user has not provided their own tick interrupt configuration so use
\r
145 the definition in this file (which uses the interval timer). */
\r
146 #define configSETUP_TICK_INTERRUPT() prvSetupTimerInterrupt()
\r
147 #endif /* configSETUP_TICK_INTERRUPT */
\r
150 * Called after the sleep mode registers have been configured, prvSleep()
\r
151 * executes the pre and post sleep macros, and actually calls the wait
\r
154 #if configUSE_TICKLESS_IDLE == 1
\r
155 static void prvSleep( portTickType xExpectedIdleTime );
\r
156 #endif /* configUSE_TICKLESS_IDLE */
\r
158 /*-----------------------------------------------------------*/
\r
160 /* Used in the context save and restore code. */
\r
161 extern void *pxCurrentTCB;
\r
163 /* Calculate how many clock increments make up a single tick period. */
\r
164 static const unsigned long ulMatchValueForOneTick = ( ( configPERIPHERAL_CLOCK_HZ / portCLOCK_DIVISOR ) / configTICK_RATE_HZ );
\r
166 #if configUSE_TICKLESS_IDLE == 1
\r
168 /* Holds the maximum number of ticks that can be suppressed - which is
\r
169 basically how far into the future an interrupt can be generated. Set
\r
170 during initialisation. This is the maximum possible value that the
\r
171 compare match register can hold divided by ulMatchValueForOneTick. */
\r
172 static const portTickType xMaximumPossibleSuppressedTicks = USHRT_MAX / ( ( configPERIPHERAL_CLOCK_HZ / portCLOCK_DIVISOR ) / configTICK_RATE_HZ );
\r
174 /* Flag set from the tick interrupt to allow the sleep processing to know if
\r
175 sleep mode was exited because of a tick interrupt, or an interrupt
\r
176 generated by something else. */
\r
177 static volatile uint32_t ulTickFlag = pdFALSE;
\r
179 /* The CMT counter is stopped temporarily each time it is re-programmed.
\r
180 The following constant offsets the CMT counter match value by the number of
\r
181 CMT counts that would typically be missed while the counter was stopped to
\r
182 compensate for the lost time. The large difference between the divided CMT
\r
183 clock and the CPU clock means it is likely ulStoppedTimerCompensation will
\r
184 equal zero - and be optimised away. */
\r
185 static const unsigned long ulStoppedTimerCompensation = 100UL / ( configCPU_CLOCK_HZ / ( configPERIPHERAL_CLOCK_HZ / portCLOCK_DIVISOR ) );
\r
189 /*-----------------------------------------------------------*/
\r
192 * See header file for description.
\r
194 portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters )
\r
196 /* Offset to end up on 8 byte boundary. */
\r
199 /* R0 is not included as it is the stack pointer. */
\r
200 *pxTopOfStack = 0x00;
\r
202 *pxTopOfStack = 0x00;
\r
204 *pxTopOfStack = portINITIAL_PSW;
\r
206 *pxTopOfStack = ( portSTACK_TYPE ) pxCode;
\r
208 /* When debugging it can be useful if every register is set to a known
\r
209 value. Otherwise code space can be saved by just setting the registers
\r
210 that need to be set. */
\r
211 #ifdef USE_FULL_REGISTER_INITIALISATION
\r
214 *pxTopOfStack = 0x12345678; /* r15. */
\r
216 *pxTopOfStack = 0xaaaabbbb;
\r
218 *pxTopOfStack = 0xdddddddd;
\r
220 *pxTopOfStack = 0xcccccccc;
\r
222 *pxTopOfStack = 0xbbbbbbbb;
\r
224 *pxTopOfStack = 0xaaaaaaaa;
\r
226 *pxTopOfStack = 0x99999999;
\r
228 *pxTopOfStack = 0x88888888;
\r
230 *pxTopOfStack = 0x77777777;
\r
232 *pxTopOfStack = 0x66666666;
\r
234 *pxTopOfStack = 0x55555555;
\r
236 *pxTopOfStack = 0x44444444;
\r
238 *pxTopOfStack = 0x33333333;
\r
240 *pxTopOfStack = 0x22222222;
\r
245 /* Leave space for the registers that will get popped from the stack
\r
246 when the task first starts executing. */
\r
247 pxTopOfStack -= 15;
\r
251 *pxTopOfStack = ( portSTACK_TYPE ) pvParameters; /* R1 */
\r
253 *pxTopOfStack = 0x12345678; /* Accumulator. */
\r
255 *pxTopOfStack = 0x87654321; /* Accumulator. */
\r
257 return pxTopOfStack;
\r
259 /*-----------------------------------------------------------*/
\r
261 portBASE_TYPE xPortStartScheduler( void )
\r
263 /* Use pxCurrentTCB just so it does not get optimised away. */
\r
264 if( pxCurrentTCB != NULL )
\r
266 /* Call an application function to set up the timer that will generate
\r
267 the tick interrupt. This way the application can decide which
\r
268 peripheral to use. If tickless mode is used then the default
\r
269 implementation defined in this file (which uses CMT0) should not be
\r
271 configSETUP_TICK_INTERRUPT();
\r
273 /* Enable the software interrupt. */
\r
274 _IEN( _ICU_SWINT ) = 1;
\r
276 /* Ensure the software interrupt is clear. */
\r
277 _IR( _ICU_SWINT ) = 0;
\r
279 /* Ensure the software interrupt is set to the kernel priority. */
\r
280 _IPR( _ICU_SWINT ) = configKERNEL_INTERRUPT_PRIORITY;
\r
282 /* Start the first task. */
\r
283 prvStartFirstTask();
\r
286 /* Execution should not reach here as the tasks are now running!
\r
287 prvSetupTimerInterrupt() is called here to prevent the compiler outputting
\r
288 a warning about a statically declared function not being referenced in the
\r
289 case that the application writer has provided their own tick interrupt
\r
290 configuration routine (and defined configSETUP_TICK_INTERRUPT() such that
\r
291 their own routine will be called in place of prvSetupTimerInterrupt()). */
\r
292 prvSetupTimerInterrupt();
\r
294 /* Should not get here. */
\r
297 /*-----------------------------------------------------------*/
\r
299 void vPortEndScheduler( void )
\r
301 /* Not implemented as there is nothing to return to. */
\r
303 /*-----------------------------------------------------------*/
\r
305 static void prvStartFirstTask( void )
\r
309 /* When starting the scheduler there is nothing that needs moving to the
\r
310 interrupt stack because the function is not called from an interrupt.
\r
311 Just ensure the current stack is the user stack. */
\r
314 /* Obtain the location of the stack associated with which ever task
\r
315 pxCurrentTCB is currently pointing to. */
\r
316 "MOV.L #_pxCurrentTCB, R15 \n" \
\r
317 "MOV.L [R15], R15 \n" \
\r
318 "MOV.L [R15], R0 \n" \
\r
320 /* Restore the registers from the stack of the task pointed to by
\r
324 /* Accumulator low 32 bits. */
\r
328 /* Accumulator high 32 bits. */
\r
331 /* R1 to R15 - R0 is not included as it is the SP. */
\r
334 /* This pops the remaining registers. */
\r
340 /*-----------------------------------------------------------*/
\r
342 void vPortSoftwareInterruptISR( void )
\r
346 /* Re-enable interrupts. */
\r
349 /* Move the data that was automatically pushed onto the interrupt stack when
\r
350 the interrupt occurred from the interrupt stack to the user stack.
\r
352 R15 is saved before it is clobbered. */
\r
355 /* Read the user stack pointer. */
\r
356 "MVFC USP, R15 \n" \
\r
358 /* Move the address down to the data being moved. */
\r
359 "SUB #12, R15 \n" \
\r
360 "MVTC R15, USP \n" \
\r
362 /* Copy the data across, R15, then PC, then PSW. */
\r
363 "MOV.L [ R0 ], [ R15 ] \n" \
\r
364 "MOV.L 4[ R0 ], 4[ R15 ] \n" \
\r
365 "MOV.L 8[ R0 ], 8[ R15 ] \n" \
\r
367 /* Move the interrupt stack pointer to its new correct position. */
\r
370 /* All the rest of the registers are saved directly to the user stack. */
\r
373 /* Save the rest of the general registers (R15 has been saved already). */
\r
374 "PUSHM R1-R14 \n" \
\r
376 /* Save the accumulator. */
\r
383 /* Shifted left as it is restored to the low order word. */
\r
384 "SHLL #16, R15 \n" \
\r
387 /* Save the stack pointer to the TCB. */
\r
388 "MOV.L #_pxCurrentTCB, R15 \n" \
\r
389 "MOV.L [ R15 ], R15 \n" \
\r
390 "MOV.L R0, [ R15 ] \n" \
\r
392 /* Ensure the interrupt mask is set to the syscall priority while the kernel
\r
393 structures are being accessed. */
\r
396 /* Select the next task to run. */
\r
397 "BSR.A _vTaskSwitchContext \n" \
\r
399 /* Reset the interrupt mask as no more data structure access is required. */
\r
402 /* Load the stack pointer of the task that is now selected as the Running
\r
403 state task from its TCB. */
\r
404 "MOV.L #_pxCurrentTCB,R15 \n" \
\r
405 "MOV.L [ R15 ], R15 \n" \
\r
406 "MOV.L [ R15 ], R0 \n" \
\r
408 /* Restore the context of the new task. The PSW (Program Status Word) and
\r
409 PC will be popped by the RTE instruction. */
\r
418 :: "i"(configMAX_SYSCALL_INTERRUPT_PRIORITY), "i"(configKERNEL_INTERRUPT_PRIORITY)
\r
421 /*-----------------------------------------------------------*/
\r
423 void vPortTickISR( void )
\r
425 /* Re-enabled interrupts. */
\r
426 __asm volatile( "SETPSW I" );
\r
428 /* Increment the tick, and perform any processing the new tick value
\r
429 necessitates. Ensure IPL is at the max syscall value first. */
\r
430 portDISABLE_INTERRUPTS_FROM_KERNEL_ISR();
\r
432 if( xTaskIncrementTick() != pdFALSE )
\r
437 portENABLE_INTERRUPTS_FROM_KERNEL_ISR();
\r
439 #if configUSE_TICKLESS_IDLE == 1
\r
441 /* The CPU woke because of a tick. */
\r
442 ulTickFlag = pdTRUE;
\r
444 /* If this is the first tick since exiting tickless mode then the CMT
\r
445 compare match value needs resetting. */
\r
446 CMT0.CMCOR = ( unsigned short ) ulMatchValueForOneTick;
\r
450 /*-----------------------------------------------------------*/
\r
452 unsigned long ulPortGetIPL( void )
\r
456 "MVFC PSW, R1 \n" \
\r
457 "SHLR #24, R1 \n" \
\r
461 /* This will never get executed, but keeps the compiler from complaining. */
\r
464 /*-----------------------------------------------------------*/
\r
466 void vPortSetIPL( unsigned long ulNewIPL )
\r
471 "MVFC PSW, R5 \n" \
\r
472 "SHLL #24, R1 \n" \
\r
473 "AND #-0F000001H, R5 \n" \
\r
475 "MVTC R5, PSW \n" \
\r
480 /*-----------------------------------------------------------*/
\r
482 static void prvSetupTimerInterrupt( void )
\r
485 SYSTEM.PRCR.WORD = portUNLOCK_KEY;
\r
491 SYSTEM.PRCR.WORD = portLOCK_KEY;
\r
493 /* Interrupt on compare match. */
\r
494 CMT0.CMCR.BIT.CMIE = 1;
\r
496 /* Set the compare match value. */
\r
497 CMT0.CMCOR = ( unsigned short ) ulMatchValueForOneTick;
\r
499 /* Divide the PCLK. */
\r
500 #if portCLOCK_DIVISOR == 512
\r
502 CMT0.CMCR.BIT.CKS = 3;
\r
504 #elif portCLOCK_DIVISOR == 128
\r
506 CMT0.CMCR.BIT.CKS = 2;
\r
508 #elif portCLOCK_DIVISOR == 32
\r
510 CMT0.CMCR.BIT.CKS = 1;
\r
512 #elif portCLOCK_DIVISOR == 8
\r
514 CMT0.CMCR.BIT.CKS = 0;
\r
518 #error Invalid portCLOCK_DIVISOR setting
\r
522 /* Enable the interrupt... */
\r
523 _IEN( _CMT0_CMI0 ) = 1;
\r
525 /* ...and set its priority to the application defined kernel priority. */
\r
526 _IPR( _CMT0_CMI0 ) = configKERNEL_INTERRUPT_PRIORITY;
\r
528 /* Start the timer. */
\r
529 CMT.CMSTR0.BIT.STR0 = 1;
\r
531 /*-----------------------------------------------------------*/
\r
533 #if configUSE_TICKLESS_IDLE == 1
\r
535 static void prvSleep( portTickType xExpectedIdleTime )
\r
537 /* Allow the application to define some pre-sleep processing. */
\r
538 configPRE_SLEEP_PROCESSING( xExpectedIdleTime );
\r
540 /* xExpectedIdleTime being set to 0 by configPRE_SLEEP_PROCESSING()
\r
541 means the application defined code has already executed the WAIT
\r
543 if( xExpectedIdleTime > 0 )
\r
545 __asm volatile( "WAIT" );
\r
548 /* Allow the application to define some post sleep processing. */
\r
549 configPOST_SLEEP_PROCESSING( xExpectedIdleTime );
\r
552 #endif /* configUSE_TICKLESS_IDLE */
\r
553 /*-----------------------------------------------------------*/
\r
555 #if configUSE_TICKLESS_IDLE == 1
\r
557 void vPortSuppressTicksAndSleep( portTickType xExpectedIdleTime )
\r
559 unsigned long ulMatchValue, ulCompleteTickPeriods, ulCurrentCount;
\r
560 eSleepModeStatus eSleepAction;
\r
562 /* THIS FUNCTION IS CALLED WITH THE SCHEDULER SUSPENDED. */
\r
564 /* Make sure the CMT reload value does not overflow the counter. */
\r
565 if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks )
\r
567 xExpectedIdleTime = xMaximumPossibleSuppressedTicks;
\r
570 /* Calculate the reload value required to wait xExpectedIdleTime tick
\r
572 ulMatchValue = ulMatchValueForOneTick * xExpectedIdleTime;
\r
573 if( ulMatchValue > ulStoppedTimerCompensation )
\r
575 /* Compensate for the fact that the CMT is going to be stopped
\r
577 ulMatchValue -= ulStoppedTimerCompensation;
\r
580 /* Stop the CMT momentarily. The time the CMT is stopped for is
\r
581 accounted for as best it can be, but using the tickless mode will
\r
582 inevitably result in some tiny drift of the time maintained by the
\r
583 kernel with respect to calendar time. */
\r
584 CMT.CMSTR0.BIT.STR0 = 0;
\r
585 while( CMT.CMSTR0.BIT.STR0 == 1 )
\r
587 /* Nothing to do here. */
\r
590 /* Critical section using the global interrupt bit as the i bit is
\r
591 automatically reset by the WAIT instruction. */
\r
592 __asm volatile( "CLRPSW i" );
\r
594 /* The tick flag is set to false before sleeping. If it is true when
\r
595 sleep mode is exited then sleep mode was probably exited because the
\r
596 tick was suppressed for the entire xExpectedIdleTime period. */
\r
597 ulTickFlag = pdFALSE;
\r
599 /* If a context switch is pending then abandon the low power entry as
\r
600 the context switch might have been pended by an external interrupt that
\r
601 requires processing. */
\r
602 eSleepAction = eTaskConfirmSleepModeStatus();
\r
603 if( eSleepAction == eAbortSleep )
\r
605 /* Restart tick. */
\r
606 CMT.CMSTR0.BIT.STR0 = 1;
\r
607 __asm volatile( "SETPSW i" );
\r
609 else if( eSleepAction == eNoTasksWaitingTimeout )
\r
611 /* Protection off. */
\r
612 SYSTEM.PRCR.WORD = portUNLOCK_KEY;
\r
614 /* Ready for software standby with all clocks stopped. */
\r
615 SYSTEM.SBYCR.BIT.SSBY = 1;
\r
617 /* Protection on. */
\r
618 SYSTEM.PRCR.WORD = portLOCK_KEY;
\r
620 /* Sleep until something happens. Calling prvSleep() will
\r
621 automatically reset the i bit in the PSW. */
\r
622 prvSleep( xExpectedIdleTime );
\r
624 /* Restart the CMT. */
\r
625 CMT.CMSTR0.BIT.STR0 = 1;
\r
629 /* Protection off. */
\r
630 SYSTEM.PRCR.WORD = portUNLOCK_KEY;
\r
632 /* Ready for deep sleep mode. */
\r
633 SYSTEM.MSTPCRC.BIT.DSLPE = 1;
\r
634 SYSTEM.MSTPCRA.BIT.MSTPA28 = 1;
\r
635 SYSTEM.SBYCR.BIT.SSBY = 0;
\r
637 /* Protection on. */
\r
638 SYSTEM.PRCR.WORD = portLOCK_KEY;
\r
640 /* Adjust the match value to take into account that the current
\r
641 time slice is already partially complete. */
\r
642 ulMatchValue -= ( unsigned long ) CMT0.CMCNT;
\r
643 CMT0.CMCOR = ( unsigned short ) ulMatchValue;
\r
645 /* Restart the CMT to count up to the new match value. */
\r
647 CMT.CMSTR0.BIT.STR0 = 1;
\r
649 /* Sleep until something happens. Calling prvSleep() will
\r
650 automatically reset the i bit in the PSW. */
\r
651 prvSleep( xExpectedIdleTime );
\r
653 /* Stop CMT. Again, the time the SysTick is stopped for is
\r
654 accounted for as best it can be, but using the tickless mode will
\r
655 inevitably result in some tiny drift of the time maintained by the
\r
656 kernel with respect to calendar time. */
\r
657 CMT.CMSTR0.BIT.STR0 = 0;
\r
658 while( CMT.CMSTR0.BIT.STR0 == 1 )
\r
660 /* Nothing to do here. */
\r
663 ulCurrentCount = ( unsigned long ) CMT0.CMCNT;
\r
665 if( ulTickFlag != pdFALSE )
\r
667 /* The tick interrupt has already executed, although because
\r
668 this function is called with the scheduler suspended the actual
\r
669 tick processing will not occur until after this function has
\r
670 exited. Reset the match value with whatever remains of this
\r
672 ulMatchValue = ulMatchValueForOneTick - ulCurrentCount;
\r
673 CMT0.CMCOR = ( unsigned short ) ulMatchValue;
\r
675 /* The tick interrupt handler will already have pended the tick
\r
676 processing in the kernel. As the pending tick will be
\r
677 processed as soon as this function exits, the tick value
\r
678 maintained by the tick is stepped forward by one less than the
\r
679 time spent sleeping. The actual stepping of the tick appears
\r
680 later in this function. */
\r
681 ulCompleteTickPeriods = xExpectedIdleTime - 1UL;
\r
685 /* Something other than the tick interrupt ended the sleep.
\r
686 How many complete tick periods passed while the processor was
\r
688 ulCompleteTickPeriods = ulCurrentCount / ulMatchValueForOneTick;
\r
690 /* The match value is set to whatever fraction of a single tick
\r
692 ulMatchValue = ulCurrentCount - ( ulCompleteTickPeriods * ulMatchValueForOneTick );
\r
693 CMT0.CMCOR = ( unsigned short ) ulMatchValue;
\r
696 /* Restart the CMT so it runs up to the match value. The match value
\r
697 will get set to the value required to generate exactly one tick period
\r
698 the next time the CMT interrupt executes. */
\r
700 CMT.CMSTR0.BIT.STR0 = 1;
\r
702 /* Wind the tick forward by the number of tick periods that the CPU
\r
703 remained in a low power state. */
\r
704 vTaskStepTick( ulCompleteTickPeriods );
\r
708 #endif /* configUSE_TICKLESS_IDLE */
\r
projects / freertos / blob