git.sur5r.net Git - freertos/blob - FreeRTOS/Source/portable/GCC/RX600/port.c

   1 /*\r
   2     FreeRTOS V8.2.1 - Copyright (C) 2015 Real Time Engineers Ltd.\r
   3     All rights reserved\r
   4 \r
   5     VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
   6 \r
   7     This file is part of the FreeRTOS distribution.\r
   8 \r
   9     FreeRTOS is free software; you can redistribute it and/or modify it under\r
  10     the terms of the GNU General Public License (version 2) as published by the\r
  11     Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.\r
  12 \r
  13     ***************************************************************************\r
  14     >>!   NOTE: The modification to the GPL is included to allow you to     !<<\r
  15     >>!   distribute a combined work that includes FreeRTOS without being   !<<\r
  16     >>!   obliged to provide the source code for proprietary components     !<<\r
  17     >>!   outside of the FreeRTOS kernel.                                   !<<\r
  18     ***************************************************************************\r
  19 \r
  20     FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
  21     WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
  22     FOR A PARTICULAR PURPOSE.  Full license text is available on the following\r
  23     link: http://www.freertos.org/a00114.html\r
  24 \r
  25     ***************************************************************************\r
  26      *                                                                       *\r
  27      *    FreeRTOS provides completely free yet professionally developed,    *\r
  28      *    robust, strictly quality controlled, supported, and cross          *\r
  29      *    platform software that is more than just the market leader, it     *\r
  30      *    is the industry's de facto standard.                               *\r
  31      *                                                                       *\r
  32      *    Help yourself get started quickly while simultaneously helping     *\r
  33      *    to support the FreeRTOS project by purchasing a FreeRTOS           *\r
  34      *    tutorial book, reference manual, or both:                          *\r
  35      *    http://www.FreeRTOS.org/Documentation                              *\r
  36      *                                                                       *\r
  37     ***************************************************************************\r
  38 \r
  39     http://www.FreeRTOS.org/FAQHelp.html - Having a problem?  Start by reading\r
  40     the FAQ page "My application does not run, what could be wrong?".  Have you\r
  41     defined configASSERT()?\r
  42 \r
  43     http://www.FreeRTOS.org/support - In return for receiving this top quality\r
  44     embedded software for free we request you assist our global community by\r
  45     participating in the support forum.\r
  46 \r
  47     http://www.FreeRTOS.org/training - Investing in training allows your team to\r
  48     be as productive as possible as early as possible.  Now you can receive\r
  49     FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers\r
  50     Ltd, and the world's leading authority on the world's leading RTOS.\r
  51 \r
  52     http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
  53     including FreeRTOS+Trace - an indispensable productivity tool, a DOS\r
  54     compatible FAT file system, and our tiny thread aware UDP/IP stack.\r
  55 \r
  56     http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.\r
  57     Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.\r
  58 \r
  59     http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High\r
  60     Integrity Systems ltd. to sell under the OpenRTOS brand.  Low cost OpenRTOS\r
  61     licenses offer ticketed support, indemnification and commercial middleware.\r
  62 \r
  63     http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
  64     engineered and independently SIL3 certified version for use in safety and\r
  65     mission critical applications that require provable dependability.\r
  66 \r
  67     1 tab == 4 spaces!\r
  68 */\r
  69 \r
  70 /*-----------------------------------------------------------\r
  71  * Implementation of functions defined in portable.h for the SH2A port.\r
  72  *----------------------------------------------------------*/\r
  73 \r
  74 /* Scheduler includes. */\r
  75 #include "FreeRTOS.h"\r
  76 #include "task.h"\r
  77 \r
  78 /* Library includes. */\r
  79 #include "string.h"\r
  80 \r
  81 /* Hardware specifics. */\r
  82 #include "iodefine.h"\r
  83 \r
  84 /*-----------------------------------------------------------*/\r
  85 \r
  86 /* Tasks should start with interrupts enabled and in Supervisor mode, therefore\r
  87 PSW is set with U and I set, and PM and IPL clear. */\r
  88 #define portINITIAL_PSW     ( ( StackType_t ) 0x00030000 )\r
  89 #define portINITIAL_FPSW    ( ( StackType_t ) 0x00000100 )\r
  90 \r
  91 /* These macros allow a critical section to be added around the call to\r
  92 xTaskIncrementTick(), which is only ever called from interrupts at the kernel\r
  93 priority - ie a known priority.  Therefore these local macros are a slight\r
  94 optimisation compared to calling the global SET/CLEAR_INTERRUPT_MASK macros,\r
  95 which would require the old IPL to be read first and stored in a local variable. */\r
  96 #define portDISABLE_INTERRUPTS_FROM_KERNEL_ISR()        __asm volatile ( "MVTIPL        %0" ::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY) )\r
  97 #define portENABLE_INTERRUPTS_FROM_KERNEL_ISR()         __asm volatile ( "MVTIPL        %0" ::"i"(configKERNEL_INTERRUPT_PRIORITY) )\r
  98 \r
  99 /*-----------------------------------------------------------*/\r
 100 \r
 101 /*\r
 102  * Function to start the first task executing - written in asm code as direct\r
 103  * access to registers is required.\r
 104  */\r
 105 static void prvStartFirstTask( void ) __attribute__((naked));\r
 106 \r
 107 /*\r
 108  * Software interrupt handler.  Performs the actual context switch (saving and\r
 109  * restoring of registers).  Written in asm code as direct register access is\r
 110  * required.\r
 111  */\r
 112 void vSoftwareInterruptISR( void ) __attribute__((naked));\r
 113 \r
 114 /*\r
 115  * The tick interrupt handler.\r
 116  */\r
 117 void vTickISR( void ) __attribute__((interrupt));\r
 118 \r
 119 /*-----------------------------------------------------------*/\r
 120 \r
 121 extern void *pxCurrentTCB;\r
 122 \r
 123 /*-----------------------------------------------------------*/\r
 124 \r
 125 /*\r
 126  * See header file for description.\r
 127  */\r
 128 StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )\r
 129 {\r
 130         /* R0 is not included as it is the stack pointer. */\r
 131 \r
 132         *pxTopOfStack = 0x00;\r
 133         pxTopOfStack--;\r
 134         *pxTopOfStack = portINITIAL_PSW;\r
 135         pxTopOfStack--;\r
 136         *pxTopOfStack = ( StackType_t ) pxCode;\r
 137 \r
 138         /* When debugging it can be useful if every register is set to a known\r
 139         value.  Otherwise code space can be saved by just setting the registers\r
 140         that need to be set. */\r
 141         #ifdef USE_FULL_REGISTER_INITIALISATION\r
 142         {\r
 143                 pxTopOfStack--;\r
 144                 *pxTopOfStack = 0xffffffff;     /* r15. */\r
 145                 pxTopOfStack--;\r
 146                 *pxTopOfStack = 0xeeeeeeee;\r
 147                 pxTopOfStack--;\r
 148                 *pxTopOfStack = 0xdddddddd;\r
 149                 pxTopOfStack--;\r
 150                 *pxTopOfStack = 0xcccccccc;\r
 151                 pxTopOfStack--;\r
 152                 *pxTopOfStack = 0xbbbbbbbb;\r
 153                 pxTopOfStack--;\r
 154                 *pxTopOfStack = 0xaaaaaaaa;\r
 155                 pxTopOfStack--;\r
 156                 *pxTopOfStack = 0x99999999;\r
 157                 pxTopOfStack--;\r
 158                 *pxTopOfStack = 0x88888888;\r
 159                 pxTopOfStack--;\r
 160                 *pxTopOfStack = 0x77777777;\r
 161                 pxTopOfStack--;\r
 162                 *pxTopOfStack = 0x66666666;\r
 163                 pxTopOfStack--;\r
 164                 *pxTopOfStack = 0x55555555;\r
 165                 pxTopOfStack--;\r
 166                 *pxTopOfStack = 0x44444444;\r
 167                 pxTopOfStack--;\r
 168                 *pxTopOfStack = 0x33333333;\r
 169                 pxTopOfStack--;\r
 170                 *pxTopOfStack = 0x22222222;\r
 171                 pxTopOfStack--;\r
 172         }\r
 173         #else\r
 174         {\r
 175                 pxTopOfStack -= 15;\r
 176         }\r
 177         #endif\r
 178 \r
 179         *pxTopOfStack = ( StackType_t ) pvParameters; /* R1 */\r
 180         pxTopOfStack--;\r
 181         *pxTopOfStack = portINITIAL_FPSW;\r
 182         pxTopOfStack--;\r
 183         *pxTopOfStack = 0x12345678; /* Accumulator. */\r
 184         pxTopOfStack--;\r
 185         *pxTopOfStack = 0x87654321; /* Accumulator. */\r
 186 \r
 187         return pxTopOfStack;\r
 188 }\r
 189 /*-----------------------------------------------------------*/\r
 190 \r
 191 BaseType_t xPortStartScheduler( void )\r
 192 {\r
 193 extern void vApplicationSetupTimerInterrupt( void );\r
 194 \r
 195         /* Use pxCurrentTCB just so it does not get optimised away. */\r
 196         if( pxCurrentTCB != NULL )\r
 197         {\r
 198                 /* Call an application function to set up the timer that will generate the\r
 199                 tick interrupt.  This way the application can decide which peripheral to\r
 200                 use.  A demo application is provided to show a suitable example. */\r
 201                 vApplicationSetupTimerInterrupt();\r
 202 \r
 203                 /* Enable the software interrupt. */\r
 204                 _IEN( _ICU_SWINT ) = 1;\r
 205 \r
 206                 /* Ensure the software interrupt is clear. */\r
 207                 _IR( _ICU_SWINT ) = 0;\r
 208 \r
 209                 /* Ensure the software interrupt is set to the kernel priority. */\r
 210                 _IPR( _ICU_SWINT ) = configKERNEL_INTERRUPT_PRIORITY;\r
 211 \r
 212                 /* Start the first task. */\r
 213                 prvStartFirstTask();\r
 214         }\r
 215 \r
 216         /* Should not get here. */\r
 217         return pdFAIL;\r
 218 }\r
 219 /*-----------------------------------------------------------*/\r
 220 \r
 221 void vPortEndScheduler( void )\r
 222 {\r
 223         /* Not implemented in ports where there is nothing to return to.\r
 224         Artificially force an assert. */\r
 225         configASSERT( pxCurrentTCB == NULL );\r
 226 }\r
 227 /*-----------------------------------------------------------*/\r
 228 \r
 229 static void prvStartFirstTask( void )\r
 230 {\r
 231         __asm volatile\r
 232         (\r
 233                 /* When starting the scheduler there is nothing that needs moving to the\r
 234                 interrupt stack because the function is not called from an interrupt.\r
 235                 Just ensure the current stack is the user stack. */\r
 236                 "SETPSW         U                                               \n" \\r
 237 \r
 238                 /* Obtain the location of the stack associated with which ever task\r
 239                 pxCurrentTCB is currently pointing to. */\r
 240                 "MOV.L          #_pxCurrentTCB, R15             \n" \\r
 241                 "MOV.L          [R15], R15                              \n" \\r
 242                 "MOV.L          [R15], R0                               \n" \\r
 243 \r
 244                 /* Restore the registers from the stack of the task pointed to by\r
 245                 pxCurrentTCB. */\r
 246             "POP                R15                                             \n" \\r
 247 \r
 248                 /* Accumulator low 32 bits. */\r
 249             "MVTACLO    R15                                     \n" \\r
 250             "POP                R15                                             \n" \\r
 251 \r
 252                 /* Accumulator high 32 bits. */\r
 253             "MVTACHI    R15                                     \n" \\r
 254             "POP                R15                                             \n" \\r
 255 \r
 256                 /* Floating point status word. */\r
 257             "MVTC               R15, FPSW                               \n" \\r
 258 \r
 259                 /* R1 to R15 - R0 is not included as it is the SP. */\r
 260             "POPM               R1-R15                                  \n" \\r
 261 \r
 262                 /* This pops the remaining registers. */\r
 263             "RTE                                                                \n" \\r
 264             "NOP                                                                \n" \\r
 265             "NOP                                                                \n"\r
 266         );\r
 267 }\r
 268 /*-----------------------------------------------------------*/\r
 269 \r
 270 void vSoftwareInterruptISR( void )\r
 271 {\r
 272         __asm volatile\r
 273         (\r
 274                 /* Re-enable interrupts. */\r
 275                 "SETPSW         I                                                       \n" \\r
 276 \r
 277                 /* Move the data that was automatically pushed onto the interrupt stack when\r
 278                 the interrupt occurred from the interrupt stack to the user stack.\r
 279 \r
 280                 R15 is saved before it is clobbered. */\r
 281                 "PUSH.L         R15                                                     \n" \\r
 282 \r
 283                 /* Read the user stack pointer. */\r
 284                 "MVFC           USP, R15                                        \n" \\r
 285 \r
 286                 /* Move the address down to the data being moved. */\r
 287                 "SUB            #12, R15                                        \n" \\r
 288                 "MVTC           R15, USP                                        \n" \\r
 289 \r
 290                 /* Copy the data across, R15, then PC, then PSW. */\r
 291                 "MOV.L          [ R0 ], [ R15 ]                         \n" \\r
 292                 "MOV.L          4[ R0 ], 4[ R15 ]                       \n" \\r
 293                 "MOV.L          8[ R0 ], 8[ R15 ]                       \n" \\r
 294 \r
 295                 /* Move the interrupt stack pointer to its new correct position. */\r
 296                 "ADD            #12, R0                                         \n" \\r
 297 \r
 298                 /* All the rest of the registers are saved directly to the user stack. */\r
 299                 "SETPSW         U                                                       \n" \\r
 300 \r
 301                 /* Save the rest of the general registers (R15 has been saved already). */\r
 302                 "PUSHM          R1-R14                                          \n" \\r
 303 \r
 304                 /* Save the FPSW and accumulator. */\r
 305                 "MVFC           FPSW, R15                                       \n" \\r
 306                 "PUSH.L         R15                                                     \n" \\r
 307                 "MVFACHI        R15                                                     \n" \\r
 308                 "PUSH.L         R15                                                     \n" \\r
 309 \r
 310                 /* Middle word. */\r
 311                 "MVFACMI        R15                                                     \n" \\r
 312 \r
 313                 /* Shifted left as it is restored to the low order word. */\r
 314                 "SHLL           #16, R15                                        \n" \\r
 315                 "PUSH.L         R15                                                     \n" \\r
 316 \r
 317                 /* Save the stack pointer to the TCB. */\r
 318                 "MOV.L          #_pxCurrentTCB, R15                     \n" \\r
 319                 "MOV.L          [ R15 ], R15                            \n" \\r
 320                 "MOV.L          R0, [ R15 ]                                     \n" \\r
 321 \r
 322                 /* Ensure the interrupt mask is set to the syscall priority while the kernel\r
 323                 structures are being accessed. */\r
 324                 "MVTIPL         %0                                                      \n" \\r
 325 \r
 326                 /* Select the next task to run. */\r
 327                 "BSR.A          _vTaskSwitchContext                     \n" \\r
 328 \r
 329                 /* Reset the interrupt mask as no more data structure access is required. */\r
 330                 "MVTIPL         %1                                                      \n" \\r
 331 \r
 332                 /* Load the stack pointer of the task that is now selected as the Running\r
 333                 state task from its TCB. */\r
 334                 "MOV.L          #_pxCurrentTCB,R15                      \n" \\r
 335                 "MOV.L          [ R15 ], R15                            \n" \\r
 336                 "MOV.L          [ R15 ], R0                                     \n" \\r
 337 \r
 338                 /* Restore the context of the new task.  The PSW (Program Status Word) and\r
 339                 PC will be popped by the RTE instruction. */\r
 340                 "POP            R15                                                     \n" \\r
 341                 "MVTACLO        R15                                                     \n" \\r
 342                 "POP            R15                                                     \n" \\r
 343                 "MVTACHI        R15                                                     \n" \\r
 344                 "POP            R15                                                     \n" \\r
 345                 "MVTC           R15, FPSW                                       \n" \\r
 346                 "POPM           R1-R15                                          \n" \\r
 347                 "RTE                                                                    \n" \\r
 348                 "NOP                                                                    \n" \\r
 349                 "NOP                                                                      "\r
 350                 :: "i"(configMAX_SYSCALL_INTERRUPT_PRIORITY), "i"(configKERNEL_INTERRUPT_PRIORITY)\r
 351         );\r
 352 }\r
 353 /*-----------------------------------------------------------*/\r
 354 \r
 355 void vTickISR( void )\r
 356 {\r
 357         /* Re-enabled interrupts. */\r
 358         __asm volatile( "SETPSW I" );\r
 359 \r
 360         /* Increment the tick, and perform any processing the new tick value\r
 361         necessitates.  Ensure IPL is at the max syscall value first. */\r
 362         portDISABLE_INTERRUPTS_FROM_KERNEL_ISR();\r
 363         {\r
 364                 if( xTaskIncrementTick() != pdFALSE )\r
 365                 {\r
 366                         taskYIELD();\r
 367                 }\r
 368         }\r
 369         portENABLE_INTERRUPTS_FROM_KERNEL_ISR();\r
 370 }\r
 371 /*-----------------------------------------------------------*/\r
 372 \r
 373 uint32_t ulPortGetIPL( void )\r
 374 {\r
 375         __asm volatile\r
 376         (\r
 377                 "MVFC   PSW, R1                 \n"     \\r
 378                 "SHLR   #24, R1                 \n"     \\r
 379                 "RTS                                      "\r
 380         );\r
 381 \r
 382         /* This will never get executed, but keeps the compiler from complaining. */\r
 383         return 0;\r
 384 }\r
 385 /*-----------------------------------------------------------*/\r
 386 \r
 387 void vPortSetIPL( uint32_t ulNewIPL )\r
 388 {\r
 389         __asm volatile\r
 390         (\r
 391                 "PUSH   R5                              \n" \\r
 392                 "MVFC   PSW, R5                 \n"     \\r
 393                 "SHLL   #24, R1                 \n" \\r
 394                 "AND    #-0F000001H, R5 \n" \\r
 395                 "OR             R1, R5                  \n" \\r
 396                 "MVTC   R5, PSW                 \n" \\r
 397                 "POP    R5                              \n" \\r
 398                 "RTS                                      "\r
 399          );\r
 400 }\r