git.sur5r.net Git - freertos/blob - FreeRTOS/Source/portable/GCC/RX600/port.c

   1 /*\r
   2     FreeRTOS V7.6.0 - Copyright (C) 2013 Real Time Engineers Ltd.\r
   3     All rights reserved\r
   4 \r
   5     VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
   6 \r
   7     ***************************************************************************\r
   8      *                                                                       *\r
   9      *    FreeRTOS provides completely free yet professionally developed,    *\r
  10      *    robust, strictly quality controlled, supported, and cross          *\r
  11      *    platform software that has become a de facto standard.             *\r
  12      *                                                                       *\r
  13      *    Help yourself get started quickly and support the FreeRTOS         *\r
  14      *    project by purchasing a FreeRTOS tutorial book, reference          *\r
  15      *    manual, or both from: http://www.FreeRTOS.org/Documentation        *\r
  16      *                                                                       *\r
  17      *    Thank you!                                                         *\r
  18      *                                                                       *\r
  19     ***************************************************************************\r
  20 \r
  21     This file is part of the FreeRTOS distribution.\r
  22 \r
  23     FreeRTOS is free software; you can redistribute it and/or modify it under\r
  24     the terms of the GNU General Public License (version 2) as published by the\r
  25     Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.\r
  26 \r
  27     >>! NOTE: The modification to the GPL is included to allow you to distribute\r
  28     >>! a combined work that includes FreeRTOS without being obliged to provide\r
  29     >>! the source code for proprietary components outside of the FreeRTOS\r
  30     >>! kernel.\r
  31 \r
  32     FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
  33     WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
  34     FOR A PARTICULAR PURPOSE.  Full license text is available from the following\r
  35     link: http://www.freertos.org/a00114.html\r
  36 \r
  37     1 tab == 4 spaces!\r
  38 \r
  39     ***************************************************************************\r
  40      *                                                                       *\r
  41      *    Having a problem?  Start by reading the FAQ "My application does   *\r
  42      *    not run, what could be wrong?"                                     *\r
  43      *                                                                       *\r
  44      *    http://www.FreeRTOS.org/FAQHelp.html                               *\r
  45      *                                                                       *\r
  46     ***************************************************************************\r
  47 \r
  48     http://www.FreeRTOS.org - Documentation, books, training, latest versions,\r
  49     license and Real Time Engineers Ltd. contact details.\r
  50 \r
  51     http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
  52     including FreeRTOS+Trace - an indispensable productivity tool, a DOS\r
  53     compatible FAT file system, and our tiny thread aware UDP/IP stack.\r
  54 \r
  55     http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High\r
  56     Integrity Systems to sell under the OpenRTOS brand.  Low cost OpenRTOS\r
  57     licenses offer ticketed support, indemnification and middleware.\r
  58 \r
  59     http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
  60     engineered and independently SIL3 certified version for use in safety and\r
  61     mission critical applications that require provable dependability.\r
  62 \r
  63     1 tab == 4 spaces!\r
  64 */\r
  65 \r
  66 /*-----------------------------------------------------------\r
  67  * Implementation of functions defined in portable.h for the SH2A port.\r
  68  *----------------------------------------------------------*/\r
  69 \r
  70 /* Scheduler includes. */\r
  71 #include "FreeRTOS.h"\r
  72 #include "task.h"\r
  73 \r
  74 /* Library includes. */\r
  75 #include "string.h"\r
  76 \r
  77 /* Hardware specifics. */\r
  78 #include "iodefine.h"\r
  79 \r
  80 /*-----------------------------------------------------------*/\r
  81 \r
  82 /* Tasks should start with interrupts enabled and in Supervisor mode, therefore\r
  83 PSW is set with U and I set, and PM and IPL clear. */\r
  84 #define portINITIAL_PSW     ( ( StackType_t ) 0x00030000 )\r
  85 #define portINITIAL_FPSW    ( ( StackType_t ) 0x00000100 )\r
  86 \r
  87 /* These macros allow a critical section to be added around the call to\r
  88 xTaskIncrementTick(), which is only ever called from interrupts at the kernel\r
  89 priority - ie a known priority.  Therefore these local macros are a slight\r
  90 optimisation compared to calling the global SET/CLEAR_INTERRUPT_MASK macros,\r
  91 which would require the old IPL to be read first and stored in a local variable. */\r
  92 #define portDISABLE_INTERRUPTS_FROM_KERNEL_ISR()        __asm volatile ( "MVTIPL        %0" ::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY) )\r
  93 #define portENABLE_INTERRUPTS_FROM_KERNEL_ISR()         __asm volatile ( "MVTIPL        %0" ::"i"(configKERNEL_INTERRUPT_PRIORITY) )\r
  94 \r
  95 /*-----------------------------------------------------------*/\r
  96 \r
  97 /*\r
  98  * Function to start the first task executing - written in asm code as direct\r
  99  * access to registers is required.\r
 100  */\r
 101 static void prvStartFirstTask( void ) __attribute__((naked));\r
 102 \r
 103 /*\r
 104  * Software interrupt handler.  Performs the actual context switch (saving and\r
 105  * restoring of registers).  Written in asm code as direct register access is\r
 106  * required.\r
 107  */\r
 108 void vSoftwareInterruptISR( void ) __attribute__((naked));\r
 109 \r
 110 /*\r
 111  * The tick interrupt handler.\r
 112  */\r
 113 void vTickISR( void ) __attribute__((interrupt));\r
 114 \r
 115 /*-----------------------------------------------------------*/\r
 116 \r
 117 extern void *pxCurrentTCB;\r
 118 \r
 119 /*-----------------------------------------------------------*/\r
 120 \r
 121 /*\r
 122  * See header file for description.\r
 123  */\r
 124 StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters )\r
 125 {\r
 126         /* R0 is not included as it is the stack pointer. */\r
 127 \r
 128         *pxTopOfStack = 0x00;\r
 129         pxTopOfStack--;\r
 130         *pxTopOfStack = portINITIAL_PSW;\r
 131         pxTopOfStack--;\r
 132         *pxTopOfStack = ( StackType_t ) pxCode;\r
 133 \r
 134         /* When debugging it can be useful if every register is set to a known\r
 135         value.  Otherwise code space can be saved by just setting the registers\r
 136         that need to be set. */\r
 137         #ifdef USE_FULL_REGISTER_INITIALISATION\r
 138         {\r
 139                 pxTopOfStack--;\r
 140                 *pxTopOfStack = 0xffffffff;     /* r15. */\r
 141                 pxTopOfStack--;\r
 142                 *pxTopOfStack = 0xeeeeeeee;\r
 143                 pxTopOfStack--;\r
 144                 *pxTopOfStack = 0xdddddddd;\r
 145                 pxTopOfStack--;\r
 146                 *pxTopOfStack = 0xcccccccc;\r
 147                 pxTopOfStack--;\r
 148                 *pxTopOfStack = 0xbbbbbbbb;\r
 149                 pxTopOfStack--;\r
 150                 *pxTopOfStack = 0xaaaaaaaa;\r
 151                 pxTopOfStack--;\r
 152                 *pxTopOfStack = 0x99999999;\r
 153                 pxTopOfStack--;\r
 154                 *pxTopOfStack = 0x88888888;\r
 155                 pxTopOfStack--;\r
 156                 *pxTopOfStack = 0x77777777;\r
 157                 pxTopOfStack--;\r
 158                 *pxTopOfStack = 0x66666666;\r
 159                 pxTopOfStack--;\r
 160                 *pxTopOfStack = 0x55555555;\r
 161                 pxTopOfStack--;\r
 162                 *pxTopOfStack = 0x44444444;\r
 163                 pxTopOfStack--;\r
 164                 *pxTopOfStack = 0x33333333;\r
 165                 pxTopOfStack--;\r
 166                 *pxTopOfStack = 0x22222222;\r
 167                 pxTopOfStack--;\r
 168         }\r
 169         #else\r
 170         {\r
 171                 pxTopOfStack -= 15;\r
 172         }\r
 173         #endif\r
 174 \r
 175         *pxTopOfStack = ( StackType_t ) pvParameters; /* R1 */\r
 176         pxTopOfStack--;\r
 177         *pxTopOfStack = portINITIAL_FPSW;\r
 178         pxTopOfStack--;\r
 179         *pxTopOfStack = 0x12345678; /* Accumulator. */\r
 180         pxTopOfStack--;\r
 181         *pxTopOfStack = 0x87654321; /* Accumulator. */\r
 182 \r
 183         return pxTopOfStack;\r
 184 }\r
 185 /*-----------------------------------------------------------*/\r
 186 \r
 187 BaseType_t xPortStartScheduler( void )\r
 188 {\r
 189 extern void vApplicationSetupTimerInterrupt( void );\r
 190 \r
 191         /* Use pxCurrentTCB just so it does not get optimised away. */\r
 192         if( pxCurrentTCB != NULL )\r
 193         {\r
 194                 /* Call an application function to set up the timer that will generate the\r
 195                 tick interrupt.  This way the application can decide which peripheral to\r
 196                 use.  A demo application is provided to show a suitable example. */\r
 197                 vApplicationSetupTimerInterrupt();\r
 198 \r
 199                 /* Enable the software interrupt. */\r
 200                 _IEN( _ICU_SWINT ) = 1;\r
 201 \r
 202                 /* Ensure the software interrupt is clear. */\r
 203                 _IR( _ICU_SWINT ) = 0;\r
 204 \r
 205                 /* Ensure the software interrupt is set to the kernel priority. */\r
 206                 _IPR( _ICU_SWINT ) = configKERNEL_INTERRUPT_PRIORITY;\r
 207 \r
 208                 /* Start the first task. */\r
 209                 prvStartFirstTask();\r
 210         }\r
 211 \r
 212         /* Should not get here. */\r
 213         return pdFAIL;\r
 214 }\r
 215 /*-----------------------------------------------------------*/\r
 216 \r
 217 void vPortEndScheduler( void )\r
 218 {\r
 219         /* Not implemented in ports where there is nothing to return to.\r
 220         Artificially force an assert. */\r
 221         configASSERT( pxCurrentTCB == NULL );\r
 222 }\r
 223 /*-----------------------------------------------------------*/\r
 224 \r
 225 static void prvStartFirstTask( void )\r
 226 {\r
 227         __asm volatile\r
 228         (\r
 229                 /* When starting the scheduler there is nothing that needs moving to the\r
 230                 interrupt stack because the function is not called from an interrupt.\r
 231                 Just ensure the current stack is the user stack. */\r
 232                 "SETPSW         U                                               \n" \\r
 233 \r
 234                 /* Obtain the location of the stack associated with which ever task\r
 235                 pxCurrentTCB is currently pointing to. */\r
 236                 "MOV.L          #_pxCurrentTCB, R15             \n" \\r
 237                 "MOV.L          [R15], R15                              \n" \\r
 238                 "MOV.L          [R15], R0                               \n" \\r
 239 \r
 240                 /* Restore the registers from the stack of the task pointed to by\r
 241                 pxCurrentTCB. */\r
 242             "POP                R15                                             \n" \\r
 243 \r
 244                 /* Accumulator low 32 bits. */\r
 245             "MVTACLO    R15                                     \n" \\r
 246             "POP                R15                                             \n" \\r
 247 \r
 248                 /* Accumulator high 32 bits. */\r
 249             "MVTACHI    R15                                     \n" \\r
 250             "POP                R15                                             \n" \\r
 251 \r
 252                 /* Floating point status word. */\r
 253             "MVTC               R15, FPSW                               \n" \\r
 254 \r
 255                 /* R1 to R15 - R0 is not included as it is the SP. */\r
 256             "POPM               R1-R15                                  \n" \\r
 257 \r
 258                 /* This pops the remaining registers. */\r
 259             "RTE                                                                \n" \\r
 260             "NOP                                                                \n" \\r
 261             "NOP                                                                \n"\r
 262         );\r
 263 }\r
 264 /*-----------------------------------------------------------*/\r
 265 \r
 266 void vSoftwareInterruptISR( void )\r
 267 {\r
 268         __asm volatile\r
 269         (\r
 270                 /* Re-enable interrupts. */\r
 271                 "SETPSW         I                                                       \n" \\r
 272 \r
 273                 /* Move the data that was automatically pushed onto the interrupt stack when\r
 274                 the interrupt occurred from the interrupt stack to the user stack.\r
 275 \r
 276                 R15 is saved before it is clobbered. */\r
 277                 "PUSH.L         R15                                                     \n" \\r
 278 \r
 279                 /* Read the user stack pointer. */\r
 280                 "MVFC           USP, R15                                        \n" \\r
 281 \r
 282                 /* Move the address down to the data being moved. */\r
 283                 "SUB            #12, R15                                        \n" \\r
 284                 "MVTC           R15, USP                                        \n" \\r
 285 \r
 286                 /* Copy the data across, R15, then PC, then PSW. */\r
 287                 "MOV.L          [ R0 ], [ R15 ]                         \n" \\r
 288                 "MOV.L          4[ R0 ], 4[ R15 ]                       \n" \\r
 289                 "MOV.L          8[ R0 ], 8[ R15 ]                       \n" \\r
 290 \r
 291                 /* Move the interrupt stack pointer to its new correct position. */\r
 292                 "ADD            #12, R0                                         \n" \\r
 293 \r
 294                 /* All the rest of the registers are saved directly to the user stack. */\r
 295                 "SETPSW         U                                                       \n" \\r
 296 \r
 297                 /* Save the rest of the general registers (R15 has been saved already). */\r
 298                 "PUSHM          R1-R14                                          \n" \\r
 299 \r
 300                 /* Save the FPSW and accumulator. */\r
 301                 "MVFC           FPSW, R15                                       \n" \\r
 302                 "PUSH.L         R15                                                     \n" \\r
 303                 "MVFACHI        R15                                                     \n" \\r
 304                 "PUSH.L         R15                                                     \n" \\r
 305 \r
 306                 /* Middle word. */\r
 307                 "MVFACMI        R15                                                     \n" \\r
 308 \r
 309                 /* Shifted left as it is restored to the low order word. */\r
 310                 "SHLL           #16, R15                                        \n" \\r
 311                 "PUSH.L         R15                                                     \n" \\r
 312 \r
 313                 /* Save the stack pointer to the TCB. */\r
 314                 "MOV.L          #_pxCurrentTCB, R15                     \n" \\r
 315                 "MOV.L          [ R15 ], R15                            \n" \\r
 316                 "MOV.L          R0, [ R15 ]                                     \n" \\r
 317 \r
 318                 /* Ensure the interrupt mask is set to the syscall priority while the kernel\r
 319                 structures are being accessed. */\r
 320                 "MVTIPL         %0                                                      \n" \\r
 321 \r
 322                 /* Select the next task to run. */\r
 323                 "BSR.A          _vTaskSwitchContext                     \n" \\r
 324 \r
 325                 /* Reset the interrupt mask as no more data structure access is required. */\r
 326                 "MVTIPL         %1                                                      \n" \\r
 327 \r
 328                 /* Load the stack pointer of the task that is now selected as the Running\r
 329                 state task from its TCB. */\r
 330                 "MOV.L          #_pxCurrentTCB,R15                      \n" \\r
 331                 "MOV.L          [ R15 ], R15                            \n" \\r
 332                 "MOV.L          [ R15 ], R0                                     \n" \\r
 333 \r
 334                 /* Restore the context of the new task.  The PSW (Program Status Word) and\r
 335                 PC will be popped by the RTE instruction. */\r
 336                 "POP            R15                                                     \n" \\r
 337                 "MVTACLO        R15                                                     \n" \\r
 338                 "POP            R15                                                     \n" \\r
 339                 "MVTACHI        R15                                                     \n" \\r
 340                 "POP            R15                                                     \n" \\r
 341                 "MVTC           R15, FPSW                                       \n" \\r
 342                 "POPM           R1-R15                                          \n" \\r
 343                 "RTE                                                                    \n" \\r
 344                 "NOP                                                                    \n" \\r
 345                 "NOP                                                                      "\r
 346                 :: "i"(configMAX_SYSCALL_INTERRUPT_PRIORITY), "i"(configKERNEL_INTERRUPT_PRIORITY)\r
 347         );\r
 348 }\r
 349 /*-----------------------------------------------------------*/\r
 350 \r
 351 void vTickISR( void )\r
 352 {\r
 353         /* Re-enabled interrupts. */\r
 354         __asm volatile( "SETPSW I" );\r
 355 \r
 356         /* Increment the tick, and perform any processing the new tick value\r
 357         necessitates.  Ensure IPL is at the max syscall value first. */\r
 358         portDISABLE_INTERRUPTS_FROM_KERNEL_ISR();\r
 359         {\r
 360                 if( xTaskIncrementTick() != pdFALSE )\r
 361                 {\r
 362                         taskYIELD();\r
 363                 }\r
 364         }\r
 365         portENABLE_INTERRUPTS_FROM_KERNEL_ISR();\r
 366 }\r
 367 /*-----------------------------------------------------------*/\r
 368 \r
 369 uint32_t ulPortGetIPL( void )\r
 370 {\r
 371         __asm volatile\r
 372         (\r
 373                 "MVFC   PSW, R1                 \n"     \\r
 374                 "SHLR   #24, R1                 \n"     \\r
 375                 "RTS                                      "\r
 376         );\r
 377 \r
 378         /* This will never get executed, but keeps the compiler from complaining. */\r
 379         return 0;\r
 380 }\r
 381 /*-----------------------------------------------------------*/\r
 382 \r
 383 void vPortSetIPL( uint32_t ulNewIPL )\r
 384 {\r
 385         __asm volatile\r
 386         (\r
 387                 "PUSH   R5                              \n" \\r
 388                 "MVFC   PSW, R5                 \n"     \\r
 389                 "SHLL   #24, R1                 \n" \\r
 390                 "AND    #-0F000001H, R5 \n" \\r
 391                 "OR             R1, R5                  \n" \\r
 392                 "MVTC   R5, PSW                 \n" \\r
 393                 "POP    R5                              \n" \\r
 394                 "RTS                                      "\r
 395          );\r
 396 }\r