2 FreeRTOS V8.0.1 - Copyright (C) 2014 Real Time Engineers Ltd.
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5 VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
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7 ***************************************************************************
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9 * FreeRTOS provides completely free yet professionally developed, *
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10 * robust, strictly quality controlled, supported, and cross *
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11 * platform software that has become a de facto standard. *
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13 * Help yourself get started quickly and support the FreeRTOS *
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14 * project by purchasing a FreeRTOS tutorial book, reference *
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15 * manual, or both from: http://www.FreeRTOS.org/Documentation *
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19 ***************************************************************************
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21 This file is part of the FreeRTOS distribution.
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23 FreeRTOS is free software; you can redistribute it and/or modify it under
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24 the terms of the GNU General Public License (version 2) as published by the
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25 Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.
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27 >>! NOTE: The modification to the GPL is included to allow you to !<<
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28 >>! distribute a combined work that includes FreeRTOS without being !<<
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29 >>! obliged to provide the source code for proprietary components !<<
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30 >>! outside of the FreeRTOS kernel. !<<
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32 FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
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33 WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
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34 FOR A PARTICULAR PURPOSE. Full license text is available from the following
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35 link: http://www.freertos.org/a00114.html
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39 ***************************************************************************
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41 * Having a problem? Start by reading the FAQ "My application does *
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42 * not run, what could be wrong?" *
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44 * http://www.FreeRTOS.org/FAQHelp.html *
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46 ***************************************************************************
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48 http://www.FreeRTOS.org - Documentation, books, training, latest versions,
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49 license and Real Time Engineers Ltd. contact details.
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51 http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
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52 including FreeRTOS+Trace - an indispensable productivity tool, a DOS
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53 compatible FAT file system, and our tiny thread aware UDP/IP stack.
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55 http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High
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56 Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS
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57 licenses offer ticketed support, indemnification and middleware.
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59 http://www.SafeRTOS.com - High Integrity Systems also provide a safety
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60 engineered and independently SIL3 certified version for use in safety and
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61 mission critical applications that require provable dependability.
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66 /*-----------------------------------------------------------
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67 * Implementation of functions defined in portable.h for the SH2A port.
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68 *----------------------------------------------------------*/
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70 /* Scheduler includes. */
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71 #include "FreeRTOS.h"
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74 /* Library includes. */
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77 /* Hardware specifics. */
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78 #include "iodefine.h"
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80 /*-----------------------------------------------------------*/
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82 /* Tasks should start with interrupts enabled and in Supervisor mode, therefore
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83 PSW is set with U and I set, and PM and IPL clear. */
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84 #define portINITIAL_PSW ( ( StackType_t ) 0x00030000 )
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85 #define portINITIAL_FPSW ( ( StackType_t ) 0x00000100 )
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87 /* These macros allow a critical section to be added around the call to
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88 xTaskIncrementTick(), which is only ever called from interrupts at the kernel
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89 priority - ie a known priority. Therefore these local macros are a slight
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90 optimisation compared to calling the global SET/CLEAR_INTERRUPT_MASK macros,
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91 which would require the old IPL to be read first and stored in a local variable. */
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92 #define portMASK_INTERRUPTS_FROM_KERNEL_ISR() __asm volatile ( "MVTIPL %0" ::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY) )
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93 #define portUNMASK_INTERRUPTS_FROM_KERNEL_ISR() __asm volatile ( "MVTIPL %0" ::"i"(configKERNEL_INTERRUPT_PRIORITY) )
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95 /*-----------------------------------------------------------*/
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98 * Function to start the first task executing - written in asm code as direct
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99 * access to registers is required.
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101 static void prvStartFirstTask( void ) __attribute__((naked));
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104 * Software interrupt handler. Performs the actual context switch (saving and
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105 * restoring of registers). Written in asm code as direct register access is
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108 void vSoftwareInterruptISR( void ) __attribute__((naked));
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111 * The tick interrupt handler.
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113 void vTickISR( void ) __attribute__((interrupt));
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115 /*-----------------------------------------------------------*/
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117 extern void *pxCurrentTCB;
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119 /*-----------------------------------------------------------*/
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122 * See header file for description.
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124 StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
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126 /* R0 is not included as it is the stack pointer. */
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128 *pxTopOfStack = 0x00;
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130 *pxTopOfStack = portINITIAL_PSW;
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132 *pxTopOfStack = ( StackType_t ) pxCode;
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134 /* When debugging it can be useful if every register is set to a known
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135 value. Otherwise code space can be saved by just setting the registers
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136 that need to be set. */
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137 #ifdef USE_FULL_REGISTER_INITIALISATION
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140 *pxTopOfStack = 0xffffffff; /* r15. */
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142 *pxTopOfStack = 0xeeeeeeee;
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144 *pxTopOfStack = 0xdddddddd;
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146 *pxTopOfStack = 0xcccccccc;
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148 *pxTopOfStack = 0xbbbbbbbb;
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150 *pxTopOfStack = 0xaaaaaaaa;
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152 *pxTopOfStack = 0x99999999;
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154 *pxTopOfStack = 0x88888888;
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156 *pxTopOfStack = 0x77777777;
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158 *pxTopOfStack = 0x66666666;
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160 *pxTopOfStack = 0x55555555;
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162 *pxTopOfStack = 0x44444444;
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164 *pxTopOfStack = 0x33333333;
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166 *pxTopOfStack = 0x22222222;
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171 pxTopOfStack -= 15;
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175 *pxTopOfStack = ( StackType_t ) pvParameters; /* R1 */
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177 *pxTopOfStack = portINITIAL_FPSW;
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179 *pxTopOfStack = 0x11111111; /* Accumulator 0. */
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181 *pxTopOfStack = 0x22222222; /* Accumulator 0. */
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183 *pxTopOfStack = 0x33333333; /* Accumulator 0. */
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185 *pxTopOfStack = 0x44444444; /* Accumulator 1. */
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187 *pxTopOfStack = 0x55555555; /* Accumulator 1. */
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189 *pxTopOfStack = 0x66666666; /* Accumulator 1. */
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191 return pxTopOfStack;
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193 /*-----------------------------------------------------------*/
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195 BaseType_t xPortStartScheduler( void )
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197 extern void vApplicationSetupTimerInterrupt( void );
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199 /* Use pxCurrentTCB just so it does not get optimised away. */
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200 if( pxCurrentTCB != NULL )
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202 /* Call an application function to set up the timer that will generate the
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203 tick interrupt. This way the application can decide which peripheral to
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204 use. A demo application is provided to show a suitable example. */
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205 vApplicationSetupTimerInterrupt();
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207 /* Enable the software interrupt. */
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208 _IEN( _ICU_SWINT ) = 1;
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210 /* Ensure the software interrupt is clear. */
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211 _IR( _ICU_SWINT ) = 0;
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213 /* Ensure the software interrupt is set to the kernel priority. */
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214 _IPR( _ICU_SWINT ) = configKERNEL_INTERRUPT_PRIORITY;
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216 /* Start the first task. */
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217 prvStartFirstTask();
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220 /* Should not get here. */
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223 /*-----------------------------------------------------------*/
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225 void vPortEndScheduler( void )
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227 /* Not implemented in ports where there is nothing to return to.
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228 Artificially force an assert. */
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229 configASSERT( pxCurrentTCB == NULL );
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231 /*-----------------------------------------------------------*/
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233 static void prvStartFirstTask( void )
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237 /* When starting the scheduler there is nothing that needs moving to the
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238 interrupt stack because the function is not called from an interrupt.
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239 Just ensure the current stack is the user stack. */
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242 /* Obtain the location of the stack associated with which ever task
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243 pxCurrentTCB is currently pointing to. */
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244 "MOV.L #_pxCurrentTCB, R15 \n" \
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245 "MOV.L [R15], R15 \n" \
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246 "MOV.L [R15], R0 \n" \
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248 /* Restore the registers from the stack of the task pointed to by
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252 /* Accumulator low 32 bits. */
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253 "MVTACLO R15, A0 \n" \
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256 /* Accumulator high 32 bits. */
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257 "MVTACHI R15, A0 \n" \
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260 /* Accumulator guard. */
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261 "MVTACGU R15, A0 \n" \
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264 /* Accumulator low 32 bits. */
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265 "MVTACLO R15, A1 \n" \
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268 /* Accumulator high 32 bits. */
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269 "MVTACHI R15, A1 \n" \
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272 /* Accumulator guard. */
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273 "MVTACGU R15, A1 \n" \
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276 /* Floating point status word. */
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277 "MVTC R15, FPSW \n" \
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279 /* R1 to R15 - R0 is not included as it is the SP. */
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282 /* This pops the remaining registers. */
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288 /*-----------------------------------------------------------*/
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290 void vSoftwareInterruptISR( void )
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294 /* Re-enable interrupts. */
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297 /* Move the data that was automatically pushed onto the interrupt stack when
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298 the interrupt occurred from the interrupt stack to the user stack.
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300 R15 is saved before it is clobbered. */
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303 /* Read the user stack pointer. */
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304 "MVFC USP, R15 \n" \
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306 /* Move the address down to the data being moved. */
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307 "SUB #12, R15 \n" \
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308 "MVTC R15, USP \n" \
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310 /* Copy the data across, R15, then PC, then PSW. */
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311 "MOV.L [ R0 ], [ R15 ] \n" \
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312 "MOV.L 4[ R0 ], 4[ R15 ] \n" \
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313 "MOV.L 8[ R0 ], 8[ R15 ] \n" \
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315 /* Move the interrupt stack pointer to its new correct position. */
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318 /* All the rest of the registers are saved directly to the user stack. */
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321 /* Save the rest of the general registers (R15 has been saved already). */
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322 "PUSHM R1-R14 \n" \
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324 /* Save the FPSW and accumulator. */
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325 "MVFC FPSW, R15 \n" \
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327 "MVFACGU #0, A1, R15 \n" \
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329 "MVFACHI #0, A1, R15 \n" \
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331 /* Low order word. */
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332 "MVFACLO #0, A1, R15 \n" \
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334 "MVFACGU #0, A0, R15 \n" \
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336 "MVFACHI #0, A0, R15 \n" \
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338 /* Low order word. */
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339 "MVFACLO #0, A0, R15 \n" \
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342 /* Save the stack pointer to the TCB. */
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343 "MOV.L #_pxCurrentTCB, R15 \n" \
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344 "MOV.L [ R15 ], R15 \n" \
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345 "MOV.L R0, [ R15 ] \n" \
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347 /* Ensure the interrupt mask is set to the syscall priority while the kernel
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348 structures are being accessed. */
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351 /* Select the next task to run. */
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352 "BSR.A _vTaskSwitchContext \n" \
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354 /* Reset the interrupt mask as no more data structure access is required. */
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357 /* Load the stack pointer of the task that is now selected as the Running
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358 state task from its TCB. */
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359 "MOV.L #_pxCurrentTCB,R15 \n" \
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360 "MOV.L [ R15 ], R15 \n" \
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361 "MOV.L [ R15 ], R0 \n" \
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363 /* Restore the context of the new task. The PSW (Program Status Word) and
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364 PC will be popped by the RTE instruction. */
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367 /* Accumulator low 32 bits. */
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368 "MVTACLO R15, A0 \n" \
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371 /* Accumulator high 32 bits. */
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372 "MVTACHI R15, A0 \n" \
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375 /* Accumulator guard. */
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376 "MVTACGU R15, A0 \n" \
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379 /* Accumulator low 32 bits. */
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380 "MVTACLO R15, A1 \n" \
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383 /* Accumulator high 32 bits. */
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384 "MVTACHI R15, A1 \n" \
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387 /* Accumulator guard. */
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388 "MVTACGU R15, A1 \n" \
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390 "MVTC R15, FPSW \n" \
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395 :: "i"(configMAX_SYSCALL_INTERRUPT_PRIORITY), "i"(configKERNEL_INTERRUPT_PRIORITY)
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398 /*-----------------------------------------------------------*/
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400 void vTickISR( void )
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402 /* Re-enabled interrupts. */
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403 __asm volatile( "SETPSW I" );
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405 /* Increment the tick, and perform any processing the new tick value
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406 necessitates. Ensure IPL is at the max syscall value first. */
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407 portMASK_INTERRUPTS_FROM_KERNEL_ISR();
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409 if( xTaskIncrementTick() != pdFALSE )
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414 portUNMASK_INTERRUPTS_FROM_KERNEL_ISR();
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416 /*-----------------------------------------------------------*/
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418 uint32_t ulPortGetIPL( void )
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422 "MVFC PSW, R1 \n" \
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423 "SHLR #24, R1 \n" \
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427 /* This will never get executed, but keeps the compiler from complaining. */
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430 /*-----------------------------------------------------------*/
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432 void vPortSetIPL( uint32_t ulNewIPL )
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437 "MVFC PSW, R5 \n" \
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438 "SHLL #24, R1 \n" \
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439 "AND #-0F000001H, R5 \n" \
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441 "MVTC R5, PSW \n" \
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