2 * FreeRTOS Kernel V10.3.0
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3 * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
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5 * Permission is hereby granted, free of charge, to any person obtaining a copy of
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6 * this software and associated documentation files (the "Software"), to deal in
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7 * the Software without restriction, including without limitation the rights to
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8 * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
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9 * the Software, and to permit persons to whom the Software is furnished to do so,
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10 * subject to the following conditions:
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12 * The above copyright notice and this permission notice shall be included in all
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13 * copies or substantial portions of the Software.
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15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
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17 * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
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18 * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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19 * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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20 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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22 * http://www.FreeRTOS.org
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23 * http://aws.amazon.com/freertos
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25 * 1 tab == 4 spaces!
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28 /*-----------------------------------------------------------
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29 * Implementation of functions defined in portable.h for the SH2A port.
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30 *----------------------------------------------------------*/
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32 /* Scheduler includes. */
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33 #include "FreeRTOS.h"
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36 /* Library includes. */
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39 /* Hardware specifics. */
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40 #include "iodefine.h"
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42 /*-----------------------------------------------------------*/
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44 /* Tasks should start with interrupts enabled and in Supervisor mode, therefore
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45 PSW is set with U and I set, and PM and IPL clear. */
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46 #define portINITIAL_PSW ( ( StackType_t ) 0x00030000 )
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47 #define portINITIAL_FPSW ( ( StackType_t ) 0x00000100 )
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49 /* These macros allow a critical section to be added around the call to
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50 xTaskIncrementTick(), which is only ever called from interrupts at the kernel
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51 priority - ie a known priority. Therefore these local macros are a slight
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52 optimisation compared to calling the global SET/CLEAR_INTERRUPT_MASK macros,
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53 which would require the old IPL to be read first and stored in a local variable. */
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54 #define portMASK_INTERRUPTS_FROM_KERNEL_ISR() __asm volatile ( "MVTIPL %0" ::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY) )
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55 #define portUNMASK_INTERRUPTS_FROM_KERNEL_ISR() __asm volatile ( "MVTIPL %0" ::"i"(configKERNEL_INTERRUPT_PRIORITY) )
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57 /*-----------------------------------------------------------*/
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60 * Function to start the first task executing - written in asm code as direct
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61 * access to registers is required.
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63 static void prvStartFirstTask( void ) __attribute__((naked));
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66 * Software interrupt handler. Performs the actual context switch (saving and
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67 * restoring of registers). Written in asm code as direct register access is
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70 void vSoftwareInterruptISR( void ) __attribute__((naked));
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73 * The tick interrupt handler.
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75 void vTickISR( void ) __attribute__((interrupt));
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77 /*-----------------------------------------------------------*/
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79 extern void *pxCurrentTCB;
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81 /*-----------------------------------------------------------*/
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84 * See header file for description.
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86 StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
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88 /* R0 is not included as it is the stack pointer. */
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90 *pxTopOfStack = 0x00;
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92 *pxTopOfStack = portINITIAL_PSW;
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94 *pxTopOfStack = ( StackType_t ) pxCode;
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96 /* When debugging it can be useful if every register is set to a known
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97 value. Otherwise code space can be saved by just setting the registers
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98 that need to be set. */
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99 #ifdef USE_FULL_REGISTER_INITIALISATION
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102 *pxTopOfStack = 0xffffffff; /* r15. */
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104 *pxTopOfStack = 0xeeeeeeee;
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106 *pxTopOfStack = 0xdddddddd;
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108 *pxTopOfStack = 0xcccccccc;
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110 *pxTopOfStack = 0xbbbbbbbb;
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112 *pxTopOfStack = 0xaaaaaaaa;
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114 *pxTopOfStack = 0x99999999;
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116 *pxTopOfStack = 0x88888888;
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118 *pxTopOfStack = 0x77777777;
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120 *pxTopOfStack = 0x66666666;
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122 *pxTopOfStack = 0x55555555;
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124 *pxTopOfStack = 0x44444444;
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126 *pxTopOfStack = 0x33333333;
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128 *pxTopOfStack = 0x22222222;
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133 pxTopOfStack -= 15;
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137 *pxTopOfStack = ( StackType_t ) pvParameters; /* R1 */
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139 *pxTopOfStack = portINITIAL_FPSW;
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141 *pxTopOfStack = 0x11111111; /* Accumulator 0. */
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143 *pxTopOfStack = 0x22222222; /* Accumulator 0. */
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145 *pxTopOfStack = 0x33333333; /* Accumulator 0. */
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147 *pxTopOfStack = 0x44444444; /* Accumulator 1. */
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149 *pxTopOfStack = 0x55555555; /* Accumulator 1. */
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151 *pxTopOfStack = 0x66666666; /* Accumulator 1. */
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153 return pxTopOfStack;
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155 /*-----------------------------------------------------------*/
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157 BaseType_t xPortStartScheduler( void )
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159 extern void vApplicationSetupTimerInterrupt( void );
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161 /* Use pxCurrentTCB just so it does not get optimised away. */
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162 if( pxCurrentTCB != NULL )
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164 /* Call an application function to set up the timer that will generate the
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165 tick interrupt. This way the application can decide which peripheral to
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166 use. A demo application is provided to show a suitable example. */
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167 vApplicationSetupTimerInterrupt();
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169 /* Enable the software interrupt. */
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170 _IEN( _ICU_SWINT ) = 1;
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172 /* Ensure the software interrupt is clear. */
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173 _IR( _ICU_SWINT ) = 0;
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175 /* Ensure the software interrupt is set to the kernel priority. */
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176 _IPR( _ICU_SWINT ) = configKERNEL_INTERRUPT_PRIORITY;
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178 /* Start the first task. */
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179 prvStartFirstTask();
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182 /* Should not get here. */
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185 /*-----------------------------------------------------------*/
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187 void vPortEndScheduler( void )
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189 /* Not implemented in ports where there is nothing to return to.
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190 Artificially force an assert. */
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191 configASSERT( pxCurrentTCB == NULL );
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193 /*-----------------------------------------------------------*/
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195 static void prvStartFirstTask( void )
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199 /* When starting the scheduler there is nothing that needs moving to the
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200 interrupt stack because the function is not called from an interrupt.
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201 Just ensure the current stack is the user stack. */
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204 /* Obtain the location of the stack associated with which ever task
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205 pxCurrentTCB is currently pointing to. */
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206 "MOV.L #_pxCurrentTCB, R15 \n" \
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207 "MOV.L [R15], R15 \n" \
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208 "MOV.L [R15], R0 \n" \
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210 /* Restore the registers from the stack of the task pointed to by
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214 /* Accumulator low 32 bits. */
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215 "MVTACLO R15, A0 \n" \
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218 /* Accumulator high 32 bits. */
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219 "MVTACHI R15, A0 \n" \
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222 /* Accumulator guard. */
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223 "MVTACGU R15, A0 \n" \
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226 /* Accumulator low 32 bits. */
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227 "MVTACLO R15, A1 \n" \
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230 /* Accumulator high 32 bits. */
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231 "MVTACHI R15, A1 \n" \
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234 /* Accumulator guard. */
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235 "MVTACGU R15, A1 \n" \
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238 /* Floating point status word. */
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239 "MVTC R15, FPSW \n" \
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241 /* R1 to R15 - R0 is not included as it is the SP. */
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244 /* This pops the remaining registers. */
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250 /*-----------------------------------------------------------*/
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252 void vSoftwareInterruptISR( void )
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256 /* Re-enable interrupts. */
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259 /* Move the data that was automatically pushed onto the interrupt stack when
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260 the interrupt occurred from the interrupt stack to the user stack.
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262 R15 is saved before it is clobbered. */
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265 /* Read the user stack pointer. */
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266 "MVFC USP, R15 \n" \
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268 /* Move the address down to the data being moved. */
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269 "SUB #12, R15 \n" \
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270 "MVTC R15, USP \n" \
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272 /* Copy the data across, R15, then PC, then PSW. */
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273 "MOV.L [ R0 ], [ R15 ] \n" \
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274 "MOV.L 4[ R0 ], 4[ R15 ] \n" \
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275 "MOV.L 8[ R0 ], 8[ R15 ] \n" \
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277 /* Move the interrupt stack pointer to its new correct position. */
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280 /* All the rest of the registers are saved directly to the user stack. */
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283 /* Save the rest of the general registers (R15 has been saved already). */
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284 "PUSHM R1-R14 \n" \
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286 /* Save the FPSW and accumulator. */
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287 "MVFC FPSW, R15 \n" \
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289 "MVFACGU #0, A1, R15 \n" \
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291 "MVFACHI #0, A1, R15 \n" \
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293 /* Low order word. */
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294 "MVFACLO #0, A1, R15 \n" \
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296 "MVFACGU #0, A0, R15 \n" \
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298 "MVFACHI #0, A0, R15 \n" \
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300 /* Low order word. */
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301 "MVFACLO #0, A0, R15 \n" \
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304 /* Save the stack pointer to the TCB. */
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305 "MOV.L #_pxCurrentTCB, R15 \n" \
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306 "MOV.L [ R15 ], R15 \n" \
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307 "MOV.L R0, [ R15 ] \n" \
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309 /* Ensure the interrupt mask is set to the syscall priority while the kernel
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310 structures are being accessed. */
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313 /* Select the next task to run. */
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314 "BSR.A _vTaskSwitchContext \n" \
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316 /* Reset the interrupt mask as no more data structure access is required. */
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319 /* Load the stack pointer of the task that is now selected as the Running
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320 state task from its TCB. */
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321 "MOV.L #_pxCurrentTCB,R15 \n" \
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322 "MOV.L [ R15 ], R15 \n" \
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323 "MOV.L [ R15 ], R0 \n" \
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325 /* Restore the context of the new task. The PSW (Program Status Word) and
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326 PC will be popped by the RTE instruction. */
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329 /* Accumulator low 32 bits. */
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330 "MVTACLO R15, A0 \n" \
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333 /* Accumulator high 32 bits. */
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334 "MVTACHI R15, A0 \n" \
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337 /* Accumulator guard. */
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338 "MVTACGU R15, A0 \n" \
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341 /* Accumulator low 32 bits. */
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342 "MVTACLO R15, A1 \n" \
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345 /* Accumulator high 32 bits. */
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346 "MVTACHI R15, A1 \n" \
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349 /* Accumulator guard. */
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350 "MVTACGU R15, A1 \n" \
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352 "MVTC R15, FPSW \n" \
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357 :: "i"(configMAX_SYSCALL_INTERRUPT_PRIORITY), "i"(configKERNEL_INTERRUPT_PRIORITY)
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360 /*-----------------------------------------------------------*/
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362 void vTickISR( void )
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364 /* Re-enabled interrupts. */
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365 __asm volatile( "SETPSW I" );
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367 /* Increment the tick, and perform any processing the new tick value
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368 necessitates. Ensure IPL is at the max syscall value first. */
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369 portMASK_INTERRUPTS_FROM_KERNEL_ISR();
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371 if( xTaskIncrementTick() != pdFALSE )
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376 portUNMASK_INTERRUPTS_FROM_KERNEL_ISR();
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378 /*-----------------------------------------------------------*/
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380 uint32_t ulPortGetIPL( void )
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384 "MVFC PSW, R1 \n" \
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385 "SHLR #24, R1 \n" \
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389 /* This will never get executed, but keeps the compiler from complaining. */
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392 /*-----------------------------------------------------------*/
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394 void vPortSetIPL( uint32_t ulNewIPL )
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399 "MVFC PSW, R5 \n" \
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400 "SHLL #24, R1 \n" \
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401 "AND #-0F000001H, R5 \n" \
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403 "MVTC R5, PSW \n" \
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projects / freertos / blob