git.sur5r.net Git - freertos/blob - FreeRTOS/Source/portable/GCC/STR75x/portISR.c

   1 /*\r
   2  * FreeRTOS Kernel V10.1.1\r
   3  * Copyright (C) 2018 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\r
   4  *\r
   5  * Permission is hereby granted, free of charge, to any person obtaining a copy of\r
   6  * this software and associated documentation files (the "Software"), to deal in\r
   7  * the Software without restriction, including without limitation the rights to\r
   8  * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\r
   9  * the Software, and to permit persons to whom the Software is furnished to do so,\r
  10  * subject to the following conditions:\r
  11  *\r
  12  * The above copyright notice and this permission notice shall be included in all\r
  13  * copies or substantial portions of the Software.\r
  14  *\r
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\r
  17  * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\r
  18  * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r
  19  * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
  20  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
  21  *\r
  22  * http://www.FreeRTOS.org\r
  23  * http://aws.amazon.com/freertos\r
  24  *\r
  25  * 1 tab == 4 spaces!\r
  26  */\r
  27 \r
  28 \r
  29 /*-----------------------------------------------------------\r
  30  * Components that can be compiled to either ARM or THUMB mode are\r
  31  * contained in port.c  The ISR routines, which can only be compiled\r
  32  * to ARM mode, are contained in this file.\r
  33  *----------------------------------------------------------*/\r
  34 \r
  35 /*\r
  36 */\r
  37 \r
  38 /* Scheduler includes. */\r
  39 #include "FreeRTOS.h"\r
  40 #include "task.h"\r
  41 \r
  42 /* Constants required to handle critical sections. */\r
  43 #define portNO_CRITICAL_NESTING         ( ( uint32_t ) 0 )\r
  44 \r
  45 volatile uint32_t ulCriticalNesting = 9999UL;\r
  46 \r
  47 /*-----------------------------------------------------------*/\r
  48 \r
  49 /* \r
  50  * The scheduler can only be started from ARM mode, hence the inclusion of this\r
  51  * function here.\r
  52  */\r
  53 void vPortISRStartFirstTask( void );\r
  54 /*-----------------------------------------------------------*/\r
  55 \r
  56 void vPortISRStartFirstTask( void )\r
  57 {\r
  58         /* Simply start the scheduler.  This is included here as it can only be\r
  59         called from ARM mode. */\r
  60         asm volatile (                                                                                                          \\r
  61         "LDR            R0, =pxCurrentTCB                                                               \n\t"   \\r
  62         "LDR            R0, [R0]                                                                                \n\t"   \\r
  63         "LDR            LR, [R0]                                                                                \n\t"   \\r
  64                                                                                                                                                 \\r
  65         /* The critical nesting depth is the first item on the stack. */        \\r
  66         /* Load it into the ulCriticalNesting variable. */                                      \\r
  67         "LDR            R0, =ulCriticalNesting                                                  \n\t"   \\r
  68         "LDMFD  LR!, {R1}                                                                                       \n\t"   \\r
  69         "STR            R1, [R0]                                                                                \n\t"   \\r
  70                                                                                                                                                 \\r
  71         /* Get the SPSR from the stack. */                                                                      \\r
  72         "LDMFD  LR!, {R0}                                                                                       \n\t"   \\r
  73         "MSR            SPSR, R0                                                                                \n\t"   \\r
  74                                                                                                                                                 \\r
  75         /* Restore all system mode registers for the task. */                           \\r
  76         "LDMFD  LR, {R0-R14}^                                                                           \n\t"   \\r
  77         "NOP                                                                                                            \n\t"   \\r
  78                                                                                                                                                 \\r
  79         /* Restore the return address. */                                                                       \\r
  80         "LDR            LR, [LR, #+60]                                                                  \n\t"   \\r
  81                                                                                                                                                 \\r
  82         /* And return - correcting the offset in the LR to obtain the */        \\r
  83         /* correct address. */                                                                                          \\r
  84         "SUBS PC, LR, #4                                                                                        \n\t"   \\r
  85         );                                                                                                                                      \r
  86 }\r
  87 /*-----------------------------------------------------------*/\r
  88 \r
  89 void vPortTickISR( void )\r
  90 {\r
  91         /* Increment the RTOS tick count, then look for the highest priority \r
  92         task that is ready to run. */\r
  93         if( xTaskIncrementTick() != pdFALSE )\r
  94         {       \r
  95                 vTaskSwitchContext();\r
  96         }\r
  97                         \r
  98         /* Ready for the next interrupt. */\r
  99         TB_ClearITPendingBit( TB_IT_Update );   \r
 100 }\r
 101 \r
 102 /*-----------------------------------------------------------*/\r
 103 \r
 104 /*\r
 105  * The interrupt management utilities can only be called from ARM mode.  When\r
 106  * THUMB_INTERWORK is defined the utilities are defined as functions here to\r
 107  * ensure a switch to ARM mode.  When THUMB_INTERWORK is not defined then\r
 108  * the utilities are defined as macros in portmacro.h - as per other ports.\r
 109  */\r
 110 #ifdef THUMB_INTERWORK\r
 111 \r
 112         void vPortDisableInterruptsFromThumb( void ) __attribute__ ((naked));\r
 113         void vPortEnableInterruptsFromThumb( void ) __attribute__ ((naked));\r
 114 \r
 115         void vPortDisableInterruptsFromThumb( void )\r
 116         {\r
 117                 asm volatile ( \r
 118                         "STMDB  SP!, {R0}               \n\t"   /* Push R0.                                                                     */\r
 119                         "MRS    R0, CPSR                \n\t"   /* Get CPSR.                                                            */\r
 120                         "ORR    R0, R0, #0xC0   \n\t"   /* Disable IRQ, FIQ.                                            */\r
 121                         "MSR    CPSR, R0                \n\t"   /* Write back modified value.                           */\r
 122                         "LDMIA  SP!, {R0}               \n\t"   /* Pop R0.                                                                      */\r
 123                         "BX             R14" );                                 /* Return back to thumb.                                        */\r
 124         }\r
 125                         \r
 126         void vPortEnableInterruptsFromThumb( void )\r
 127         {\r
 128                 asm volatile ( \r
 129                         "STMDB  SP!, {R0}               \n\t"   /* Push R0.                                                                     */      \r
 130                         "MRS    R0, CPSR                \n\t"   /* Get CPSR.                                                            */      \r
 131                         "BIC    R0, R0, #0xC0   \n\t"   /* Enable IRQ, FIQ.                                                     */      \r
 132                         "MSR    CPSR, R0                \n\t"   /* Write back modified value.                           */      \r
 133                         "LDMIA  SP!, {R0}               \n\t"   /* Pop R0.                                                                      */\r
 134                         "BX             R14" );                                 /* Return back to thumb.                                        */\r
 135         }\r
 136 \r
 137 #endif /* THUMB_INTERWORK */\r
 138 /*-----------------------------------------------------------*/\r
 139 \r
 140 void vPortEnterCritical( void )\r
 141 {\r
 142         /* Disable interrupts as per portDISABLE_INTERRUPTS();                                                  */\r
 143         asm volatile ( \r
 144                 "STMDB  SP!, {R0}                       \n\t"   /* Push R0.                                                             */\r
 145                 "MRS    R0, CPSR                        \n\t"   /* Get CPSR.                                                    */\r
 146                 "ORR    R0, R0, #0xC0           \n\t"   /* Disable IRQ, FIQ.                                    */\r
 147                 "MSR    CPSR, R0                        \n\t"   /* Write back modified value.                   */\r
 148                 "LDMIA  SP!, {R0}" );                           /* Pop R0.                                                              */\r
 149 \r
 150         /* Now interrupts are disabled ulCriticalNesting can be accessed \r
 151         directly.  Increment ulCriticalNesting to keep a count of how many times\r
 152         portENTER_CRITICAL() has been called. */\r
 153         ulCriticalNesting++;\r
 154 }\r
 155 /*-----------------------------------------------------------*/\r
 156 \r
 157 void vPortExitCritical( void )\r
 158 {\r
 159         if( ulCriticalNesting > portNO_CRITICAL_NESTING )\r
 160         {\r
 161                 /* Decrement the nesting count as we are leaving a critical section. */\r
 162                 ulCriticalNesting--;\r
 163 \r
 164                 /* If the nesting level has reached zero then interrupts should be\r
 165                 re-enabled. */\r
 166                 if( ulCriticalNesting == portNO_CRITICAL_NESTING )\r
 167                 {\r
 168                         /* Enable interrupts as per portEXIT_CRITICAL().                                        */\r
 169                         asm volatile ( \r
 170                                 "STMDB  SP!, {R0}               \n\t"   /* Push R0.                                             */      \r
 171                                 "MRS    R0, CPSR                \n\t"   /* Get CPSR.                                    */      \r
 172                                 "BIC    R0, R0, #0xC0   \n\t"   /* Enable IRQ, FIQ.                             */      \r
 173                                 "MSR    CPSR, R0                \n\t"   /* Write back modified value.   */      \r
 174                                 "LDMIA  SP!, {R0}" );                   /* Pop R0.                                              */\r
 175                 }\r
 176         }\r
 177 }\r
 178 \r
 179 \r
 180 \r
 181 \r
 182 \r