git.sur5r.net Git - freertos/blob - FreeRTOS/Source/portable/GCC/STR75x/portISR.c

   1 /*\r
   2     FreeRTOS V8.0.1 - Copyright (C) 2014 Real Time Engineers Ltd. \r
   3     All rights reserved\r
   4 \r
   5     VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
   6 \r
   7     ***************************************************************************\r
   8      *                                                                       *\r
   9      *    FreeRTOS provides completely free yet professionally developed,    *\r
  10      *    robust, strictly quality controlled, supported, and cross          *\r
  11      *    platform software that has become a de facto standard.             *\r
  12      *                                                                       *\r
  13      *    Help yourself get started quickly and support the FreeRTOS         *\r
  14      *    project by purchasing a FreeRTOS tutorial book, reference          *\r
  15      *    manual, or both from: http://www.FreeRTOS.org/Documentation        *\r
  16      *                                                                       *\r
  17      *    Thank you!                                                         *\r
  18      *                                                                       *\r
  19     ***************************************************************************\r
  20 \r
  21     This file is part of the FreeRTOS distribution.\r
  22 \r
  23     FreeRTOS is free software; you can redistribute it and/or modify it under\r
  24     the terms of the GNU General Public License (version 2) as published by the\r
  25     Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.\r
  26 \r
  27     >>!   NOTE: The modification to the GPL is included to allow you to     !<<\r
  28     >>!   distribute a combined work that includes FreeRTOS without being   !<<\r
  29     >>!   obliged to provide the source code for proprietary components     !<<\r
  30     >>!   outside of the FreeRTOS kernel.                                   !<<\r
  31 \r
  32     FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
  33     WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
  34     FOR A PARTICULAR PURPOSE.  Full license text is available from the following\r
  35     link: http://www.freertos.org/a00114.html\r
  36 \r
  37     1 tab == 4 spaces!\r
  38 \r
  39     ***************************************************************************\r
  40      *                                                                       *\r
  41      *    Having a problem?  Start by reading the FAQ "My application does   *\r
  42      *    not run, what could be wrong?"                                     *\r
  43      *                                                                       *\r
  44      *    http://www.FreeRTOS.org/FAQHelp.html                               *\r
  45      *                                                                       *\r
  46     ***************************************************************************\r
  47 \r
  48     http://www.FreeRTOS.org - Documentation, books, training, latest versions,\r
  49     license and Real Time Engineers Ltd. contact details.\r
  50 \r
  51     http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
  52     including FreeRTOS+Trace - an indispensable productivity tool, a DOS\r
  53     compatible FAT file system, and our tiny thread aware UDP/IP stack.\r
  54 \r
  55     http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High\r
  56     Integrity Systems to sell under the OpenRTOS brand.  Low cost OpenRTOS\r
  57     licenses offer ticketed support, indemnification and middleware.\r
  58 \r
  59     http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
  60     engineered and independently SIL3 certified version for use in safety and\r
  61     mission critical applications that require provable dependability.\r
  62 \r
  63     1 tab == 4 spaces!\r
  64 */\r
  65 \r
  66 \r
  67 /*-----------------------------------------------------------\r
  68  * Components that can be compiled to either ARM or THUMB mode are\r
  69  * contained in port.c  The ISR routines, which can only be compiled\r
  70  * to ARM mode, are contained in this file.\r
  71  *----------------------------------------------------------*/\r
  72 \r
  73 /*\r
  74 */\r
  75 \r
  76 /* Scheduler includes. */\r
  77 #include "FreeRTOS.h"\r
  78 #include "task.h"\r
  79 \r
  80 /* Constants required to handle critical sections. */\r
  81 #define portNO_CRITICAL_NESTING         ( ( uint32_t ) 0 )\r
  82 \r
  83 volatile uint32_t ulCriticalNesting = 9999UL;\r
  84 \r
  85 /*-----------------------------------------------------------*/\r
  86 \r
  87 /* \r
  88  * The scheduler can only be started from ARM mode, hence the inclusion of this\r
  89  * function here.\r
  90  */\r
  91 void vPortISRStartFirstTask( void );\r
  92 /*-----------------------------------------------------------*/\r
  93 \r
  94 void vPortISRStartFirstTask( void )\r
  95 {\r
  96         /* Simply start the scheduler.  This is included here as it can only be\r
  97         called from ARM mode. */\r
  98         asm volatile (                                                                                                          \\r
  99         "LDR            R0, =pxCurrentTCB                                                               \n\t"   \\r
 100         "LDR            R0, [R0]                                                                                \n\t"   \\r
 101         "LDR            LR, [R0]                                                                                \n\t"   \\r
 102                                                                                                                                                 \\r
 103         /* The critical nesting depth is the first item on the stack. */        \\r
 104         /* Load it into the ulCriticalNesting variable. */                                      \\r
 105         "LDR            R0, =ulCriticalNesting                                                  \n\t"   \\r
 106         "LDMFD  LR!, {R1}                                                                                       \n\t"   \\r
 107         "STR            R1, [R0]                                                                                \n\t"   \\r
 108                                                                                                                                                 \\r
 109         /* Get the SPSR from the stack. */                                                                      \\r
 110         "LDMFD  LR!, {R0}                                                                                       \n\t"   \\r
 111         "MSR            SPSR, R0                                                                                \n\t"   \\r
 112                                                                                                                                                 \\r
 113         /* Restore all system mode registers for the task. */                           \\r
 114         "LDMFD  LR, {R0-R14}^                                                                           \n\t"   \\r
 115         "NOP                                                                                                            \n\t"   \\r
 116                                                                                                                                                 \\r
 117         /* Restore the return address. */                                                                       \\r
 118         "LDR            LR, [LR, #+60]                                                                  \n\t"   \\r
 119                                                                                                                                                 \\r
 120         /* And return - correcting the offset in the LR to obtain the */        \\r
 121         /* correct address. */                                                                                          \\r
 122         "SUBS PC, LR, #4                                                                                        \n\t"   \\r
 123         );                                                                                                                                      \r
 124 }\r
 125 /*-----------------------------------------------------------*/\r
 126 \r
 127 void vPortTickISR( void )\r
 128 {\r
 129         /* Increment the RTOS tick count, then look for the highest priority \r
 130         task that is ready to run. */\r
 131         if( xTaskIncrementTick() != pdFALSE )\r
 132         {       \r
 133                 vTaskSwitchContext();\r
 134         }\r
 135                         \r
 136         /* Ready for the next interrupt. */\r
 137         TB_ClearITPendingBit( TB_IT_Update );   \r
 138 }\r
 139 \r
 140 /*-----------------------------------------------------------*/\r
 141 \r
 142 /*\r
 143  * The interrupt management utilities can only be called from ARM mode.  When\r
 144  * THUMB_INTERWORK is defined the utilities are defined as functions here to\r
 145  * ensure a switch to ARM mode.  When THUMB_INTERWORK is not defined then\r
 146  * the utilities are defined as macros in portmacro.h - as per other ports.\r
 147  */\r
 148 #ifdef THUMB_INTERWORK\r
 149 \r
 150         void vPortDisableInterruptsFromThumb( void ) __attribute__ ((naked));\r
 151         void vPortEnableInterruptsFromThumb( void ) __attribute__ ((naked));\r
 152 \r
 153         void vPortDisableInterruptsFromThumb( void )\r
 154         {\r
 155                 asm volatile ( \r
 156                         "STMDB  SP!, {R0}               \n\t"   /* Push R0.                                                                     */\r
 157                         "MRS    R0, CPSR                \n\t"   /* Get CPSR.                                                            */\r
 158                         "ORR    R0, R0, #0xC0   \n\t"   /* Disable IRQ, FIQ.                                            */\r
 159                         "MSR    CPSR, R0                \n\t"   /* Write back modified value.                           */\r
 160                         "LDMIA  SP!, {R0}               \n\t"   /* Pop R0.                                                                      */\r
 161                         "BX             R14" );                                 /* Return back to thumb.                                        */\r
 162         }\r
 163                         \r
 164         void vPortEnableInterruptsFromThumb( void )\r
 165         {\r
 166                 asm volatile ( \r
 167                         "STMDB  SP!, {R0}               \n\t"   /* Push R0.                                                                     */      \r
 168                         "MRS    R0, CPSR                \n\t"   /* Get CPSR.                                                            */      \r
 169                         "BIC    R0, R0, #0xC0   \n\t"   /* Enable IRQ, FIQ.                                                     */      \r
 170                         "MSR    CPSR, R0                \n\t"   /* Write back modified value.                           */      \r
 171                         "LDMIA  SP!, {R0}               \n\t"   /* Pop R0.                                                                      */\r
 172                         "BX             R14" );                                 /* Return back to thumb.                                        */\r
 173         }\r
 174 \r
 175 #endif /* THUMB_INTERWORK */\r
 176 /*-----------------------------------------------------------*/\r
 177 \r
 178 void vPortEnterCritical( void )\r
 179 {\r
 180         /* Disable interrupts as per portDISABLE_INTERRUPTS();                                                  */\r
 181         asm volatile ( \r
 182                 "STMDB  SP!, {R0}                       \n\t"   /* Push R0.                                                             */\r
 183                 "MRS    R0, CPSR                        \n\t"   /* Get CPSR.                                                    */\r
 184                 "ORR    R0, R0, #0xC0           \n\t"   /* Disable IRQ, FIQ.                                    */\r
 185                 "MSR    CPSR, R0                        \n\t"   /* Write back modified value.                   */\r
 186                 "LDMIA  SP!, {R0}" );                           /* Pop R0.                                                              */\r
 187 \r
 188         /* Now interrupts are disabled ulCriticalNesting can be accessed \r
 189         directly.  Increment ulCriticalNesting to keep a count of how many times\r
 190         portENTER_CRITICAL() has been called. */\r
 191         ulCriticalNesting++;\r
 192 }\r
 193 /*-----------------------------------------------------------*/\r
 194 \r
 195 void vPortExitCritical( void )\r
 196 {\r
 197         if( ulCriticalNesting > portNO_CRITICAL_NESTING )\r
 198         {\r
 199                 /* Decrement the nesting count as we are leaving a critical section. */\r
 200                 ulCriticalNesting--;\r
 201 \r
 202                 /* If the nesting level has reached zero then interrupts should be\r
 203                 re-enabled. */\r
 204                 if( ulCriticalNesting == portNO_CRITICAL_NESTING )\r
 205                 {\r
 206                         /* Enable interrupts as per portEXIT_CRITICAL().                                        */\r
 207                         asm volatile ( \r
 208                                 "STMDB  SP!, {R0}               \n\t"   /* Push R0.                                             */      \r
 209                                 "MRS    R0, CPSR                \n\t"   /* Get CPSR.                                    */      \r
 210                                 "BIC    R0, R0, #0xC0   \n\t"   /* Enable IRQ, FIQ.                             */      \r
 211                                 "MSR    CPSR, R0                \n\t"   /* Write back modified value.   */      \r
 212                                 "LDMIA  SP!, {R0}" );                   /* Pop R0.                                              */\r
 213                 }\r
 214         }\r
 215 }\r
 216 \r
 217 \r
 218 \r
 219 \r
 220 \r