git.sur5r.net Git - freertos/blob - FreeRTOS/Source/portable/GCC/STR75x/portISR.c

   1 /*\r
   2     FreeRTOS V7.5.1 - Copyright (C) 2013 Real Time Engineers Ltd.\r
   3 \r
   4     VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
   5 \r
   6     ***************************************************************************\r
   7      *                                                                       *\r
   8      *    FreeRTOS provides completely free yet professionally developed,    *\r
   9      *    robust, strictly quality controlled, supported, and cross          *\r
  10      *    platform software that has become a de facto standard.             *\r
  11      *                                                                       *\r
  12      *    Help yourself get started quickly and support the FreeRTOS         *\r
  13      *    project by purchasing a FreeRTOS tutorial book, reference          *\r
  14      *    manual, or both from: http://www.FreeRTOS.org/Documentation        *\r
  15      *                                                                       *\r
  16      *    Thank you!                                                         *\r
  17      *                                                                       *\r
  18     ***************************************************************************\r
  19 \r
  20     This file is part of the FreeRTOS distribution.\r
  21 \r
  22     FreeRTOS is free software; you can redistribute it and/or modify it under\r
  23     the terms of the GNU General Public License (version 2) as published by the\r
  24     Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.\r
  25 \r
  26     >>! NOTE: The modification to the GPL is included to allow you to distribute\r
  27     >>! a combined work that includes FreeRTOS without being obliged to provide\r
  28     >>! the source code for proprietary components outside of the FreeRTOS\r
  29     >>! kernel.\r
  30 \r
  31     FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
  32     WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
  33     FOR A PARTICULAR PURPOSE.  Full license text is available from the following\r
  34     link: http://www.freertos.org/a00114.html\r
  35 \r
  36     1 tab == 4 spaces!\r
  37 \r
  38     ***************************************************************************\r
  39      *                                                                       *\r
  40      *    Having a problem?  Start by reading the FAQ "My application does   *\r
  41      *    not run, what could be wrong?"                                     *\r
  42      *                                                                       *\r
  43      *    http://www.FreeRTOS.org/FAQHelp.html                               *\r
  44      *                                                                       *\r
  45     ***************************************************************************\r
  46 \r
  47     http://www.FreeRTOS.org - Documentation, books, training, latest versions,\r
  48     license and Real Time Engineers Ltd. contact details.\r
  49 \r
  50     http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
  51     including FreeRTOS+Trace - an indispensable productivity tool, a DOS\r
  52     compatible FAT file system, and our tiny thread aware UDP/IP stack.\r
  53 \r
  54     http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High\r
  55     Integrity Systems to sell under the OpenRTOS brand.  Low cost OpenRTOS\r
  56     licenses offer ticketed support, indemnification and middleware.\r
  57 \r
  58     http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
  59     engineered and independently SIL3 certified version for use in safety and\r
  60     mission critical applications that require provable dependability.\r
  61 \r
  62     1 tab == 4 spaces!\r
  63 */\r
  64 \r
  65 \r
  66 /*-----------------------------------------------------------\r
  67  * Components that can be compiled to either ARM or THUMB mode are\r
  68  * contained in port.c  The ISR routines, which can only be compiled\r
  69  * to ARM mode, are contained in this file.\r
  70  *----------------------------------------------------------*/\r
  71 \r
  72 /*\r
  73 */\r
  74 \r
  75 /* Scheduler includes. */\r
  76 #include "FreeRTOS.h"\r
  77 #include "task.h"\r
  78 \r
  79 /* Constants required to handle critical sections. */\r
  80 #define portNO_CRITICAL_NESTING         ( ( unsigned long ) 0 )\r
  81 \r
  82 volatile unsigned long ulCriticalNesting = 9999UL;\r
  83 \r
  84 /*-----------------------------------------------------------*/\r
  85 \r
  86 /* \r
  87  * The scheduler can only be started from ARM mode, hence the inclusion of this\r
  88  * function here.\r
  89  */\r
  90 void vPortISRStartFirstTask( void );\r
  91 /*-----------------------------------------------------------*/\r
  92 \r
  93 void vPortISRStartFirstTask( void )\r
  94 {\r
  95         /* Simply start the scheduler.  This is included here as it can only be\r
  96         called from ARM mode. */\r
  97         asm volatile (                                                                                                          \\r
  98         "LDR            R0, =pxCurrentTCB                                                               \n\t"   \\r
  99         "LDR            R0, [R0]                                                                                \n\t"   \\r
 100         "LDR            LR, [R0]                                                                                \n\t"   \\r
 101                                                                                                                                                 \\r
 102         /* The critical nesting depth is the first item on the stack. */        \\r
 103         /* Load it into the ulCriticalNesting variable. */                                      \\r
 104         "LDR            R0, =ulCriticalNesting                                                  \n\t"   \\r
 105         "LDMFD  LR!, {R1}                                                                                       \n\t"   \\r
 106         "STR            R1, [R0]                                                                                \n\t"   \\r
 107                                                                                                                                                 \\r
 108         /* Get the SPSR from the stack. */                                                                      \\r
 109         "LDMFD  LR!, {R0}                                                                                       \n\t"   \\r
 110         "MSR            SPSR, R0                                                                                \n\t"   \\r
 111                                                                                                                                                 \\r
 112         /* Restore all system mode registers for the task. */                           \\r
 113         "LDMFD  LR, {R0-R14}^                                                                           \n\t"   \\r
 114         "NOP                                                                                                            \n\t"   \\r
 115                                                                                                                                                 \\r
 116         /* Restore the return address. */                                                                       \\r
 117         "LDR            LR, [LR, #+60]                                                                  \n\t"   \\r
 118                                                                                                                                                 \\r
 119         /* And return - correcting the offset in the LR to obtain the */        \\r
 120         /* correct address. */                                                                                          \\r
 121         "SUBS PC, LR, #4                                                                                        \n\t"   \\r
 122         );                                                                                                                                      \r
 123 }\r
 124 /*-----------------------------------------------------------*/\r
 125 \r
 126 void vPortTickISR( void )\r
 127 {\r
 128         /* Increment the RTOS tick count, then look for the highest priority \r
 129         task that is ready to run. */\r
 130         if( xTaskIncrementTick() != pdFALSE )\r
 131         {       \r
 132                 vTaskSwitchContext();\r
 133         }\r
 134                         \r
 135         /* Ready for the next interrupt. */\r
 136         TB_ClearITPendingBit( TB_IT_Update );   \r
 137 }\r
 138 \r
 139 /*-----------------------------------------------------------*/\r
 140 \r
 141 /*\r
 142  * The interrupt management utilities can only be called from ARM mode.  When\r
 143  * THUMB_INTERWORK is defined the utilities are defined as functions here to\r
 144  * ensure a switch to ARM mode.  When THUMB_INTERWORK is not defined then\r
 145  * the utilities are defined as macros in portmacro.h - as per other ports.\r
 146  */\r
 147 #ifdef THUMB_INTERWORK\r
 148 \r
 149         void vPortDisableInterruptsFromThumb( void ) __attribute__ ((naked));\r
 150         void vPortEnableInterruptsFromThumb( void ) __attribute__ ((naked));\r
 151 \r
 152         void vPortDisableInterruptsFromThumb( void )\r
 153         {\r
 154                 asm volatile ( \r
 155                         "STMDB  SP!, {R0}               \n\t"   /* Push R0.                                                                     */\r
 156                         "MRS    R0, CPSR                \n\t"   /* Get CPSR.                                                            */\r
 157                         "ORR    R0, R0, #0xC0   \n\t"   /* Disable IRQ, FIQ.                                            */\r
 158                         "MSR    CPSR, R0                \n\t"   /* Write back modified value.                           */\r
 159                         "LDMIA  SP!, {R0}               \n\t"   /* Pop R0.                                                                      */\r
 160                         "BX             R14" );                                 /* Return back to thumb.                                        */\r
 161         }\r
 162                         \r
 163         void vPortEnableInterruptsFromThumb( void )\r
 164         {\r
 165                 asm volatile ( \r
 166                         "STMDB  SP!, {R0}               \n\t"   /* Push R0.                                                                     */      \r
 167                         "MRS    R0, CPSR                \n\t"   /* Get CPSR.                                                            */      \r
 168                         "BIC    R0, R0, #0xC0   \n\t"   /* Enable IRQ, FIQ.                                                     */      \r
 169                         "MSR    CPSR, R0                \n\t"   /* Write back modified value.                           */      \r
 170                         "LDMIA  SP!, {R0}               \n\t"   /* Pop R0.                                                                      */\r
 171                         "BX             R14" );                                 /* Return back to thumb.                                        */\r
 172         }\r
 173 \r
 174 #endif /* THUMB_INTERWORK */\r
 175 /*-----------------------------------------------------------*/\r
 176 \r
 177 void vPortEnterCritical( void )\r
 178 {\r
 179         /* Disable interrupts as per portDISABLE_INTERRUPTS();                                                  */\r
 180         asm volatile ( \r
 181                 "STMDB  SP!, {R0}                       \n\t"   /* Push R0.                                                             */\r
 182                 "MRS    R0, CPSR                        \n\t"   /* Get CPSR.                                                    */\r
 183                 "ORR    R0, R0, #0xC0           \n\t"   /* Disable IRQ, FIQ.                                    */\r
 184                 "MSR    CPSR, R0                        \n\t"   /* Write back modified value.                   */\r
 185                 "LDMIA  SP!, {R0}" );                           /* Pop R0.                                                              */\r
 186 \r
 187         /* Now interrupts are disabled ulCriticalNesting can be accessed \r
 188         directly.  Increment ulCriticalNesting to keep a count of how many times\r
 189         portENTER_CRITICAL() has been called. */\r
 190         ulCriticalNesting++;\r
 191 }\r
 192 /*-----------------------------------------------------------*/\r
 193 \r
 194 void vPortExitCritical( void )\r
 195 {\r
 196         if( ulCriticalNesting > portNO_CRITICAL_NESTING )\r
 197         {\r
 198                 /* Decrement the nesting count as we are leaving a critical section. */\r
 199                 ulCriticalNesting--;\r
 200 \r
 201                 /* If the nesting level has reached zero then interrupts should be\r
 202                 re-enabled. */\r
 203                 if( ulCriticalNesting == portNO_CRITICAL_NESTING )\r
 204                 {\r
 205                         /* Enable interrupts as per portEXIT_CRITICAL().                                        */\r
 206                         asm volatile ( \r
 207                                 "STMDB  SP!, {R0}               \n\t"   /* Push R0.                                             */      \r
 208                                 "MRS    R0, CPSR                \n\t"   /* Get CPSR.                                    */      \r
 209                                 "BIC    R0, R0, #0xC0   \n\t"   /* Enable IRQ, FIQ.                             */      \r
 210                                 "MSR    CPSR, R0                \n\t"   /* Write back modified value.   */      \r
 211                                 "LDMIA  SP!, {R0}" );                   /* Pop R0.                                              */\r
 212                 }\r
 213         }\r
 214 }\r
 215 \r
 216 \r
 217 \r
 218 \r
 219 \r