git.sur5r.net Git - freertos/blob - FreeRTOS/Source/portable/GCC/STR75x/portISR.c

   1 /*\r
   2     FreeRTOS V8.2.1 - Copyright (C) 2015 Real Time Engineers Ltd.\r
   3     All rights reserved\r
   4 \r
   5     VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
   6 \r
   7     This file is part of the FreeRTOS distribution.\r
   8 \r
   9     FreeRTOS is free software; you can redistribute it and/or modify it under\r
  10     the terms of the GNU General Public License (version 2) as published by the\r
  11     Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.\r
  12 \r
  13     ***************************************************************************\r
  14     >>!   NOTE: The modification to the GPL is included to allow you to     !<<\r
  15     >>!   distribute a combined work that includes FreeRTOS without being   !<<\r
  16     >>!   obliged to provide the source code for proprietary components     !<<\r
  17     >>!   outside of the FreeRTOS kernel.                                   !<<\r
  18     ***************************************************************************\r
  19 \r
  20     FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
  21     WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
  22     FOR A PARTICULAR PURPOSE.  Full license text is available on the following\r
  23     link: http://www.freertos.org/a00114.html\r
  24 \r
  25     ***************************************************************************\r
  26      *                                                                       *\r
  27      *    FreeRTOS provides completely free yet professionally developed,    *\r
  28      *    robust, strictly quality controlled, supported, and cross          *\r
  29      *    platform software that is more than just the market leader, it     *\r
  30      *    is the industry's de facto standard.                               *\r
  31      *                                                                       *\r
  32      *    Help yourself get started quickly while simultaneously helping     *\r
  33      *    to support the FreeRTOS project by purchasing a FreeRTOS           *\r
  34      *    tutorial book, reference manual, or both:                          *\r
  35      *    http://www.FreeRTOS.org/Documentation                              *\r
  36      *                                                                       *\r
  37     ***************************************************************************\r
  38 \r
  39     http://www.FreeRTOS.org/FAQHelp.html - Having a problem?  Start by reading\r
  40     the FAQ page "My application does not run, what could be wrong?".  Have you\r
  41     defined configASSERT()?\r
  42 \r
  43     http://www.FreeRTOS.org/support - In return for receiving this top quality\r
  44     embedded software for free we request you assist our global community by\r
  45     participating in the support forum.\r
  46 \r
  47     http://www.FreeRTOS.org/training - Investing in training allows your team to\r
  48     be as productive as possible as early as possible.  Now you can receive\r
  49     FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers\r
  50     Ltd, and the world's leading authority on the world's leading RTOS.\r
  51 \r
  52     http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
  53     including FreeRTOS+Trace - an indispensable productivity tool, a DOS\r
  54     compatible FAT file system, and our tiny thread aware UDP/IP stack.\r
  55 \r
  56     http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.\r
  57     Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.\r
  58 \r
  59     http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High\r
  60     Integrity Systems ltd. to sell under the OpenRTOS brand.  Low cost OpenRTOS\r
  61     licenses offer ticketed support, indemnification and commercial middleware.\r
  62 \r
  63     http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
  64     engineered and independently SIL3 certified version for use in safety and\r
  65     mission critical applications that require provable dependability.\r
  66 \r
  67     1 tab == 4 spaces!\r
  68 */\r
  69 \r
  70 \r
  71 /*-----------------------------------------------------------\r
  72  * Components that can be compiled to either ARM or THUMB mode are\r
  73  * contained in port.c  The ISR routines, which can only be compiled\r
  74  * to ARM mode, are contained in this file.\r
  75  *----------------------------------------------------------*/\r
  76 \r
  77 /*\r
  78 */\r
  79 \r
  80 /* Scheduler includes. */\r
  81 #include "FreeRTOS.h"\r
  82 #include "task.h"\r
  83 \r
  84 /* Constants required to handle critical sections. */\r
  85 #define portNO_CRITICAL_NESTING         ( ( uint32_t ) 0 )\r
  86 \r
  87 volatile uint32_t ulCriticalNesting = 9999UL;\r
  88 \r
  89 /*-----------------------------------------------------------*/\r
  90 \r
  91 /* \r
  92  * The scheduler can only be started from ARM mode, hence the inclusion of this\r
  93  * function here.\r
  94  */\r
  95 void vPortISRStartFirstTask( void );\r
  96 /*-----------------------------------------------------------*/\r
  97 \r
  98 void vPortISRStartFirstTask( void )\r
  99 {\r
 100         /* Simply start the scheduler.  This is included here as it can only be\r
 101         called from ARM mode. */\r
 102         asm volatile (                                                                                                          \\r
 103         "LDR            R0, =pxCurrentTCB                                                               \n\t"   \\r
 104         "LDR            R0, [R0]                                                                                \n\t"   \\r
 105         "LDR            LR, [R0]                                                                                \n\t"   \\r
 106                                                                                                                                                 \\r
 107         /* The critical nesting depth is the first item on the stack. */        \\r
 108         /* Load it into the ulCriticalNesting variable. */                                      \\r
 109         "LDR            R0, =ulCriticalNesting                                                  \n\t"   \\r
 110         "LDMFD  LR!, {R1}                                                                                       \n\t"   \\r
 111         "STR            R1, [R0]                                                                                \n\t"   \\r
 112                                                                                                                                                 \\r
 113         /* Get the SPSR from the stack. */                                                                      \\r
 114         "LDMFD  LR!, {R0}                                                                                       \n\t"   \\r
 115         "MSR            SPSR, R0                                                                                \n\t"   \\r
 116                                                                                                                                                 \\r
 117         /* Restore all system mode registers for the task. */                           \\r
 118         "LDMFD  LR, {R0-R14}^                                                                           \n\t"   \\r
 119         "NOP                                                                                                            \n\t"   \\r
 120                                                                                                                                                 \\r
 121         /* Restore the return address. */                                                                       \\r
 122         "LDR            LR, [LR, #+60]                                                                  \n\t"   \\r
 123                                                                                                                                                 \\r
 124         /* And return - correcting the offset in the LR to obtain the */        \\r
 125         /* correct address. */                                                                                          \\r
 126         "SUBS PC, LR, #4                                                                                        \n\t"   \\r
 127         );                                                                                                                                      \r
 128 }\r
 129 /*-----------------------------------------------------------*/\r
 130 \r
 131 void vPortTickISR( void )\r
 132 {\r
 133         /* Increment the RTOS tick count, then look for the highest priority \r
 134         task that is ready to run. */\r
 135         if( xTaskIncrementTick() != pdFALSE )\r
 136         {       \r
 137                 vTaskSwitchContext();\r
 138         }\r
 139                         \r
 140         /* Ready for the next interrupt. */\r
 141         TB_ClearITPendingBit( TB_IT_Update );   \r
 142 }\r
 143 \r
 144 /*-----------------------------------------------------------*/\r
 145 \r
 146 /*\r
 147  * The interrupt management utilities can only be called from ARM mode.  When\r
 148  * THUMB_INTERWORK is defined the utilities are defined as functions here to\r
 149  * ensure a switch to ARM mode.  When THUMB_INTERWORK is not defined then\r
 150  * the utilities are defined as macros in portmacro.h - as per other ports.\r
 151  */\r
 152 #ifdef THUMB_INTERWORK\r
 153 \r
 154         void vPortDisableInterruptsFromThumb( void ) __attribute__ ((naked));\r
 155         void vPortEnableInterruptsFromThumb( void ) __attribute__ ((naked));\r
 156 \r
 157         void vPortDisableInterruptsFromThumb( void )\r
 158         {\r
 159                 asm volatile ( \r
 160                         "STMDB  SP!, {R0}               \n\t"   /* Push R0.                                                                     */\r
 161                         "MRS    R0, CPSR                \n\t"   /* Get CPSR.                                                            */\r
 162                         "ORR    R0, R0, #0xC0   \n\t"   /* Disable IRQ, FIQ.                                            */\r
 163                         "MSR    CPSR, R0                \n\t"   /* Write back modified value.                           */\r
 164                         "LDMIA  SP!, {R0}               \n\t"   /* Pop R0.                                                                      */\r
 165                         "BX             R14" );                                 /* Return back to thumb.                                        */\r
 166         }\r
 167                         \r
 168         void vPortEnableInterruptsFromThumb( void )\r
 169         {\r
 170                 asm volatile ( \r
 171                         "STMDB  SP!, {R0}               \n\t"   /* Push R0.                                                                     */      \r
 172                         "MRS    R0, CPSR                \n\t"   /* Get CPSR.                                                            */      \r
 173                         "BIC    R0, R0, #0xC0   \n\t"   /* Enable IRQ, FIQ.                                                     */      \r
 174                         "MSR    CPSR, R0                \n\t"   /* Write back modified value.                           */      \r
 175                         "LDMIA  SP!, {R0}               \n\t"   /* Pop R0.                                                                      */\r
 176                         "BX             R14" );                                 /* Return back to thumb.                                        */\r
 177         }\r
 178 \r
 179 #endif /* THUMB_INTERWORK */\r
 180 /*-----------------------------------------------------------*/\r
 181 \r
 182 void vPortEnterCritical( void )\r
 183 {\r
 184         /* Disable interrupts as per portDISABLE_INTERRUPTS();                                                  */\r
 185         asm volatile ( \r
 186                 "STMDB  SP!, {R0}                       \n\t"   /* Push R0.                                                             */\r
 187                 "MRS    R0, CPSR                        \n\t"   /* Get CPSR.                                                    */\r
 188                 "ORR    R0, R0, #0xC0           \n\t"   /* Disable IRQ, FIQ.                                    */\r
 189                 "MSR    CPSR, R0                        \n\t"   /* Write back modified value.                   */\r
 190                 "LDMIA  SP!, {R0}" );                           /* Pop R0.                                                              */\r
 191 \r
 192         /* Now interrupts are disabled ulCriticalNesting can be accessed \r
 193         directly.  Increment ulCriticalNesting to keep a count of how many times\r
 194         portENTER_CRITICAL() has been called. */\r
 195         ulCriticalNesting++;\r
 196 }\r
 197 /*-----------------------------------------------------------*/\r
 198 \r
 199 void vPortExitCritical( void )\r
 200 {\r
 201         if( ulCriticalNesting > portNO_CRITICAL_NESTING )\r
 202         {\r
 203                 /* Decrement the nesting count as we are leaving a critical section. */\r
 204                 ulCriticalNesting--;\r
 205 \r
 206                 /* If the nesting level has reached zero then interrupts should be\r
 207                 re-enabled. */\r
 208                 if( ulCriticalNesting == portNO_CRITICAL_NESTING )\r
 209                 {\r
 210                         /* Enable interrupts as per portEXIT_CRITICAL().                                        */\r
 211                         asm volatile ( \r
 212                                 "STMDB  SP!, {R0}               \n\t"   /* Push R0.                                             */      \r
 213                                 "MRS    R0, CPSR                \n\t"   /* Get CPSR.                                    */      \r
 214                                 "BIC    R0, R0, #0xC0   \n\t"   /* Enable IRQ, FIQ.                             */      \r
 215                                 "MSR    CPSR, R0                \n\t"   /* Write back modified value.   */      \r
 216                                 "LDMIA  SP!, {R0}" );                   /* Pop R0.                                              */\r
 217                 }\r
 218         }\r
 219 }\r
 220 \r
 221 \r
 222 \r
 223 \r
 224 \r