2 * FreeRTOS Kernel V10.0.0
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3 * Copyright (C) 2017 Amazon.com, Inc. or its affiliates. All Rights Reserved.
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5 * Permission is hereby granted, free of charge, to any person obtaining a copy of
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6 * this software and associated documentation files (the "Software"), to deal in
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7 * the Software without restriction, including without limitation the rights to
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8 * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
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9 * the Software, and to permit persons to whom the Software is furnished to do so,
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10 * subject to the following conditions:
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12 * The above copyright notice and this permission notice shall be included in all
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13 * copies or substantial portions of the Software. If you wish to use our Amazon
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14 * FreeRTOS name, please do so in a fair use way that does not cause confusion.
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16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
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18 * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
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19 * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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20 * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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21 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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23 * http://www.FreeRTOS.org
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24 * http://aws.amazon.com/freertos
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26 * 1 tab == 4 spaces!
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29 /* Standard includes. */
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33 /* TriCore specific includes. */
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35 #include <machine/intrinsics.h>
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36 #include <machine/cint.h>
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37 #include <machine/wdtcon.h>
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39 /* Kernel includes. */
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40 #include "FreeRTOS.h"
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44 #if configCHECK_FOR_STACK_OVERFLOW > 0
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45 #error "Stack checking cannot be used with this port, as, unlike most ports, the pxTopOfStack member of the TCB is consumed CSA. CSA starvation, loosely equivalent to stack overflow, will result in a trap exception."
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46 /* The stack pointer is accessible using portCSA_TO_ADDRESS( portCSA_TO_ADDRESS( pxCurrentTCB->pxTopOfStack )[ 0 ] )[ 2 ]; */
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47 #endif /* configCHECK_FOR_STACK_OVERFLOW */
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50 /*-----------------------------------------------------------*/
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52 /* System register Definitions. */
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53 #define portSYSTEM_PROGRAM_STATUS_WORD ( 0x000008FFUL ) /* Supervisor Mode, MPU Register Set 0 and Call Depth Counting disabled. */
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54 #define portINITIAL_PRIVILEGED_PROGRAM_STATUS_WORD ( 0x000014FFUL ) /* IO Level 1, MPU Register Set 1 and Call Depth Counting disabled. */
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55 #define portINITIAL_UNPRIVILEGED_PROGRAM_STATUS_WORD ( 0x000010FFUL ) /* IO Level 0, MPU Register Set 1 and Call Depth Counting disabled. */
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56 #define portINITIAL_PCXI_UPPER_CONTEXT_WORD ( 0x00C00000UL ) /* The lower 20 bits identify the CSA address. */
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57 #define portINITIAL_SYSCON ( 0x00000000UL ) /* MPU Disable. */
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59 /* CSA manipulation macros. */
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60 #define portCSA_FCX_MASK ( 0x000FFFFFUL )
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62 /* OS Interrupt and Trap mechanisms. */
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63 #define portRESTORE_PSW_MASK ( ~( 0x000000FFUL ) )
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64 #define portSYSCALL_TRAP ( 6 )
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66 /* Each CSA contains 16 words of data. */
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67 #define portNUM_WORDS_IN_CSA ( 16 )
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69 /* The interrupt enable bit in the PCP_SRC register. */
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70 #define portENABLE_CPU_INTERRUPT ( 1U << 12U )
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71 /*-----------------------------------------------------------*/
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74 * Perform any hardware configuration necessary to generate the tick interrupt.
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76 static void prvSystemTickHandler( int ) __attribute__((longcall));
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77 static void prvSetupTimerInterrupt( void );
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80 * Trap handler for yields.
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82 static void prvTrapYield( int iTrapIdentification );
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85 * Priority 1 interrupt handler for yields pended from an interrupt.
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87 static void prvInterruptYield( int iTrapIdentification );
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89 /*-----------------------------------------------------------*/
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91 /* This reference is required by the save/restore context macros. */
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92 extern volatile uint32_t *pxCurrentTCB;
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94 /* Precalculate the compare match value at compile time. */
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95 static const uint32_t ulCompareMatchValue = ( configPERIPHERAL_CLOCK_HZ / configTICK_RATE_HZ );
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97 /*-----------------------------------------------------------*/
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99 StackType_t *pxPortInitialiseStack( StackType_t * pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
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101 uint32_t *pulUpperCSA = NULL;
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102 uint32_t *pulLowerCSA = NULL;
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104 /* 16 Address Registers (4 Address registers are global), 16 Data
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105 Registers, and 3 System Registers.
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107 There are 3 registers that track the CSAs.
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108 FCX points to the head of globally free set of CSAs.
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109 PCX for the task needs to point to Lower->Upper->NULL arrangement.
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110 LCX points to the last free CSA so that corrective action can be taken.
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112 Need two CSAs to store the context of a task.
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113 The upper context contains D8-D15, A10-A15, PSW and PCXI->NULL.
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114 The lower context contains D0-D7, A2-A7, A11 and PCXI->UpperContext.
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115 The pxCurrentTCB->pxTopOfStack points to the Lower Context RSLCX matching the initial BISR.
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116 The Lower Context points to the Upper Context ready for the return from the interrupt handler.
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118 The Real stack pointer for the task is stored in the A10 which is restored
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119 with the upper context. */
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121 /* Have to disable interrupts here because the CSAs are going to be
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123 portENTER_CRITICAL();
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125 /* DSync to ensure that buffering is not a problem. */
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128 /* Consume two free CSAs. */
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129 pulLowerCSA = portCSA_TO_ADDRESS( __MFCR( $FCX ) );
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130 if( NULL != pulLowerCSA )
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132 /* The Lower Links to the Upper. */
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133 pulUpperCSA = portCSA_TO_ADDRESS( pulLowerCSA[ 0 ] );
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136 /* Check that we have successfully reserved two CSAs. */
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137 if( ( NULL != pulLowerCSA ) && ( NULL != pulUpperCSA ) )
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139 /* Remove the two consumed CSAs from the free CSA list. */
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142 _mtcr( $FCX, pulUpperCSA[ 0 ] );
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148 /* Simply trigger a context list depletion trap. */
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152 portEXIT_CRITICAL();
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154 /* Clear the upper CSA. */
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155 memset( pulUpperCSA, 0, portNUM_WORDS_IN_CSA * sizeof( uint32_t ) );
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157 /* Upper Context. */
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158 pulUpperCSA[ 2 ] = ( uint32_t )pxTopOfStack; /* A10; Stack Return aka Stack Pointer */
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159 pulUpperCSA[ 1 ] = portSYSTEM_PROGRAM_STATUS_WORD; /* PSW */
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161 /* Clear the lower CSA. */
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162 memset( pulLowerCSA, 0, portNUM_WORDS_IN_CSA * sizeof( uint32_t ) );
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164 /* Lower Context. */
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165 pulLowerCSA[ 8 ] = ( uint32_t ) pvParameters; /* A4; Address Type Parameter Register */
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166 pulLowerCSA[ 1 ] = ( uint32_t ) pxCode; /* A11; Return Address aka RA */
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168 /* PCXI pointing to the Upper context. */
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169 pulLowerCSA[ 0 ] = ( portINITIAL_PCXI_UPPER_CONTEXT_WORD | ( uint32_t ) portADDRESS_TO_CSA( pulUpperCSA ) );
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171 /* Save the link to the CSA in the top of stack. */
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172 pxTopOfStack = (uint32_t * ) portADDRESS_TO_CSA( pulLowerCSA );
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174 /* DSync to ensure that buffering is not a problem. */
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177 return pxTopOfStack;
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179 /*-----------------------------------------------------------*/
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181 int32_t xPortStartScheduler( void )
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183 extern void vTrapInstallHandlers( void );
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184 uint32_t ulMFCR = 0UL;
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185 uint32_t *pulUpperCSA = NULL;
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186 uint32_t *pulLowerCSA = NULL;
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188 /* Interrupts at or below configMAX_SYSCALL_INTERRUPT_PRIORITY are disable
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189 when this function is called. */
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191 /* Set-up the timer interrupt. */
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192 prvSetupTimerInterrupt();
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194 /* Install the Trap Handlers. */
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195 vTrapInstallHandlers();
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197 /* Install the Syscall Handler for yield calls. */
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198 if( 0 == _install_trap_handler( portSYSCALL_TRAP, prvTrapYield ) )
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200 /* Failed to install the yield handler, force an assert. */
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201 configASSERT( ( ( volatile void * ) NULL ) );
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204 /* Enable then install the priority 1 interrupt for pending context
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205 switches from an ISR. See mod_SRC in the TriCore manual. */
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206 CPU_SRC0.reg = ( portENABLE_CPU_INTERRUPT ) | ( configKERNEL_YIELD_PRIORITY );
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207 if( 0 == _install_int_handler( configKERNEL_YIELD_PRIORITY, prvInterruptYield, 0 ) )
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209 /* Failed to install the yield handler, force an assert. */
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210 configASSERT( ( ( volatile void * ) NULL ) );
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215 /* Load the initial SYSCON. */
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216 _mtcr( $SYSCON, portINITIAL_SYSCON );
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219 /* ENDINIT has already been applied in the 'cstart.c' code. */
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221 /* Clear the PSW.CDC to enable the use of an RFE without it generating an
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222 exception because this code is not genuinely in an exception. */
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223 ulMFCR = __MFCR( $PSW );
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224 ulMFCR &= portRESTORE_PSW_MASK;
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226 _mtcr( $PSW, ulMFCR );
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229 /* Finally, perform the equivalent of a portRESTORE_CONTEXT() */
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230 pulLowerCSA = portCSA_TO_ADDRESS( ( *pxCurrentTCB ) );
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231 pulUpperCSA = portCSA_TO_ADDRESS( pulLowerCSA[0] );
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233 _mtcr( $PCXI, *pxCurrentTCB );
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239 /* Return to the first task selected to execute. */
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240 __asm volatile( "rfe" );
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242 /* Will not get here. */
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245 /*-----------------------------------------------------------*/
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247 static void prvSetupTimerInterrupt( void )
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249 /* Set-up the clock divider. */
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252 /* Wait until access to Endint protected register is enabled. */
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253 while( 0 != ( WDT_CON0.reg & 0x1UL ) );
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255 /* RMC == 1 so STM Clock == FPI */
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256 STM_CLC.reg = ( 1UL << 8 );
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260 /* Determine how many bits are used without changing other bits in the CMCON register. */
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261 STM_CMCON.reg &= ~( 0x1fUL );
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262 STM_CMCON.reg |= ( 0x1fUL - __CLZ( configPERIPHERAL_CLOCK_HZ / configTICK_RATE_HZ ) );
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264 /* Take into account the current time so a tick doesn't happen immediately. */
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265 STM_CMP0.reg = ulCompareMatchValue + STM_TIM0.reg;
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267 if( 0 != _install_int_handler( configKERNEL_INTERRUPT_PRIORITY, prvSystemTickHandler, 0 ) )
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269 /* Set-up the interrupt. */
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270 STM_SRC0.reg = ( configKERNEL_INTERRUPT_PRIORITY | 0x00005000UL );
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272 /* Enable the Interrupt. */
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273 STM_ISRR.reg &= ~( 0x03UL );
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274 STM_ISRR.reg |= 0x1UL;
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275 STM_ISRR.reg &= ~( 0x07UL );
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276 STM_ICR.reg |= 0x1UL;
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280 /* Failed to install the Tick Interrupt. */
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281 configASSERT( ( ( volatile void * ) NULL ) );
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284 /*-----------------------------------------------------------*/
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286 static void prvSystemTickHandler( int iArg )
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288 uint32_t ulSavedInterruptMask;
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289 uint32_t *pxUpperCSA = NULL;
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290 uint32_t xUpperCSA = 0UL;
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291 extern volatile uint32_t *pxCurrentTCB;
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292 int32_t lYieldRequired;
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294 /* Just to avoid compiler warnings about unused parameters. */
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297 /* Clear the interrupt source. */
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298 STM_ISRR.reg = 1UL;
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300 /* Reload the Compare Match register for X ticks into the future.
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302 If critical section or interrupt nesting budgets are exceeded, then
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303 it is possible that the calculated next compare match value is in the
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304 past. If this occurs (unlikely), it is possible that the resulting
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305 time slippage will exceed a single tick period. Any adverse effect of
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306 this is time bounded by the fact that only the first n bits of the 56 bit
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307 STM timer are being used for a compare match, so another compare match
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308 will occur after an overflow in just those n bits (not the entire 56 bits).
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309 As an example, if the peripheral clock is 75MHz, and the tick rate is 1KHz,
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310 a missed tick could result in the next tick interrupt occurring within a
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311 time that is 1.7 times the desired period. The fact that this is greater
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312 than a single tick period is an effect of using a timer that cannot be
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313 automatically reset, in hardware, by the occurrence of a tick interrupt.
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314 Changing the tick source to a timer that has an automatic reset on compare
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315 match (such as a GPTA timer) will reduce the maximum possible additional
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316 period to exactly 1 times the desired period. */
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317 STM_CMP0.reg += ulCompareMatchValue;
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319 /* Kernel API calls require Critical Sections. */
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320 ulSavedInterruptMask = portSET_INTERRUPT_MASK_FROM_ISR();
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322 /* Increment the Tick. */
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323 lYieldRequired = xTaskIncrementTick();
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325 portCLEAR_INTERRUPT_MASK_FROM_ISR( ulSavedInterruptMask );
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327 if( lYieldRequired != pdFALSE )
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329 /* Save the context of a task.
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330 The upper context is automatically saved when entering a trap or interrupt.
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331 Need to save the lower context as well and copy the PCXI CSA ID into
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332 pxCurrentTCB->pxTopOfStack. Only Lower Context CSA IDs may be saved to the
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335 Call vTaskSwitchContext to select the next task, note that this changes the
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336 value of pxCurrentTCB so that it needs to be reloaded.
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338 Call vPortSetMPURegisterSetOne to change the MPU mapping for the task
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339 that has just been switched in.
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341 Load the context of the task.
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342 Need to restore the lower context by loading the CSA from
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343 pxCurrentTCB->pxTopOfStack into PCXI (effectively changing the call stack).
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344 In the Interrupt handler post-amble, RSLCX will restore the lower context
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345 of the task. RFE will restore the upper context of the task, jump to the
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346 return address and restore the previous state of interrupts being
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347 enabled/disabled. */
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350 xUpperCSA = __MFCR( $PCXI );
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351 pxUpperCSA = portCSA_TO_ADDRESS( xUpperCSA );
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352 *pxCurrentTCB = pxUpperCSA[ 0 ];
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353 vTaskSwitchContext();
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354 pxUpperCSA[ 0 ] = *pxCurrentTCB;
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355 CPU_SRC0.bits.SETR = 0;
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359 /*-----------------------------------------------------------*/
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362 * When a task is deleted, it is yielded permanently until the IDLE task
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363 * has an opportunity to reclaim the memory that that task was using.
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364 * Typically, the memory used by a task is the TCB and Stack but in the
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365 * TriCore this includes the CSAs that were consumed as part of the Call
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366 * Stack. These CSAs can only be returned to the Globally Free Pool when
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367 * they are not part of the current Call Stack, hence, delaying the
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368 * reclamation until the IDLE task is freeing the task's other resources.
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369 * This function uses the head of the linked list of CSAs (from when the
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370 * task yielded for the last time) and finds the tail (the very bottom of
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371 * the call stack) and inserts this list at the head of the Free list,
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372 * attaching the existing Free List to the tail of the reclaimed call stack.
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374 * NOTE: the IDLE task needs processing time to complete this function
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375 * and in heavily loaded systems, the Free CSAs may be consumed faster
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376 * than they can be freed assuming that tasks are being spawned and
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377 * deleted frequently.
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379 void vPortReclaimCSA( uint32_t *pxTCB )
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381 uint32_t pxHeadCSA, pxTailCSA, pxFreeCSA;
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382 uint32_t *pulNextCSA;
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384 /* A pointer to the first CSA in the list of CSAs consumed by the task is
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385 stored in the first element of the tasks TCB structure (where the stack
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386 pointer would be on a traditional stack based architecture). */
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387 pxHeadCSA = ( *pxTCB ) & portCSA_FCX_MASK;
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389 /* Mask off everything in the CSA link field other than the address. If
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390 the address is NULL, then the CSA is not linking anywhere and there is
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392 pxTailCSA = pxHeadCSA;
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394 /* Convert the link value to contain just a raw address and store this
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395 in a local variable. */
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396 pulNextCSA = portCSA_TO_ADDRESS( pxTailCSA );
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398 /* Iterate over the CSAs that were consumed as part of the task. The
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399 first field in the CSA is the pointer to then next CSA. Mask off
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400 everything in the pointer to the next CSA, other than the link address.
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401 If this is NULL, then the CSA currently being pointed to is the last in
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403 while( 0UL != ( pulNextCSA[ 0 ] & portCSA_FCX_MASK ) )
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405 /* Clear all bits of the pointer to the next in the chain, other
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406 than the address bits themselves. */
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407 pulNextCSA[ 0 ] = pulNextCSA[ 0 ] & portCSA_FCX_MASK;
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409 /* Move the pointer to point to the next CSA in the list. */
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410 pxTailCSA = pulNextCSA[ 0 ];
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412 /* Update the local pointer to the CSA. */
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413 pulNextCSA = portCSA_TO_ADDRESS( pxTailCSA );
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418 /* Look up the current free CSA head. */
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420 pxFreeCSA = __MFCR( $FCX );
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422 /* Join the current Free onto the Tail of what is being reclaimed. */
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423 portCSA_TO_ADDRESS( pxTailCSA )[ 0 ] = pxFreeCSA;
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425 /* Move the head of the reclaimed into the Free. */
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427 _mtcr( $FCX, pxHeadCSA );
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432 /*-----------------------------------------------------------*/
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434 void vPortEndScheduler( void )
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436 /* Nothing to do. Unlikely to want to end. */
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438 /*-----------------------------------------------------------*/
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440 static void prvTrapYield( int iTrapIdentification )
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442 uint32_t *pxUpperCSA = NULL;
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443 uint32_t xUpperCSA = 0UL;
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444 extern volatile uint32_t *pxCurrentTCB;
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446 switch( iTrapIdentification )
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448 case portSYSCALL_TASK_YIELD:
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449 /* Save the context of a task.
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450 The upper context is automatically saved when entering a trap or interrupt.
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451 Need to save the lower context as well and copy the PCXI CSA ID into
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452 pxCurrentTCB->pxTopOfStack. Only Lower Context CSA IDs may be saved to the
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455 Call vTaskSwitchContext to select the next task, note that this changes the
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456 value of pxCurrentTCB so that it needs to be reloaded.
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458 Call vPortSetMPURegisterSetOne to change the MPU mapping for the task
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459 that has just been switched in.
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461 Load the context of the task.
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462 Need to restore the lower context by loading the CSA from
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463 pxCurrentTCB->pxTopOfStack into PCXI (effectively changing the call stack).
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464 In the Interrupt handler post-amble, RSLCX will restore the lower context
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465 of the task. RFE will restore the upper context of the task, jump to the
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466 return address and restore the previous state of interrupts being
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467 enabled/disabled. */
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470 xUpperCSA = __MFCR( $PCXI );
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471 pxUpperCSA = portCSA_TO_ADDRESS( xUpperCSA );
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472 *pxCurrentTCB = pxUpperCSA[ 0 ];
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473 vTaskSwitchContext();
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474 pxUpperCSA[ 0 ] = *pxCurrentTCB;
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475 CPU_SRC0.bits.SETR = 0;
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480 /* Unimplemented trap called. */
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481 configASSERT( ( ( volatile void * ) NULL ) );
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485 /*-----------------------------------------------------------*/
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487 static void prvInterruptYield( int iId )
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489 uint32_t *pxUpperCSA = NULL;
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490 uint32_t xUpperCSA = 0UL;
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491 extern volatile uint32_t *pxCurrentTCB;
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493 /* Just to remove compiler warnings. */
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496 /* Save the context of a task.
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497 The upper context is automatically saved when entering a trap or interrupt.
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498 Need to save the lower context as well and copy the PCXI CSA ID into
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499 pxCurrentTCB->pxTopOfStack. Only Lower Context CSA IDs may be saved to the
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502 Call vTaskSwitchContext to select the next task, note that this changes the
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503 value of pxCurrentTCB so that it needs to be reloaded.
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505 Call vPortSetMPURegisterSetOne to change the MPU mapping for the task
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506 that has just been switched in.
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508 Load the context of the task.
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509 Need to restore the lower context by loading the CSA from
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510 pxCurrentTCB->pxTopOfStack into PCXI (effectively changing the call stack).
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511 In the Interrupt handler post-amble, RSLCX will restore the lower context
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512 of the task. RFE will restore the upper context of the task, jump to the
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513 return address and restore the previous state of interrupts being
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514 enabled/disabled. */
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517 xUpperCSA = __MFCR( $PCXI );
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518 pxUpperCSA = portCSA_TO_ADDRESS( xUpperCSA );
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519 *pxCurrentTCB = pxUpperCSA[ 0 ];
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520 vTaskSwitchContext();
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521 pxUpperCSA[ 0 ] = *pxCurrentTCB;
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522 CPU_SRC0.bits.SETR = 0;
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525 /*-----------------------------------------------------------*/
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527 uint32_t uxPortSetInterruptMaskFromISR( void )
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529 uint32_t uxReturn = 0UL;
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532 uxReturn = __MFCR( $ICR );
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533 _mtcr( $ICR, ( ( uxReturn & ~portCCPN_MASK ) | configMAX_SYSCALL_INTERRUPT_PRIORITY ) );
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537 /* Return just the interrupt mask bits. */
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538 return ( uxReturn & portCCPN_MASK );
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540 /*-----------------------------------------------------------*/
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