2 FreeRTOS V7.5.2 - Copyright (C) 2013 Real Time Engineers Ltd.
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4 VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
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6 ***************************************************************************
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8 * FreeRTOS provides completely free yet professionally developed, *
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9 * robust, strictly quality controlled, supported, and cross *
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10 * platform software that has become a de facto standard. *
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12 * Help yourself get started quickly and support the FreeRTOS *
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13 * project by purchasing a FreeRTOS tutorial book, reference *
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14 * manual, or both from: http://www.FreeRTOS.org/Documentation *
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18 ***************************************************************************
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20 This file is part of the FreeRTOS distribution.
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22 FreeRTOS is free software; you can redistribute it and/or modify it under
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23 the terms of the GNU General Public License (version 2) as published by the
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24 Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.
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26 >>! NOTE: The modification to the GPL is included to allow you to distribute
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27 >>! a combined work that includes FreeRTOS without being obliged to provide
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28 >>! the source code for proprietary components outside of the FreeRTOS
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31 FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
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32 WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
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33 FOR A PARTICULAR PURPOSE. Full license text is available from the following
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34 link: http://www.freertos.org/a00114.html
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38 ***************************************************************************
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40 * Having a problem? Start by reading the FAQ "My application does *
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41 * not run, what could be wrong?" *
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43 * http://www.FreeRTOS.org/FAQHelp.html *
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45 ***************************************************************************
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47 http://www.FreeRTOS.org - Documentation, books, training, latest versions,
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48 license and Real Time Engineers Ltd. contact details.
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50 http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
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51 including FreeRTOS+Trace - an indispensable productivity tool, a DOS
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52 compatible FAT file system, and our tiny thread aware UDP/IP stack.
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54 http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High
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55 Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS
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56 licenses offer ticketed support, indemnification and middleware.
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58 http://www.SafeRTOS.com - High Integrity Systems also provide a safety
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59 engineered and independently SIL3 certified version for use in safety and
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60 mission critical applications that require provable dependability.
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65 /* Standard includes. */
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69 /* TriCore specific includes. */
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71 #include <machine/intrinsics.h>
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72 #include <machine/cint.h>
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73 #include <machine/wdtcon.h>
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75 /* Kernel includes. */
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76 #include "FreeRTOS.h"
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80 #if configCHECK_FOR_STACK_OVERFLOW > 0
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81 #error "Stack checking cannot be used with this port, as, unlike most ports, the pxTopOfStack member of the TCB is consumed CSA. CSA starvation, loosely equivalent to stack overflow, will result in a trap exception."
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82 /* The stack pointer is accessible using portCSA_TO_ADDRESS( portCSA_TO_ADDRESS( pxCurrentTCB->pxTopOfStack )[ 0 ] )[ 2 ]; */
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83 #endif /* configCHECK_FOR_STACK_OVERFLOW */
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86 /*-----------------------------------------------------------*/
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88 /* System register Definitions. */
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89 #define portSYSTEM_PROGRAM_STATUS_WORD ( 0x000008FFUL ) /* Supervisor Mode, MPU Register Set 0 and Call Depth Counting disabled. */
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90 #define portINITIAL_PRIVILEGED_PROGRAM_STATUS_WORD ( 0x000014FFUL ) /* IO Level 1, MPU Register Set 1 and Call Depth Counting disabled. */
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91 #define portINITIAL_UNPRIVILEGED_PROGRAM_STATUS_WORD ( 0x000010FFUL ) /* IO Level 0, MPU Register Set 1 and Call Depth Counting disabled. */
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92 #define portINITIAL_PCXI_UPPER_CONTEXT_WORD ( 0x00C00000UL ) /* The lower 20 bits identify the CSA address. */
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93 #define portINITIAL_SYSCON ( 0x00000000UL ) /* MPU Disable. */
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95 /* CSA manipulation macros. */
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96 #define portCSA_FCX_MASK ( 0x000FFFFFUL )
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98 /* OS Interrupt and Trap mechanisms. */
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99 #define portRESTORE_PSW_MASK ( ~( 0x000000FFUL ) )
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100 #define portSYSCALL_TRAP ( 6 )
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102 /* Each CSA contains 16 words of data. */
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103 #define portNUM_WORDS_IN_CSA ( 16 )
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105 /* The interrupt enable bit in the PCP_SRC register. */
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106 #define portENABLE_CPU_INTERRUPT ( 1U << 12U )
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107 /*-----------------------------------------------------------*/
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110 * Perform any hardware configuration necessary to generate the tick interrupt.
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112 static void prvSystemTickHandler( int ) __attribute__((longcall));
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113 static void prvSetupTimerInterrupt( void );
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116 * Trap handler for yields.
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118 static void prvTrapYield( int iTrapIdentification );
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121 * Priority 1 interrupt handler for yields pended from an interrupt.
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123 static void prvInterruptYield( int iTrapIdentification );
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125 /*-----------------------------------------------------------*/
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127 /* This reference is required by the save/restore context macros. */
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128 extern volatile unsigned long *pxCurrentTCB;
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130 /* Precalculate the compare match value at compile time. */
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131 static const unsigned long ulCompareMatchValue = ( configPERIPHERAL_CLOCK_HZ / configTICK_RATE_HZ );
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133 /*-----------------------------------------------------------*/
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135 portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE * pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters )
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137 unsigned long *pulUpperCSA = NULL;
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138 unsigned long *pulLowerCSA = NULL;
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140 /* 16 Address Registers (4 Address registers are global), 16 Data
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141 Registers, and 3 System Registers.
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143 There are 3 registers that track the CSAs.
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144 FCX points to the head of globally free set of CSAs.
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145 PCX for the task needs to point to Lower->Upper->NULL arrangement.
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146 LCX points to the last free CSA so that corrective action can be taken.
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148 Need two CSAs to store the context of a task.
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149 The upper context contains D8-D15, A10-A15, PSW and PCXI->NULL.
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150 The lower context contains D0-D7, A2-A7, A11 and PCXI->UpperContext.
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151 The pxCurrentTCB->pxTopOfStack points to the Lower Context RSLCX matching the initial BISR.
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152 The Lower Context points to the Upper Context ready for the return from the interrupt handler.
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154 The Real stack pointer for the task is stored in the A10 which is restored
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155 with the upper context. */
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157 /* Have to disable interrupts here because the CSAs are going to be
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159 portENTER_CRITICAL();
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161 /* DSync to ensure that buffering is not a problem. */
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164 /* Consume two free CSAs. */
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165 pulLowerCSA = portCSA_TO_ADDRESS( _mfcr( $FCX ) );
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166 if( NULL != pulLowerCSA )
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168 /* The Lower Links to the Upper. */
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169 pulUpperCSA = portCSA_TO_ADDRESS( pulLowerCSA[ 0 ] );
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172 /* Check that we have successfully reserved two CSAs. */
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173 if( ( NULL != pulLowerCSA ) && ( NULL != pulUpperCSA ) )
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175 /* Remove the two consumed CSAs from the free CSA list. */
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178 _mtcr( $FCX, pulUpperCSA[ 0 ] );
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184 /* Simply trigger a context list depletion trap. */
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188 portEXIT_CRITICAL();
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190 /* Clear the upper CSA. */
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191 memset( pulUpperCSA, 0, portNUM_WORDS_IN_CSA * sizeof( unsigned long ) );
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193 /* Upper Context. */
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194 pulUpperCSA[ 2 ] = ( unsigned long )pxTopOfStack; /* A10; Stack Return aka Stack Pointer */
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195 pulUpperCSA[ 1 ] = portSYSTEM_PROGRAM_STATUS_WORD; /* PSW */
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197 /* Clear the lower CSA. */
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198 memset( pulLowerCSA, 0, portNUM_WORDS_IN_CSA * sizeof( unsigned long ) );
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200 /* Lower Context. */
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201 pulLowerCSA[ 8 ] = ( unsigned long ) pvParameters; /* A4; Address Type Parameter Register */
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202 pulLowerCSA[ 1 ] = ( unsigned long ) pxCode; /* A11; Return Address aka RA */
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204 /* PCXI pointing to the Upper context. */
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205 pulLowerCSA[ 0 ] = ( portINITIAL_PCXI_UPPER_CONTEXT_WORD | ( unsigned long ) portADDRESS_TO_CSA( pulUpperCSA ) );
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207 /* Save the link to the CSA in the top of stack. */
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208 pxTopOfStack = (unsigned long * ) portADDRESS_TO_CSA( pulLowerCSA );
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210 /* DSync to ensure that buffering is not a problem. */
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213 return pxTopOfStack;
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215 /*-----------------------------------------------------------*/
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217 long xPortStartScheduler( void )
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219 extern void vTrapInstallHandlers( void );
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220 unsigned long ulMFCR = 0UL;
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221 unsigned long *pulUpperCSA = NULL;
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222 unsigned long *pulLowerCSA = NULL;
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224 /* Interrupts at or below configMAX_SYSCALL_INTERRUPT_PRIORITY are disable
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225 when this function is called. */
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227 /* Set-up the timer interrupt. */
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228 prvSetupTimerInterrupt();
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230 /* Install the Trap Handlers. */
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231 vTrapInstallHandlers();
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233 /* Install the Syscall Handler for yield calls. */
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234 if( 0 == _install_trap_handler( portSYSCALL_TRAP, prvTrapYield ) )
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236 /* Failed to install the yield handler, force an assert. */
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237 configASSERT( ( ( volatile void * ) NULL ) );
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240 /* Enable then install the priority 1 interrupt for pending context
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241 switches from an ISR. See mod_SRC in the TriCore manual. */
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242 CPU_SRC0.reg = ( portENABLE_CPU_INTERRUPT ) | ( configKERNEL_YIELD_PRIORITY );
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243 if( 0 == _install_int_handler( configKERNEL_YIELD_PRIORITY, prvInterruptYield, 0 ) )
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245 /* Failed to install the yield handler, force an assert. */
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246 configASSERT( ( ( volatile void * ) NULL ) );
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251 /* Load the initial SYSCON. */
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252 _mtcr( $SYSCON, portINITIAL_SYSCON );
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255 /* ENDINIT has already been applied in the 'cstart.c' code. */
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257 /* Clear the PSW.CDC to enable the use of an RFE without it generating an
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258 exception because this code is not genuinely in an exception. */
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259 ulMFCR = _mfcr( $PSW );
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260 ulMFCR &= portRESTORE_PSW_MASK;
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262 _mtcr( $PSW, ulMFCR );
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265 /* Finally, perform the equivalent of a portRESTORE_CONTEXT() */
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266 pulLowerCSA = portCSA_TO_ADDRESS( ( *pxCurrentTCB ) );
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267 pulUpperCSA = portCSA_TO_ADDRESS( pulLowerCSA[0] );
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269 _mtcr( $PCXI, *pxCurrentTCB );
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275 /* Return to the first task selected to execute. */
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276 __asm volatile( "rfe" );
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278 /* Will not get here. */
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281 /*-----------------------------------------------------------*/
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283 static void prvSetupTimerInterrupt( void )
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285 /* Set-up the clock divider. */
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288 /* Wait until access to Endint protected register is enabled. */
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289 while( 0 != ( WDT_CON0.reg & 0x1UL ) );
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291 /* RMC == 1 so STM Clock == FPI */
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292 STM_CLC.reg = ( 1UL << 8 );
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296 /* Determine how many bits are used without changing other bits in the CMCON register. */
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297 STM_CMCON.reg &= ~( 0x1fUL );
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298 STM_CMCON.reg |= ( 0x1fUL - __CLZ( configPERIPHERAL_CLOCK_HZ / configTICK_RATE_HZ ) );
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300 /* Take into account the current time so a tick doesn't happen immediately. */
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301 STM_CMP0.reg = ulCompareMatchValue + STM_TIM0.reg;
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303 if( 0 != _install_int_handler( configKERNEL_INTERRUPT_PRIORITY, prvSystemTickHandler, 0 ) )
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305 /* Set-up the interrupt. */
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306 STM_SRC0.reg = ( configKERNEL_INTERRUPT_PRIORITY | 0x00005000UL );
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308 /* Enable the Interrupt. */
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309 STM_ISRR.reg &= ~( 0x03UL );
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310 STM_ISRR.reg |= 0x1UL;
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311 STM_ISRR.reg &= ~( 0x07UL );
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312 STM_ICR.reg |= 0x1UL;
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316 /* Failed to install the Tick Interrupt. */
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317 configASSERT( ( ( volatile void * ) NULL ) );
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320 /*-----------------------------------------------------------*/
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322 static void prvSystemTickHandler( int iArg )
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324 unsigned long ulSavedInterruptMask;
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325 unsigned long *pxUpperCSA = NULL;
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326 unsigned long xUpperCSA = 0UL;
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327 extern volatile unsigned long *pxCurrentTCB;
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328 long lYieldRequired;
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330 /* Just to avoid compiler warnings about unused parameters. */
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333 /* Clear the interrupt source. */
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334 STM_ISRR.reg = 1UL;
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336 /* Reload the Compare Match register for X ticks into the future.
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338 If critical section or interrupt nesting budgets are exceeded, then
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339 it is possible that the calculated next compare match value is in the
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340 past. If this occurs (unlikely), it is possible that the resulting
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341 time slippage will exceed a single tick period. Any adverse effect of
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342 this is time bounded by the fact that only the first n bits of the 56 bit
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343 STM timer are being used for a compare match, so another compare match
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344 will occur after an overflow in just those n bits (not the entire 56 bits).
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345 As an example, if the peripheral clock is 75MHz, and the tick rate is 1KHz,
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346 a missed tick could result in the next tick interrupt occurring within a
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347 time that is 1.7 times the desired period. The fact that this is greater
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348 than a single tick period is an effect of using a timer that cannot be
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349 automatically reset, in hardware, by the occurrence of a tick interrupt.
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350 Changing the tick source to a timer that has an automatic reset on compare
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351 match (such as a GPTA timer) will reduce the maximum possible additional
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352 period to exactly 1 times the desired period. */
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353 STM_CMP0.reg += ulCompareMatchValue;
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355 /* Kernel API calls require Critical Sections. */
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356 ulSavedInterruptMask = portSET_INTERRUPT_MASK_FROM_ISR();
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358 /* Increment the Tick. */
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359 lYieldRequired = xTaskIncrementTick();
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361 portCLEAR_INTERRUPT_MASK_FROM_ISR( ulSavedInterruptMask );
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363 if( lYieldRequired != pdFALSE )
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365 /* Save the context of a task.
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366 The upper context is automatically saved when entering a trap or interrupt.
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367 Need to save the lower context as well and copy the PCXI CSA ID into
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368 pxCurrentTCB->pxTopOfStack. Only Lower Context CSA IDs may be saved to the
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371 Call vTaskSwitchContext to select the next task, note that this changes the
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372 value of pxCurrentTCB so that it needs to be reloaded.
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374 Call vPortSetMPURegisterSetOne to change the MPU mapping for the task
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375 that has just been switched in.
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377 Load the context of the task.
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378 Need to restore the lower context by loading the CSA from
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379 pxCurrentTCB->pxTopOfStack into PCXI (effectively changing the call stack).
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380 In the Interrupt handler post-amble, RSLCX will restore the lower context
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381 of the task. RFE will restore the upper context of the task, jump to the
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382 return address and restore the previous state of interrupts being
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383 enabled/disabled. */
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386 xUpperCSA = _mfcr( $PCXI );
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387 pxUpperCSA = portCSA_TO_ADDRESS( xUpperCSA );
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388 *pxCurrentTCB = pxUpperCSA[ 0 ];
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389 vTaskSwitchContext();
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390 pxUpperCSA[ 0 ] = *pxCurrentTCB;
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391 CPU_SRC0.bits.SETR = 0;
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395 /*-----------------------------------------------------------*/
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398 * When a task is deleted, it is yielded permanently until the IDLE task
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399 * has an opportunity to reclaim the memory that that task was using.
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400 * Typically, the memory used by a task is the TCB and Stack but in the
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401 * TriCore this includes the CSAs that were consumed as part of the Call
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402 * Stack. These CSAs can only be returned to the Globally Free Pool when
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403 * they are not part of the current Call Stack, hence, delaying the
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404 * reclamation until the IDLE task is freeing the task's other resources.
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405 * This function uses the head of the linked list of CSAs (from when the
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406 * task yielded for the last time) and finds the tail (the very bottom of
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407 * the call stack) and inserts this list at the head of the Free list,
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408 * attaching the existing Free List to the tail of the reclaimed call stack.
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410 * NOTE: the IDLE task needs processing time to complete this function
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411 * and in heavily loaded systems, the Free CSAs may be consumed faster
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412 * than they can be freed assuming that tasks are being spawned and
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413 * deleted frequently.
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415 void vPortReclaimCSA( unsigned long *pxTCB )
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417 unsigned long pxHeadCSA, pxTailCSA, pxFreeCSA;
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418 unsigned long *pulNextCSA;
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420 /* A pointer to the first CSA in the list of CSAs consumed by the task is
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421 stored in the first element of the tasks TCB structure (where the stack
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422 pointer would be on a traditional stack based architecture). */
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423 pxHeadCSA = ( *pxTCB ) & portCSA_FCX_MASK;
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425 /* Mask off everything in the CSA link field other than the address. If
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426 the address is NULL, then the CSA is not linking anywhere and there is
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428 pxTailCSA = pxHeadCSA;
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430 /* Convert the link value to contain just a raw address and store this
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431 in a local variable. */
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432 pulNextCSA = portCSA_TO_ADDRESS( pxTailCSA );
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434 /* Iterate over the CSAs that were consumed as part of the task. The
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435 first field in the CSA is the pointer to then next CSA. Mask off
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436 everything in the pointer to the next CSA, other than the link address.
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437 If this is NULL, then the CSA currently being pointed to is the last in
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439 while( 0UL != ( pulNextCSA[ 0 ] & portCSA_FCX_MASK ) )
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441 /* Clear all bits of the pointer to the next in the chain, other
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442 than the address bits themselves. */
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443 pulNextCSA[ 0 ] = pulNextCSA[ 0 ] & portCSA_FCX_MASK;
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445 /* Move the pointer to point to the next CSA in the list. */
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446 pxTailCSA = pulNextCSA[ 0 ];
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448 /* Update the local pointer to the CSA. */
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449 pulNextCSA = portCSA_TO_ADDRESS( pxTailCSA );
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454 /* Look up the current free CSA head. */
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456 pxFreeCSA = _mfcr( $FCX );
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458 /* Join the current Free onto the Tail of what is being reclaimed. */
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459 portCSA_TO_ADDRESS( pxTailCSA )[ 0 ] = pxFreeCSA;
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461 /* Move the head of the reclaimed into the Free. */
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463 _mtcr( $FCX, pxHeadCSA );
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468 /*-----------------------------------------------------------*/
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470 void vPortEndScheduler( void )
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472 /* Nothing to do. Unlikely to want to end. */
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474 /*-----------------------------------------------------------*/
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476 static void prvTrapYield( int iTrapIdentification )
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478 unsigned long *pxUpperCSA = NULL;
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479 unsigned long xUpperCSA = 0UL;
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480 extern volatile unsigned long *pxCurrentTCB;
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482 switch( iTrapIdentification )
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484 case portSYSCALL_TASK_YIELD:
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485 /* Save the context of a task.
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486 The upper context is automatically saved when entering a trap or interrupt.
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487 Need to save the lower context as well and copy the PCXI CSA ID into
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488 pxCurrentTCB->pxTopOfStack. Only Lower Context CSA IDs may be saved to the
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491 Call vTaskSwitchContext to select the next task, note that this changes the
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492 value of pxCurrentTCB so that it needs to be reloaded.
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494 Call vPortSetMPURegisterSetOne to change the MPU mapping for the task
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495 that has just been switched in.
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497 Load the context of the task.
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498 Need to restore the lower context by loading the CSA from
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499 pxCurrentTCB->pxTopOfStack into PCXI (effectively changing the call stack).
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500 In the Interrupt handler post-amble, RSLCX will restore the lower context
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501 of the task. RFE will restore the upper context of the task, jump to the
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502 return address and restore the previous state of interrupts being
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503 enabled/disabled. */
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506 xUpperCSA = _mfcr( $PCXI );
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507 pxUpperCSA = portCSA_TO_ADDRESS( xUpperCSA );
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508 *pxCurrentTCB = pxUpperCSA[ 0 ];
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509 vTaskSwitchContext();
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510 pxUpperCSA[ 0 ] = *pxCurrentTCB;
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511 CPU_SRC0.bits.SETR = 0;
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516 /* Unimplemented trap called. */
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517 configASSERT( ( ( volatile void * ) NULL ) );
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521 /*-----------------------------------------------------------*/
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523 static void prvInterruptYield( int iId )
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525 unsigned long *pxUpperCSA = NULL;
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526 unsigned long xUpperCSA = 0UL;
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527 extern volatile unsigned long *pxCurrentTCB;
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529 /* Just to remove compiler warnings. */
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532 /* Save the context of a task.
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533 The upper context is automatically saved when entering a trap or interrupt.
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534 Need to save the lower context as well and copy the PCXI CSA ID into
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535 pxCurrentTCB->pxTopOfStack. Only Lower Context CSA IDs may be saved to the
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538 Call vTaskSwitchContext to select the next task, note that this changes the
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539 value of pxCurrentTCB so that it needs to be reloaded.
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541 Call vPortSetMPURegisterSetOne to change the MPU mapping for the task
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542 that has just been switched in.
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544 Load the context of the task.
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545 Need to restore the lower context by loading the CSA from
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546 pxCurrentTCB->pxTopOfStack into PCXI (effectively changing the call stack).
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547 In the Interrupt handler post-amble, RSLCX will restore the lower context
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548 of the task. RFE will restore the upper context of the task, jump to the
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549 return address and restore the previous state of interrupts being
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550 enabled/disabled. */
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553 xUpperCSA = _mfcr( $PCXI );
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554 pxUpperCSA = portCSA_TO_ADDRESS( xUpperCSA );
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555 *pxCurrentTCB = pxUpperCSA[ 0 ];
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556 vTaskSwitchContext();
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557 pxUpperCSA[ 0 ] = *pxCurrentTCB;
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558 CPU_SRC0.bits.SETR = 0;
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561 /*-----------------------------------------------------------*/
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563 unsigned long uxPortSetInterruptMaskFromISR( void )
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565 unsigned long uxReturn = 0UL;
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568 uxReturn = _mfcr( $ICR );
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569 _mtcr( $ICR, ( ( uxReturn & ~portCCPN_MASK ) | configMAX_SYSCALL_INTERRUPT_PRIORITY ) );
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573 /* Return just the interrupt mask bits. */
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574 return ( uxReturn & portCCPN_MASK );
\r
576 /*-----------------------------------------------------------*/
\r