2 FreeRTOS V7.4.2 - Copyright (C) 2013 Real Time Engineers Ltd.
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4 FEATURES AND PORTS ARE ADDED TO FREERTOS ALL THE TIME. PLEASE VISIT
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5 http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
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7 ***************************************************************************
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9 * FreeRTOS tutorial books are available in pdf and paperback. *
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10 * Complete, revised, and edited pdf reference manuals are also *
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13 * Purchasing FreeRTOS documentation will not only help you, by *
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14 * ensuring you get running as quickly as possible and with an *
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15 * in-depth knowledge of how to use FreeRTOS, it will also help *
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16 * the FreeRTOS project to continue with its mission of providing *
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17 * professional grade, cross platform, de facto standard solutions *
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18 * for microcontrollers - completely free of charge! *
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20 * >>> See http://www.FreeRTOS.org/Documentation for details. <<< *
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22 * Thank you for using FreeRTOS, and thank you for your support! *
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24 ***************************************************************************
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27 This file is part of the FreeRTOS distribution.
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29 FreeRTOS is free software; you can redistribute it and/or modify it under
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30 the terms of the GNU General Public License (version 2) as published by the
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31 Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
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33 >>>>>>NOTE<<<<<< The modification to the GPL is included to allow you to
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34 distribute a combined work that includes FreeRTOS without being obliged to
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35 provide the source code for proprietary components outside of the FreeRTOS
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38 FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
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39 WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
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40 FOR A PARTICULAR PURPOSE. See the GNU General Public License for more
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41 details. You should have received a copy of the GNU General Public License
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42 and the FreeRTOS license exception along with FreeRTOS; if not it can be
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43 viewed here: http://www.freertos.org/a00114.html and also obtained by
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44 writing to Real Time Engineers Ltd., contact details for whom are available
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45 on the FreeRTOS WEB site.
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49 ***************************************************************************
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51 * Having a problem? Start by reading the FAQ "My application does *
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52 * not run, what could be wrong?" *
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54 * http://www.FreeRTOS.org/FAQHelp.html *
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56 ***************************************************************************
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59 http://www.FreeRTOS.org - Documentation, books, training, latest versions,
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60 license and Real Time Engineers Ltd. contact details.
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62 http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
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63 including FreeRTOS+Trace - an indispensable productivity tool, and our new
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64 fully thread aware and reentrant UDP/IP stack.
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66 http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High
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67 Integrity Systems, who sell the code with commercial support,
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68 indemnification and middleware, under the OpenRTOS brand.
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70 http://www.SafeRTOS.com - High Integrity Systems also provide a safety
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71 engineered and independently SIL3 certified version for use in safety and
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72 mission critical applications that require provable dependability.
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75 /* Standard includes. */
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79 /* TriCore specific includes. */
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81 #include <machine/intrinsics.h>
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82 #include <machine/cint.h>
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83 #include <machine/wdtcon.h>
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85 /* Kernel includes. */
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86 #include "FreeRTOS.h"
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90 #if configCHECK_FOR_STACK_OVERFLOW > 0
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91 #error "Stack checking cannot be used with this port, as, unlike most ports, the pxTopOfStack member of the TCB is consumed CSA. CSA starvation, loosely equivalent to stack overflow, will result in a trap exception."
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92 /* The stack pointer is accessible using portCSA_TO_ADDRESS( portCSA_TO_ADDRESS( pxCurrentTCB->pxTopOfStack )[ 0 ] )[ 2 ]; */
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93 #endif /* configCHECK_FOR_STACK_OVERFLOW */
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96 /*-----------------------------------------------------------*/
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98 /* System register Definitions. */
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99 #define portSYSTEM_PROGRAM_STATUS_WORD ( 0x000008FFUL ) /* Supervisor Mode, MPU Register Set 0 and Call Depth Counting disabled. */
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100 #define portINITIAL_PRIVILEGED_PROGRAM_STATUS_WORD ( 0x000014FFUL ) /* IO Level 1, MPU Register Set 1 and Call Depth Counting disabled. */
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101 #define portINITIAL_UNPRIVILEGED_PROGRAM_STATUS_WORD ( 0x000010FFUL ) /* IO Level 0, MPU Register Set 1 and Call Depth Counting disabled. */
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102 #define portINITIAL_PCXI_UPPER_CONTEXT_WORD ( 0x00C00000UL ) /* The lower 20 bits identify the CSA address. */
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103 #define portINITIAL_SYSCON ( 0x00000000UL ) /* MPU Disable. */
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105 /* CSA manipulation macros. */
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106 #define portCSA_FCX_MASK ( 0x000FFFFFUL )
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108 /* OS Interrupt and Trap mechanisms. */
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109 #define portRESTORE_PSW_MASK ( ~( 0x000000FFUL ) )
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110 #define portSYSCALL_TRAP ( 6 )
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112 /* Each CSA contains 16 words of data. */
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113 #define portNUM_WORDS_IN_CSA ( 16 )
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115 /* The interrupt enable bit in the PCP_SRC register. */
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116 #define portENABLE_CPU_INTERRUPT ( 1U << 12U )
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117 /*-----------------------------------------------------------*/
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120 * Perform any hardware configuration necessary to generate the tick interrupt.
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122 static void prvSystemTickHandler( int ) __attribute__((longcall));
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123 static void prvSetupTimerInterrupt( void );
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126 * Trap handler for yields.
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128 static void prvTrapYield( int iTrapIdentification );
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131 * Priority 1 interrupt handler for yields pended from an interrupt.
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133 static void prvInterruptYield( int iTrapIdentification );
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135 /*-----------------------------------------------------------*/
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137 /* This reference is required by the save/restore context macros. */
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138 extern volatile unsigned long *pxCurrentTCB;
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140 /* Precalculate the compare match value at compile time. */
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141 static const unsigned long ulCompareMatchValue = ( configPERIPHERAL_CLOCK_HZ / configTICK_RATE_HZ );
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143 /*-----------------------------------------------------------*/
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145 portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE * pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters )
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147 unsigned long *pulUpperCSA = NULL;
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148 unsigned long *pulLowerCSA = NULL;
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150 /* 16 Address Registers (4 Address registers are global), 16 Data
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151 Registers, and 3 System Registers.
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153 There are 3 registers that track the CSAs.
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154 FCX points to the head of globally free set of CSAs.
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155 PCX for the task needs to point to Lower->Upper->NULL arrangement.
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156 LCX points to the last free CSA so that corrective action can be taken.
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158 Need two CSAs to store the context of a task.
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159 The upper context contains D8-D15, A10-A15, PSW and PCXI->NULL.
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160 The lower context contains D0-D7, A2-A7, A11 and PCXI->UpperContext.
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161 The pxCurrentTCB->pxTopOfStack points to the Lower Context RSLCX matching the initial BISR.
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162 The Lower Context points to the Upper Context ready for the return from the interrupt handler.
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164 The Real stack pointer for the task is stored in the A10 which is restored
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165 with the upper context. */
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167 /* Have to disable interrupts here because the CSAs are going to be
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169 portENTER_CRITICAL();
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171 /* DSync to ensure that buffering is not a problem. */
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174 /* Consume two free CSAs. */
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175 pulLowerCSA = portCSA_TO_ADDRESS( _mfcr( $FCX ) );
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176 if( NULL != pulLowerCSA )
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178 /* The Lower Links to the Upper. */
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179 pulUpperCSA = portCSA_TO_ADDRESS( pulLowerCSA[ 0 ] );
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182 /* Check that we have successfully reserved two CSAs. */
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183 if( ( NULL != pulLowerCSA ) && ( NULL != pulUpperCSA ) )
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185 /* Remove the two consumed CSAs from the free CSA list. */
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188 _mtcr( $FCX, pulUpperCSA[ 0 ] );
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194 /* Simply trigger a context list depletion trap. */
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198 portEXIT_CRITICAL();
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200 /* Clear the upper CSA. */
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201 memset( pulUpperCSA, 0, portNUM_WORDS_IN_CSA * sizeof( unsigned long ) );
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203 /* Upper Context. */
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204 pulUpperCSA[ 2 ] = ( unsigned long )pxTopOfStack; /* A10; Stack Return aka Stack Pointer */
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205 pulUpperCSA[ 1 ] = portSYSTEM_PROGRAM_STATUS_WORD; /* PSW */
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207 /* Clear the lower CSA. */
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208 memset( pulLowerCSA, 0, portNUM_WORDS_IN_CSA * sizeof( unsigned long ) );
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210 /* Lower Context. */
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211 pulLowerCSA[ 8 ] = ( unsigned long ) pvParameters; /* A4; Address Type Parameter Register */
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212 pulLowerCSA[ 1 ] = ( unsigned long ) pxCode; /* A11; Return Address aka RA */
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214 /* PCXI pointing to the Upper context. */
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215 pulLowerCSA[ 0 ] = ( portINITIAL_PCXI_UPPER_CONTEXT_WORD | ( unsigned long ) portADDRESS_TO_CSA( pulUpperCSA ) );
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217 /* Save the link to the CSA in the top of stack. */
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218 pxTopOfStack = (unsigned long * ) portADDRESS_TO_CSA( pulLowerCSA );
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220 /* DSync to ensure that buffering is not a problem. */
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223 return pxTopOfStack;
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225 /*-----------------------------------------------------------*/
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227 long xPortStartScheduler( void )
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229 extern void vTrapInstallHandlers( void );
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230 unsigned long ulMFCR = 0UL;
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231 unsigned long *pulUpperCSA = NULL;
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232 unsigned long *pulLowerCSA = NULL;
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234 /* Interrupts at or below configMAX_SYSCALL_INTERRUPT_PRIORITY are disable
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235 when this function is called. */
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237 /* Set-up the timer interrupt. */
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238 prvSetupTimerInterrupt();
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240 /* Install the Trap Handlers. */
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241 vTrapInstallHandlers();
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243 /* Install the Syscall Handler for yield calls. */
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244 if( 0 == _install_trap_handler( portSYSCALL_TRAP, prvTrapYield ) )
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246 /* Failed to install the yield handler, force an assert. */
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247 configASSERT( ( ( volatile void * ) NULL ) );
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250 /* Enable then install the priority 1 interrupt for pending context
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251 switches from an ISR. See mod_SRC in the TriCore manual. */
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252 CPU_SRC0.reg = ( portENABLE_CPU_INTERRUPT ) | ( configKERNEL_YIELD_PRIORITY );
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253 if( 0 == _install_int_handler( configKERNEL_YIELD_PRIORITY, prvInterruptYield, 0 ) )
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255 /* Failed to install the yield handler, force an assert. */
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256 configASSERT( ( ( volatile void * ) NULL ) );
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261 /* Load the initial SYSCON. */
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262 _mtcr( $SYSCON, portINITIAL_SYSCON );
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265 /* ENDINIT has already been applied in the 'cstart.c' code. */
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267 /* Clear the PSW.CDC to enable the use of an RFE without it generating an
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268 exception because this code is not genuinely in an exception. */
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269 ulMFCR = _mfcr( $PSW );
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270 ulMFCR &= portRESTORE_PSW_MASK;
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272 _mtcr( $PSW, ulMFCR );
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275 /* Finally, perform the equivalent of a portRESTORE_CONTEXT() */
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276 pulLowerCSA = portCSA_TO_ADDRESS( ( *pxCurrentTCB ) );
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277 pulUpperCSA = portCSA_TO_ADDRESS( pulLowerCSA[0] );
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279 _mtcr( $PCXI, *pxCurrentTCB );
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285 /* Return to the first task selected to execute. */
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286 __asm volatile( "rfe" );
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288 /* Will not get here. */
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291 /*-----------------------------------------------------------*/
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293 static void prvSetupTimerInterrupt( void )
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295 /* Set-up the clock divider. */
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298 /* Wait until access to Endint protected register is enabled. */
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299 while( 0 != ( WDT_CON0.reg & 0x1UL ) );
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301 /* RMC == 1 so STM Clock == FPI */
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302 STM_CLC.reg = ( 1UL << 8 );
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306 /* Determine how many bits are used without changing other bits in the CMCON register. */
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307 STM_CMCON.reg &= ~( 0x1fUL );
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308 STM_CMCON.reg |= ( 0x1fUL - __CLZ( configPERIPHERAL_CLOCK_HZ / configTICK_RATE_HZ ) );
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310 /* Take into account the current time so a tick doesn't happen immediately. */
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311 STM_CMP0.reg = ulCompareMatchValue + STM_TIM0.reg;
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313 if( 0 != _install_int_handler( configKERNEL_INTERRUPT_PRIORITY, prvSystemTickHandler, 0 ) )
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315 /* Set-up the interrupt. */
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316 STM_SRC0.reg = ( configKERNEL_INTERRUPT_PRIORITY | 0x00005000UL );
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318 /* Enable the Interrupt. */
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319 STM_ISRR.reg &= ~( 0x03UL );
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320 STM_ISRR.reg |= 0x1UL;
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321 STM_ISRR.reg &= ~( 0x07UL );
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322 STM_ICR.reg |= 0x1UL;
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326 /* Failed to install the Tick Interrupt. */
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327 configASSERT( ( ( volatile void * ) NULL ) );
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330 /*-----------------------------------------------------------*/
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332 static void prvSystemTickHandler( int iArg )
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334 unsigned long ulSavedInterruptMask;
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335 unsigned long *pxUpperCSA = NULL;
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336 unsigned long xUpperCSA = 0UL;
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337 extern volatile unsigned long *pxCurrentTCB;
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338 long lYieldRequired;
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340 /* Just to avoid compiler warnings about unused parameters. */
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343 /* Clear the interrupt source. */
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344 STM_ISRR.reg = 1UL;
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346 /* Reload the Compare Match register for X ticks into the future.
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348 If critical section or interrupt nesting budgets are exceeded, then
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349 it is possible that the calculated next compare match value is in the
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350 past. If this occurs (unlikely), it is possible that the resulting
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351 time slippage will exceed a single tick period. Any adverse effect of
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352 this is time bounded by the fact that only the first n bits of the 56 bit
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353 STM timer are being used for a compare match, so another compare match
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354 will occur after an overflow in just those n bits (not the entire 56 bits).
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355 As an example, if the peripheral clock is 75MHz, and the tick rate is 1KHz,
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356 a missed tick could result in the next tick interrupt occurring within a
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357 time that is 1.7 times the desired period. The fact that this is greater
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358 than a single tick period is an effect of using a timer that cannot be
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359 automatically reset, in hardware, by the occurrence of a tick interrupt.
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360 Changing the tick source to a timer that has an automatic reset on compare
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361 match (such as a GPTA timer) will reduce the maximum possible additional
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362 period to exactly 1 times the desired period. */
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363 STM_CMP0.reg += ulCompareMatchValue;
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365 /* Kernel API calls require Critical Sections. */
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366 ulSavedInterruptMask = portSET_INTERRUPT_MASK_FROM_ISR();
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368 /* Increment the Tick. */
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369 lYieldRequired = xTaskIncrementTick();
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371 portCLEAR_INTERRUPT_MASK_FROM_ISR( ulSavedInterruptMask );
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373 if( lYieldRequired != pdFALSE )
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375 /* Save the context of a task.
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376 The upper context is automatically saved when entering a trap or interrupt.
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377 Need to save the lower context as well and copy the PCXI CSA ID into
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378 pxCurrentTCB->pxTopOfStack. Only Lower Context CSA IDs may be saved to the
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381 Call vTaskSwitchContext to select the next task, note that this changes the
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382 value of pxCurrentTCB so that it needs to be reloaded.
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384 Call vPortSetMPURegisterSetOne to change the MPU mapping for the task
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385 that has just been switched in.
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387 Load the context of the task.
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388 Need to restore the lower context by loading the CSA from
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389 pxCurrentTCB->pxTopOfStack into PCXI (effectively changing the call stack).
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390 In the Interrupt handler post-amble, RSLCX will restore the lower context
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391 of the task. RFE will restore the upper context of the task, jump to the
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392 return address and restore the previous state of interrupts being
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393 enabled/disabled. */
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396 xUpperCSA = _mfcr( $PCXI );
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397 pxUpperCSA = portCSA_TO_ADDRESS( xUpperCSA );
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398 *pxCurrentTCB = pxUpperCSA[ 0 ];
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399 vTaskSwitchContext();
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400 pxUpperCSA[ 0 ] = *pxCurrentTCB;
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401 CPU_SRC0.bits.SETR = 0;
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405 /*-----------------------------------------------------------*/
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408 * When a task is deleted, it is yielded permanently until the IDLE task
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409 * has an opportunity to reclaim the memory that that task was using.
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410 * Typically, the memory used by a task is the TCB and Stack but in the
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411 * TriCore this includes the CSAs that were consumed as part of the Call
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412 * Stack. These CSAs can only be returned to the Globally Free Pool when
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413 * they are not part of the current Call Stack, hence, delaying the
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414 * reclamation until the IDLE task is freeing the task's other resources.
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415 * This function uses the head of the linked list of CSAs (from when the
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416 * task yielded for the last time) and finds the tail (the very bottom of
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417 * the call stack) and inserts this list at the head of the Free list,
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418 * attaching the existing Free List to the tail of the reclaimed call stack.
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420 * NOTE: the IDLE task needs processing time to complete this function
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421 * and in heavily loaded systems, the Free CSAs may be consumed faster
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422 * than they can be freed assuming that tasks are being spawned and
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423 * deleted frequently.
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425 void vPortReclaimCSA( unsigned long *pxTCB )
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427 unsigned long pxHeadCSA, pxTailCSA, pxFreeCSA;
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428 unsigned long *pulNextCSA;
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430 /* A pointer to the first CSA in the list of CSAs consumed by the task is
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431 stored in the first element of the tasks TCB structure (where the stack
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432 pointer would be on a traditional stack based architecture). */
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433 pxHeadCSA = ( *pxTCB ) & portCSA_FCX_MASK;
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435 /* Mask off everything in the CSA link field other than the address. If
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436 the address is NULL, then the CSA is not linking anywhere and there is
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438 pxTailCSA = pxHeadCSA;
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440 /* Convert the link value to contain just a raw address and store this
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441 in a local variable. */
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442 pulNextCSA = portCSA_TO_ADDRESS( pxTailCSA );
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444 /* Iterate over the CSAs that were consumed as part of the task. The
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445 first field in the CSA is the pointer to then next CSA. Mask off
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446 everything in the pointer to the next CSA, other than the link address.
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447 If this is NULL, then the CSA currently being pointed to is the last in
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449 while( 0UL != ( pulNextCSA[ 0 ] & portCSA_FCX_MASK ) )
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451 /* Clear all bits of the pointer to the next in the chain, other
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452 than the address bits themselves. */
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453 pulNextCSA[ 0 ] = pulNextCSA[ 0 ] & portCSA_FCX_MASK;
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455 /* Move the pointer to point to the next CSA in the list. */
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456 pxTailCSA = pulNextCSA[ 0 ];
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458 /* Update the local pointer to the CSA. */
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459 pulNextCSA = portCSA_TO_ADDRESS( pxTailCSA );
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464 /* Look up the current free CSA head. */
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466 pxFreeCSA = _mfcr( $FCX );
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468 /* Join the current Free onto the Tail of what is being reclaimed. */
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469 portCSA_TO_ADDRESS( pxTailCSA )[ 0 ] = pxFreeCSA;
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471 /* Move the head of the reclaimed into the Free. */
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473 _mtcr( $FCX, pxHeadCSA );
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478 /*-----------------------------------------------------------*/
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480 void vPortEndScheduler( void )
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482 /* Nothing to do. Unlikely to want to end. */
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484 /*-----------------------------------------------------------*/
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486 static void prvTrapYield( int iTrapIdentification )
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488 unsigned long *pxUpperCSA = NULL;
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489 unsigned long xUpperCSA = 0UL;
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490 extern volatile unsigned long *pxCurrentTCB;
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492 switch( iTrapIdentification )
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494 case portSYSCALL_TASK_YIELD:
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495 /* Save the context of a task.
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496 The upper context is automatically saved when entering a trap or interrupt.
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497 Need to save the lower context as well and copy the PCXI CSA ID into
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498 pxCurrentTCB->pxTopOfStack. Only Lower Context CSA IDs may be saved to the
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501 Call vTaskSwitchContext to select the next task, note that this changes the
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502 value of pxCurrentTCB so that it needs to be reloaded.
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504 Call vPortSetMPURegisterSetOne to change the MPU mapping for the task
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505 that has just been switched in.
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507 Load the context of the task.
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508 Need to restore the lower context by loading the CSA from
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509 pxCurrentTCB->pxTopOfStack into PCXI (effectively changing the call stack).
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510 In the Interrupt handler post-amble, RSLCX will restore the lower context
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511 of the task. RFE will restore the upper context of the task, jump to the
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512 return address and restore the previous state of interrupts being
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513 enabled/disabled. */
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516 xUpperCSA = _mfcr( $PCXI );
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517 pxUpperCSA = portCSA_TO_ADDRESS( xUpperCSA );
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518 *pxCurrentTCB = pxUpperCSA[ 0 ];
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519 vTaskSwitchContext();
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520 pxUpperCSA[ 0 ] = *pxCurrentTCB;
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521 CPU_SRC0.bits.SETR = 0;
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526 /* Unimplemented trap called. */
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527 configASSERT( ( ( volatile void * ) NULL ) );
\r
531 /*-----------------------------------------------------------*/
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533 static void prvInterruptYield( int iId )
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535 unsigned long *pxUpperCSA = NULL;
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536 unsigned long xUpperCSA = 0UL;
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537 extern volatile unsigned long *pxCurrentTCB;
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539 /* Just to remove compiler warnings. */
\r
542 /* Save the context of a task.
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543 The upper context is automatically saved when entering a trap or interrupt.
\r
544 Need to save the lower context as well and copy the PCXI CSA ID into
\r
545 pxCurrentTCB->pxTopOfStack. Only Lower Context CSA IDs may be saved to the
\r
548 Call vTaskSwitchContext to select the next task, note that this changes the
\r
549 value of pxCurrentTCB so that it needs to be reloaded.
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551 Call vPortSetMPURegisterSetOne to change the MPU mapping for the task
\r
552 that has just been switched in.
\r
554 Load the context of the task.
\r
555 Need to restore the lower context by loading the CSA from
\r
556 pxCurrentTCB->pxTopOfStack into PCXI (effectively changing the call stack).
\r
557 In the Interrupt handler post-amble, RSLCX will restore the lower context
\r
558 of the task. RFE will restore the upper context of the task, jump to the
\r
559 return address and restore the previous state of interrupts being
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560 enabled/disabled. */
\r
563 xUpperCSA = _mfcr( $PCXI );
\r
564 pxUpperCSA = portCSA_TO_ADDRESS( xUpperCSA );
\r
565 *pxCurrentTCB = pxUpperCSA[ 0 ];
\r
566 vTaskSwitchContext();
\r
567 pxUpperCSA[ 0 ] = *pxCurrentTCB;
\r
568 CPU_SRC0.bits.SETR = 0;
\r
571 /*-----------------------------------------------------------*/
\r
573 unsigned long uxPortSetInterruptMaskFromISR( void )
\r
575 unsigned long uxReturn = 0UL;
\r
578 uxReturn = _mfcr( $ICR );
\r
579 _mtcr( $ICR, ( ( uxReturn & ~portCCPN_MASK ) | configMAX_SYSCALL_INTERRUPT_PRIORITY ) );
\r
583 /* Return just the interrupt mask bits. */
\r
584 return ( uxReturn & portCCPN_MASK );
\r
586 /*-----------------------------------------------------------*/
\r