git.sur5r.net Git - freertos/blob - FreeRTOS/Source/portable/GCC/TriCore_1782/porttrap.c

   1 /*\r
   2  * FreeRTOS Kernel V10.0.0\r
   3  * Copyright (C) 2017 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\r
   4  *\r
   5  * Permission is hereby granted, free of charge, to any person obtaining a copy of\r
   6  * this software and associated documentation files (the "Software"), to deal in\r
   7  * the Software without restriction, including without limitation the rights to\r
   8  * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\r
   9  * the Software, and to permit persons to whom the Software is furnished to do so,\r
  10  * subject to the following conditions:\r
  11  *\r
  12  * The above copyright notice and this permission notice shall be included in all\r
  13  * copies or substantial portions of the Software. If you wish to use our Amazon\r
  14  * FreeRTOS name, please do so in a fair use way that does not cause confusion.\r
  15  *\r
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\r
  18  * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\r
  19  * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r
  20  * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
  21  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
  22  *\r
  23  * http://www.FreeRTOS.org\r
  24  * http://aws.amazon.com/freertos\r
  25  *\r
  26  * 1 tab == 4 spaces!\r
  27  */\r
  28 \r
  29 /* Kernel includes. */\r
  30 #include "FreeRTOS.h"\r
  31 \r
  32 /* Machine includes */\r
  33 #include <tc1782.h>\r
  34 #include <machine/intrinsics.h>\r
  35 #include <machine/cint.h>\r
  36 /*---------------------------------------------------------------------------*/\r
  37 \r
  38 /*\r
  39  * This reference is required by the Save/Restore Context Macros.\r
  40  */\r
  41 extern volatile uint32_t *pxCurrentTCB;\r
  42 /*-----------------------------------------------------------*/\r
  43 \r
  44 /*\r
  45  * This file contains base definitions for all of the possible traps in the system.\r
  46  * It is suggested to provide implementations for all of the traps but for\r
  47  * the time being they simply trigger a DEBUG instruction so that it is easy\r
  48  * to see what caused a particular trap.\r
  49  *\r
  50  * Trap Class 6, the SYSCALL, is used exclusively by the operating system.\r
  51  */\r
  52 \r
  53 /* The Trap Classes. */\r
  54 #define portMMU_TRAP                                                                            0\r
  55 #define portIPT_TRAP                                                                            1\r
  56 #define portIE_TRAP                                                                                     2\r
  57 #define portCM_TRAP                                                                                     3\r
  58 #define portSBP_TRAP                                                                            4\r
  59 #define portASSERT_TRAP                                                                         5\r
  60 #define portNMI_TRAP                                                                            7\r
  61 \r
  62 /* MMU Trap Identifications. */\r
  63 #define portTIN_MMU_VIRTUAL_ADDRESS_FILL                                        0\r
  64 #define portTIN_MMU_VIRTUAL_ADDRESS_PROTECTION                          1\r
  65 \r
  66 /* Internal Protection Trap Identifications. */\r
  67 #define portTIN_IPT_PRIVILIGED_INSTRUCTION                                      1\r
  68 #define portTIN_IPT_MEMORY_PROTECTION_READ                                      2\r
  69 #define portTIN_IPT_MEMORY_PROTECTION_WRITE                                     3\r
  70 #define portTIN_IPT_MEMORY_PROTECTION_EXECUTION                         4\r
  71 #define portTIN_IPT_MEMORY_PROTECTION_PERIPHERAL_ACCESS         5\r
  72 #define portTIN_IPT_MEMORY_PROTECTION_NULL_ADDRESS                      6\r
  73 #define portTIN_IPT_MEMORY_PROTECTION_GLOBAL_REGISTER_WRITE_PROTECTION  7\r
  74 \r
  75 /* Instruction Error Trap Identifications. */\r
  76 #define portTIN_IE_ILLEGAL_OPCODE                                                       1\r
  77 #define portTIN_IE_UNIMPLEMENTED_OPCODE                                         2\r
  78 #define portTIN_IE_INVALID_OPERAND                                                      3\r
  79 #define portTIN_IE_DATA_ADDRESS_ALIGNMENT                                       4\r
  80 #define portTIN_IE_INVALID_LOCAL_MEMORY_ADDRESS                         5\r
  81 \r
  82 /* Context Management Trap Identifications. */\r
  83 #define portTIN_CM_FREE_CONTEXT_LIST_DEPLETION                          1\r
  84 #define portTIN_CM_CALL_DEPTH_OVERFLOW                                          2\r
  85 #define portTIN_CM_CALL_DEPTH_UNDEFLOW                                          3\r
  86 #define portTIN_CM_FREE_CONTEXT_LIST_UNDERFLOW                          4\r
  87 #define portTIN_CM_CALL_STACK_UNDERFLOW                                         5\r
  88 #define portTIN_CM_CONTEXT_TYPE                                                         6\r
  89 #define portTIN_CM_NESTING_ERROR                                                        7\r
  90 \r
  91 /* System Bus and Peripherals Trap Identifications. */\r
  92 #define portTIN_SBP_PROGRAM_FETCH_SYNCHRONOUS_ERROR                     1\r
  93 #define portTIN_SBP_DATA_ACCESS_SYNCHRONOUS_ERROR                       2\r
  94 #define portTIN_SBP_DATA_ACCESS_ASYNCHRONOUS_ERROR                      3\r
  95 #define portTIN_SBP_COPROCESSOR_TRAP_ASYNCHRONOUS_ERROR         4\r
  96 #define portTIN_SBP_PROGRAM_MEMORY_INTEGRITY_ERROR                      5\r
  97 #define portTIN_SBP_DATA_MEMORY_INTEGRITY_ERROR                         6\r
  98 \r
  99 /* Assertion Trap Identifications. */\r
 100 #define portTIN_ASSERT_ARITHMETIC_OVERFLOW                                      1\r
 101 #define portTIN_ASSERT_STICKY_ARITHMETIC_OVERFLOW                       2\r
 102 \r
 103 /* Non-maskable Interrupt Trap Identifications. */\r
 104 #define portTIN_NMI_NON_MASKABLE_INTERRUPT                                      0\r
 105 /*---------------------------------------------------------------------------*/\r
 106 \r
 107 void vMMUTrap( int iTrapIdentification ) __attribute__( ( longcall, weak ) );\r
 108 void vInternalProtectionTrap( int iTrapIdentification ) __attribute__( ( longcall, weak ) );\r
 109 void vInstructionErrorTrap( int iTrapIdentification ) __attribute__( ( longcall, weak ) );\r
 110 void vContextManagementTrap( int iTrapIdentification ) __attribute__( ( longcall, weak ) );\r
 111 void vSystemBusAndPeripheralsTrap( int iTrapIdentification ) __attribute__( ( longcall, weak ) );\r
 112 void vAssertionTrap( int iTrapIdentification ) __attribute__( ( longcall, weak ) );\r
 113 void vNonMaskableInterruptTrap( int iTrapIdentification ) __attribute__( ( longcall, weak ) );\r
 114 /*---------------------------------------------------------------------------*/\r
 115 \r
 116 void vTrapInstallHandlers( void )\r
 117 {\r
 118         if( 0 == _install_trap_handler ( portMMU_TRAP, vMMUTrap ) )\r
 119         {\r
 120                 _debug();\r
 121         }\r
 122 \r
 123         if( 0 == _install_trap_handler ( portIPT_TRAP, vInternalProtectionTrap ) )\r
 124         {\r
 125                 _debug();\r
 126         }\r
 127 \r
 128         if( 0 == _install_trap_handler ( portIE_TRAP, vInstructionErrorTrap ) )\r
 129         {\r
 130                 _debug();\r
 131         }\r
 132 \r
 133         if( 0 == _install_trap_handler ( portCM_TRAP, vContextManagementTrap ) )\r
 134         {\r
 135                 _debug();\r
 136         }\r
 137 \r
 138         if( 0 == _install_trap_handler ( portSBP_TRAP, vSystemBusAndPeripheralsTrap ) )\r
 139         {\r
 140                 _debug();\r
 141         }\r
 142 \r
 143         if( 0 == _install_trap_handler ( portASSERT_TRAP, vAssertionTrap ) )\r
 144         {\r
 145                 _debug();\r
 146         }\r
 147 \r
 148         if( 0 == _install_trap_handler ( portNMI_TRAP, vNonMaskableInterruptTrap ) )\r
 149         {\r
 150                 _debug();\r
 151         }\r
 152 }\r
 153 /*-----------------------------------------------------------*/\r
 154 \r
 155 void vMMUTrap( int iTrapIdentification )\r
 156 {\r
 157         switch( iTrapIdentification )\r
 158         {\r
 159         case portTIN_MMU_VIRTUAL_ADDRESS_FILL:\r
 160         case portTIN_MMU_VIRTUAL_ADDRESS_PROTECTION:\r
 161         default:\r
 162                 _debug();\r
 163                 break;\r
 164         }\r
 165 }\r
 166 /*---------------------------------------------------------------------------*/\r
 167 \r
 168 void vInternalProtectionTrap( int iTrapIdentification )\r
 169 {\r
 170         /* Deliberate fall through to default. */\r
 171         switch( iTrapIdentification )\r
 172         {\r
 173                 case portTIN_IPT_PRIVILIGED_INSTRUCTION:\r
 174                         /* Instruction is not allowed at current execution level, eg DISABLE at User-0. */\r
 175 \r
 176                 case portTIN_IPT_MEMORY_PROTECTION_READ:\r
 177                         /* Load word using invalid address. */\r
 178                         \r
 179                 case portTIN_IPT_MEMORY_PROTECTION_WRITE:\r
 180                         /* Store Word using invalid address. */\r
 181                         \r
 182                 case portTIN_IPT_MEMORY_PROTECTION_EXECUTION:\r
 183                         /* PC jumped to an address outside of the valid range. */\r
 184                         \r
 185                 case portTIN_IPT_MEMORY_PROTECTION_PERIPHERAL_ACCESS:\r
 186                         /* Access to a peripheral denied at current execution level. */\r
 187                         \r
 188                 case portTIN_IPT_MEMORY_PROTECTION_NULL_ADDRESS:\r
 189                         /* NULL Pointer. */\r
 190                         \r
 191                 case portTIN_IPT_MEMORY_PROTECTION_GLOBAL_REGISTER_WRITE_PROTECTION:\r
 192                         /* Tried to modify a global address pointer register. */\r
 193                         \r
 194                 default:\r
 195                 \r
 196                         pxCurrentTCB[ 0 ] = __MFCR( $PCXI );\r
 197                         _debug();\r
 198                         break;\r
 199         }\r
 200 }\r
 201 /*---------------------------------------------------------------------------*/\r
 202 \r
 203 void vInstructionErrorTrap( int iTrapIdentification )\r
 204 {\r
 205         /* Deliberate fall through to default. */\r
 206         switch( iTrapIdentification )\r
 207         {\r
 208                 case portTIN_IE_ILLEGAL_OPCODE:\r
 209                 case portTIN_IE_UNIMPLEMENTED_OPCODE:\r
 210                 case portTIN_IE_INVALID_OPERAND:\r
 211                 case portTIN_IE_DATA_ADDRESS_ALIGNMENT:\r
 212                 case portTIN_IE_INVALID_LOCAL_MEMORY_ADDRESS:\r
 213                 default:\r
 214                         _debug();\r
 215                         break;\r
 216         }\r
 217 }\r
 218 /*---------------------------------------------------------------------------*/\r
 219 \r
 220 void vContextManagementTrap( int iTrapIdentification )\r
 221 {\r
 222         /* Deliberate fall through to default. */\r
 223         switch( iTrapIdentification )\r
 224         {\r
 225                 case portTIN_CM_FREE_CONTEXT_LIST_DEPLETION:\r
 226                 case portTIN_CM_CALL_DEPTH_OVERFLOW:\r
 227                 case portTIN_CM_CALL_DEPTH_UNDEFLOW:\r
 228                 case portTIN_CM_FREE_CONTEXT_LIST_UNDERFLOW:\r
 229                 case portTIN_CM_CALL_STACK_UNDERFLOW:\r
 230                 case portTIN_CM_CONTEXT_TYPE:\r
 231                 case portTIN_CM_NESTING_ERROR:\r
 232                 default:\r
 233                         _debug();\r
 234                         break;\r
 235         }\r
 236 }\r
 237 /*---------------------------------------------------------------------------*/\r
 238 \r
 239 void vSystemBusAndPeripheralsTrap( int iTrapIdentification )\r
 240 {\r
 241         /* Deliberate fall through to default. */\r
 242         switch( iTrapIdentification )\r
 243         {\r
 244                 case portTIN_SBP_PROGRAM_FETCH_SYNCHRONOUS_ERROR:\r
 245                 case portTIN_SBP_DATA_ACCESS_SYNCHRONOUS_ERROR:\r
 246                 case portTIN_SBP_DATA_ACCESS_ASYNCHRONOUS_ERROR:\r
 247                 case portTIN_SBP_COPROCESSOR_TRAP_ASYNCHRONOUS_ERROR:\r
 248                 case portTIN_SBP_PROGRAM_MEMORY_INTEGRITY_ERROR:\r
 249                 case portTIN_SBP_DATA_MEMORY_INTEGRITY_ERROR:\r
 250                 default:\r
 251                         _debug();\r
 252                         break;\r
 253         }\r
 254 }\r
 255 /*---------------------------------------------------------------------------*/\r
 256 \r
 257 void vAssertionTrap( int iTrapIdentification )\r
 258 {\r
 259         /* Deliberate fall through to default. */\r
 260         switch( iTrapIdentification )\r
 261         {\r
 262                 case portTIN_ASSERT_ARITHMETIC_OVERFLOW:\r
 263                 case portTIN_ASSERT_STICKY_ARITHMETIC_OVERFLOW:\r
 264                 default:\r
 265                         _debug();\r
 266                         break;\r
 267         }\r
 268 }\r
 269 /*---------------------------------------------------------------------------*/\r
 270 \r
 271 void vNonMaskableInterruptTrap( int iTrapIdentification )\r
 272 {\r
 273         /* Deliberate fall through to default. */\r
 274         switch( iTrapIdentification )\r
 275         {\r
 276                 case portTIN_NMI_NON_MASKABLE_INTERRUPT:\r
 277                 default:\r
 278                         _debug();\r
 279                         break;\r
 280         }\r
 281 }\r
 282 /*---------------------------------------------------------------------------*/\r