git.sur5r.net Git - freertos/blob - FreeRTOS/Source/portable/GCC/TriCore_1782/porttrap.c

   1 /*\r
   2     FreeRTOS V7.5.3 - Copyright (C) 2013 Real Time Engineers Ltd. \r
   3     All rights reserved\r
   4 \r
   5     VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
   6 \r
   7     ***************************************************************************\r
   8      *                                                                       *\r
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  11      *    platform software that has become a de facto standard.             *\r
  12      *                                                                       *\r
  13      *    Help yourself get started quickly and support the FreeRTOS         *\r
  14      *    project by purchasing a FreeRTOS tutorial book, reference          *\r
  15      *    manual, or both from: http://www.FreeRTOS.org/Documentation        *\r
  16      *                                                                       *\r
  17      *    Thank you!                                                         *\r
  18      *                                                                       *\r
  19     ***************************************************************************\r
  20 \r
  21     This file is part of the FreeRTOS distribution.\r
  22 \r
  23     FreeRTOS is free software; you can redistribute it and/or modify it under\r
  24     the terms of the GNU General Public License (version 2) as published by the\r
  25     Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.\r
  26 \r
  27     >>! NOTE: The modification to the GPL is included to allow you to distribute\r
  28     >>! a combined work that includes FreeRTOS without being obliged to provide\r
  29     >>! the source code for proprietary components outside of the FreeRTOS\r
  30     >>! kernel.\r
  31 \r
  32     FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
  33     WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
  34     FOR A PARTICULAR PURPOSE.  Full license text is available from the following\r
  35     link: http://www.freertos.org/a00114.html\r
  36 \r
  37     1 tab == 4 spaces!\r
  38 \r
  39     ***************************************************************************\r
  40      *                                                                       *\r
  41      *    Having a problem?  Start by reading the FAQ "My application does   *\r
  42      *    not run, what could be wrong?"                                     *\r
  43      *                                                                       *\r
  44      *    http://www.FreeRTOS.org/FAQHelp.html                               *\r
  45      *                                                                       *\r
  46     ***************************************************************************\r
  47 \r
  48     http://www.FreeRTOS.org - Documentation, books, training, latest versions,\r
  49     license and Real Time Engineers Ltd. contact details.\r
  50 \r
  51     http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
  52     including FreeRTOS+Trace - an indispensable productivity tool, a DOS\r
  53     compatible FAT file system, and our tiny thread aware UDP/IP stack.\r
  54 \r
  55     http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High\r
  56     Integrity Systems to sell under the OpenRTOS brand.  Low cost OpenRTOS\r
  57     licenses offer ticketed support, indemnification and middleware.\r
  58 \r
  59     http://www.SafeRTOS.com - High Integrity Systems also provide a safety\r
  60     engineered and independently SIL3 certified version for use in safety and\r
  61     mission critical applications that require provable dependability.\r
  62 \r
  63     1 tab == 4 spaces!\r
  64 */\r
  65 \r
  66 /* Kernel includes. */\r
  67 #include "FreeRTOS.h"\r
  68 \r
  69 /* Machine includes */\r
  70 #include <tc1782.h>\r
  71 #include <machine/intrinsics.h>\r
  72 #include <machine/cint.h>\r
  73 /*---------------------------------------------------------------------------*/\r
  74 \r
  75 /*\r
  76  * This reference is required by the Save/Restore Context Macros.\r
  77  */\r
  78 extern volatile unsigned long *pxCurrentTCB;\r
  79 /*-----------------------------------------------------------*/\r
  80 \r
  81 /*\r
  82  * This file contains base definitions for all of the possible traps in the system.\r
  83  * It is suggested to provide implementations for all of the traps but for\r
  84  * the time being they simply trigger a DEBUG instruction so that it is easy\r
  85  * to see what caused a particular trap.\r
  86  *\r
  87  * Trap Class 6, the SYSCALL, is used exclusively by the operating system.\r
  88  */\r
  89 \r
  90 /* The Trap Classes. */\r
  91 #define portMMU_TRAP                                                                            0\r
  92 #define portIPT_TRAP                                                                            1\r
  93 #define portIE_TRAP                                                                                     2\r
  94 #define portCM_TRAP                                                                                     3\r
  95 #define portSBP_TRAP                                                                            4\r
  96 #define portASSERT_TRAP                                                                         5\r
  97 #define portNMI_TRAP                                                                            7\r
  98 \r
  99 /* MMU Trap Identifications. */\r
 100 #define portTIN_MMU_VIRTUAL_ADDRESS_FILL                                        0\r
 101 #define portTIN_MMU_VIRTUAL_ADDRESS_PROTECTION                          1\r
 102 \r
 103 /* Internal Protection Trap Identifications. */\r
 104 #define portTIN_IPT_PRIVILIGED_INSTRUCTION                                      1\r
 105 #define portTIN_IPT_MEMORY_PROTECTION_READ                                      2\r
 106 #define portTIN_IPT_MEMORY_PROTECTION_WRITE                                     3\r
 107 #define portTIN_IPT_MEMORY_PROTECTION_EXECUTION                         4\r
 108 #define portTIN_IPT_MEMORY_PROTECTION_PERIPHERAL_ACCESS         5\r
 109 #define portTIN_IPT_MEMORY_PROTECTION_NULL_ADDRESS                      6\r
 110 #define portTIN_IPT_MEMORY_PROTECTION_GLOBAL_REGISTER_WRITE_PROTECTION  7\r
 111 \r
 112 /* Instruction Error Trap Identifications. */\r
 113 #define portTIN_IE_ILLEGAL_OPCODE                                                       1\r
 114 #define portTIN_IE_UNIMPLEMENTED_OPCODE                                         2\r
 115 #define portTIN_IE_INVALID_OPERAND                                                      3\r
 116 #define portTIN_IE_DATA_ADDRESS_ALIGNMENT                                       4\r
 117 #define portTIN_IE_INVALID_LOCAL_MEMORY_ADDRESS                         5\r
 118 \r
 119 /* Context Management Trap Identifications. */\r
 120 #define portTIN_CM_FREE_CONTEXT_LIST_DEPLETION                          1\r
 121 #define portTIN_CM_CALL_DEPTH_OVERFLOW                                          2\r
 122 #define portTIN_CM_CALL_DEPTH_UNDEFLOW                                          3\r
 123 #define portTIN_CM_FREE_CONTEXT_LIST_UNDERFLOW                          4\r
 124 #define portTIN_CM_CALL_STACK_UNDERFLOW                                         5\r
 125 #define portTIN_CM_CONTEXT_TYPE                                                         6\r
 126 #define portTIN_CM_NESTING_ERROR                                                        7\r
 127 \r
 128 /* System Bus and Peripherals Trap Identifications. */\r
 129 #define portTIN_SBP_PROGRAM_FETCH_SYNCHRONOUS_ERROR                     1\r
 130 #define portTIN_SBP_DATA_ACCESS_SYNCHRONOUS_ERROR                       2\r
 131 #define portTIN_SBP_DATA_ACCESS_ASYNCHRONOUS_ERROR                      3\r
 132 #define portTIN_SBP_COPROCESSOR_TRAP_ASYNCHRONOUS_ERROR         4\r
 133 #define portTIN_SBP_PROGRAM_MEMORY_INTEGRITY_ERROR                      5\r
 134 #define portTIN_SBP_DATA_MEMORY_INTEGRITY_ERROR                         6\r
 135 \r
 136 /* Assertion Trap Identifications. */\r
 137 #define portTIN_ASSERT_ARITHMETIC_OVERFLOW                                      1\r
 138 #define portTIN_ASSERT_STICKY_ARITHMETIC_OVERFLOW                       2\r
 139 \r
 140 /* Non-maskable Interrupt Trap Identifications. */\r
 141 #define portTIN_NMI_NON_MASKABLE_INTERRUPT                                      0\r
 142 /*---------------------------------------------------------------------------*/\r
 143 \r
 144 void vMMUTrap( int iTrapIdentification ) __attribute__( ( longcall, weak ) );\r
 145 void vInternalProtectionTrap( int iTrapIdentification ) __attribute__( ( longcall, weak ) );\r
 146 void vInstructionErrorTrap( int iTrapIdentification ) __attribute__( ( longcall, weak ) );\r
 147 void vContextManagementTrap( int iTrapIdentification ) __attribute__( ( longcall, weak ) );\r
 148 void vSystemBusAndPeripheralsTrap( int iTrapIdentification ) __attribute__( ( longcall, weak ) );\r
 149 void vAssertionTrap( int iTrapIdentification ) __attribute__( ( longcall, weak ) );\r
 150 void vNonMaskableInterruptTrap( int iTrapIdentification ) __attribute__( ( longcall, weak ) );\r
 151 /*---------------------------------------------------------------------------*/\r
 152 \r
 153 void vTrapInstallHandlers( void )\r
 154 {\r
 155         if( 0 == _install_trap_handler ( portMMU_TRAP, vMMUTrap ) )\r
 156         {\r
 157                 _debug();\r
 158         }\r
 159 \r
 160         if( 0 == _install_trap_handler ( portIPT_TRAP, vInternalProtectionTrap ) )\r
 161         {\r
 162                 _debug();\r
 163         }\r
 164 \r
 165         if( 0 == _install_trap_handler ( portIE_TRAP, vInstructionErrorTrap ) )\r
 166         {\r
 167                 _debug();\r
 168         }\r
 169 \r
 170         if( 0 == _install_trap_handler ( portCM_TRAP, vContextManagementTrap ) )\r
 171         {\r
 172                 _debug();\r
 173         }\r
 174 \r
 175         if( 0 == _install_trap_handler ( portSBP_TRAP, vSystemBusAndPeripheralsTrap ) )\r
 176         {\r
 177                 _debug();\r
 178         }\r
 179 \r
 180         if( 0 == _install_trap_handler ( portASSERT_TRAP, vAssertionTrap ) )\r
 181         {\r
 182                 _debug();\r
 183         }\r
 184 \r
 185         if( 0 == _install_trap_handler ( portNMI_TRAP, vNonMaskableInterruptTrap ) )\r
 186         {\r
 187                 _debug();\r
 188         }\r
 189 }\r
 190 /*-----------------------------------------------------------*/\r
 191 \r
 192 void vMMUTrap( int iTrapIdentification )\r
 193 {\r
 194         switch( iTrapIdentification )\r
 195         {\r
 196         case portTIN_MMU_VIRTUAL_ADDRESS_FILL:\r
 197         case portTIN_MMU_VIRTUAL_ADDRESS_PROTECTION:\r
 198         default:\r
 199                 _debug();\r
 200                 break;\r
 201         }\r
 202 }\r
 203 /*---------------------------------------------------------------------------*/\r
 204 \r
 205 void vInternalProtectionTrap( int iTrapIdentification )\r
 206 {\r
 207         /* Deliberate fall through to default. */\r
 208         switch( iTrapIdentification )\r
 209         {\r
 210                 case portTIN_IPT_PRIVILIGED_INSTRUCTION:\r
 211                         /* Instruction is not allowed at current execution level, eg DISABLE at User-0. */\r
 212 \r
 213                 case portTIN_IPT_MEMORY_PROTECTION_READ:\r
 214                         /* Load word using invalid address. */\r
 215                         \r
 216                 case portTIN_IPT_MEMORY_PROTECTION_WRITE:\r
 217                         /* Store Word using invalid address. */\r
 218                         \r
 219                 case portTIN_IPT_MEMORY_PROTECTION_EXECUTION:\r
 220                         /* PC jumped to an address outside of the valid range. */\r
 221                         \r
 222                 case portTIN_IPT_MEMORY_PROTECTION_PERIPHERAL_ACCESS:\r
 223                         /* Access to a peripheral denied at current execution level. */\r
 224                         \r
 225                 case portTIN_IPT_MEMORY_PROTECTION_NULL_ADDRESS:\r
 226                         /* NULL Pointer. */\r
 227                         \r
 228                 case portTIN_IPT_MEMORY_PROTECTION_GLOBAL_REGISTER_WRITE_PROTECTION:\r
 229                         /* Tried to modify a global address pointer register. */\r
 230                         \r
 231                 default:\r
 232                 \r
 233                         pxCurrentTCB[ 0 ] = _mfcr( $PCXI );\r
 234                         _debug();\r
 235                         break;\r
 236         }\r
 237 }\r
 238 /*---------------------------------------------------------------------------*/\r
 239 \r
 240 void vInstructionErrorTrap( int iTrapIdentification )\r
 241 {\r
 242         /* Deliberate fall through to default. */\r
 243         switch( iTrapIdentification )\r
 244         {\r
 245                 case portTIN_IE_ILLEGAL_OPCODE:\r
 246                 case portTIN_IE_UNIMPLEMENTED_OPCODE:\r
 247                 case portTIN_IE_INVALID_OPERAND:\r
 248                 case portTIN_IE_DATA_ADDRESS_ALIGNMENT:\r
 249                 case portTIN_IE_INVALID_LOCAL_MEMORY_ADDRESS:\r
 250                 default:\r
 251                         _debug();\r
 252                         break;\r
 253         }\r
 254 }\r
 255 /*---------------------------------------------------------------------------*/\r
 256 \r
 257 void vContextManagementTrap( int iTrapIdentification )\r
 258 {\r
 259         /* Deliberate fall through to default. */\r
 260         switch( iTrapIdentification )\r
 261         {\r
 262                 case portTIN_CM_FREE_CONTEXT_LIST_DEPLETION:\r
 263                 case portTIN_CM_CALL_DEPTH_OVERFLOW:\r
 264                 case portTIN_CM_CALL_DEPTH_UNDEFLOW:\r
 265                 case portTIN_CM_FREE_CONTEXT_LIST_UNDERFLOW:\r
 266                 case portTIN_CM_CALL_STACK_UNDERFLOW:\r
 267                 case portTIN_CM_CONTEXT_TYPE:\r
 268                 case portTIN_CM_NESTING_ERROR:\r
 269                 default:\r
 270                         _debug();\r
 271                         break;\r
 272         }\r
 273 }\r
 274 /*---------------------------------------------------------------------------*/\r
 275 \r
 276 void vSystemBusAndPeripheralsTrap( int iTrapIdentification )\r
 277 {\r
 278         /* Deliberate fall through to default. */\r
 279         switch( iTrapIdentification )\r
 280         {\r
 281                 case portTIN_SBP_PROGRAM_FETCH_SYNCHRONOUS_ERROR:\r
 282                 case portTIN_SBP_DATA_ACCESS_SYNCHRONOUS_ERROR:\r
 283                 case portTIN_SBP_DATA_ACCESS_ASYNCHRONOUS_ERROR:\r
 284                 case portTIN_SBP_COPROCESSOR_TRAP_ASYNCHRONOUS_ERROR:\r
 285                 case portTIN_SBP_PROGRAM_MEMORY_INTEGRITY_ERROR:\r
 286                 case portTIN_SBP_DATA_MEMORY_INTEGRITY_ERROR:\r
 287                 default:\r
 288                         _debug();\r
 289                         break;\r
 290         }\r
 291 }\r
 292 /*---------------------------------------------------------------------------*/\r
 293 \r
 294 void vAssertionTrap( int iTrapIdentification )\r
 295 {\r
 296         /* Deliberate fall through to default. */\r
 297         switch( iTrapIdentification )\r
 298         {\r
 299                 case portTIN_ASSERT_ARITHMETIC_OVERFLOW:\r
 300                 case portTIN_ASSERT_STICKY_ARITHMETIC_OVERFLOW:\r
 301                 default:\r
 302                         _debug();\r
 303                         break;\r
 304         }\r
 305 }\r
 306 /*---------------------------------------------------------------------------*/\r
 307 \r
 308 void vNonMaskableInterruptTrap( int iTrapIdentification )\r
 309 {\r
 310         /* Deliberate fall through to default. */\r
 311         switch( iTrapIdentification )\r
 312         {\r
 313                 case portTIN_NMI_NON_MASKABLE_INTERRUPT:\r
 314                 default:\r
 315                         _debug();\r
 316                         break;\r
 317         }\r
 318 }\r
 319 /*---------------------------------------------------------------------------*/\r