git.sur5r.net Git - freertos/blob - FreeRTOS/Source/portable/GCC/TriCore_1782/porttrap.c

   1 /*\r
   2     FreeRTOS V7.4.0 - Copyright (C) 2013 Real Time Engineers Ltd.\r
   3 \r
   4     FEATURES AND PORTS ARE ADDED TO FREERTOS ALL THE TIME.  PLEASE VISIT\r
   5     http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
   6 \r
   7     ***************************************************************************\r
   8      *                                                                       *\r
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  15      *    in-depth knowledge of how to use FreeRTOS, it will also help       *\r
  16      *    the FreeRTOS project to continue with its mission of providing     *\r
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  22      *    Thank you for using FreeRTOS, and thank you for your support!      *\r
  23      *                                                                       *\r
  24     ***************************************************************************\r
  25 \r
  26 \r
  27     This file is part of the FreeRTOS distribution.\r
  28 \r
  29     FreeRTOS is free software; you can redistribute it and/or modify it under\r
  30     the terms of the GNU General Public License (version 2) as published by the\r
  31     Free Software Foundation AND MODIFIED BY the FreeRTOS exception.\r
  32 \r
  33     >>>>>>NOTE<<<<<< The modification to the GPL is included to allow you to\r
  34     distribute a combined work that includes FreeRTOS without being obliged to\r
  35     provide the source code for proprietary components outside of the FreeRTOS\r
  36     kernel.\r
  37 \r
  38     FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
  39     WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
  40     FOR A PARTICULAR PURPOSE.  See the GNU General Public License for more\r
  41     details. You should have received a copy of the GNU General Public License\r
  42     and the FreeRTOS license exception along with FreeRTOS; if not itcan be\r
  43     viewed here: http://www.freertos.org/a00114.html and also obtained by\r
  44     writing to Real Time Engineers Ltd., contact details for whom are available\r
  45     on the FreeRTOS WEB site.\r
  46 \r
  47     1 tab == 4 spaces!\r
  48 \r
  49     ***************************************************************************\r
  50      *                                                                       *\r
  51      *    Having a problem?  Start by reading the FAQ "My application does   *\r
  52      *    not run, what could be wrong?"                                     *\r
  53      *                                                                       *\r
  54      *    http://www.FreeRTOS.org/FAQHelp.html                               *\r
  55      *                                                                       *\r
  56     ***************************************************************************\r
  57 \r
  58 \r
  59     http://www.FreeRTOS.org - Documentation, books, training, latest versions, \r
  60     license and Real Time Engineers Ltd. contact details.\r
  61 \r
  62     http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
  63     including FreeRTOS+Trace - an indispensable productivity tool, and our new\r
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  65 \r
  66     http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High \r
  67     Integrity Systems, who sell the code with commercial support, \r
  68     indemnification and middleware, under the OpenRTOS brand.\r
  69     \r
  70     http://www.SafeRTOS.com - High Integrity Systems also provide a safety \r
  71     engineered and independently SIL3 certified version for use in safety and \r
  72     mission critical applications that require provable dependability.\r
  73 */\r
  74 \r
  75 /* Kernel includes. */\r
  76 #include "FreeRTOS.h"\r
  77 \r
  78 /* Machine includes */\r
  79 #include <tc1782.h>\r
  80 #include <machine/intrinsics.h>\r
  81 #include <machine/cint.h>\r
  82 /*---------------------------------------------------------------------------*/\r
  83 \r
  84 /*\r
  85  * This reference is required by the Save/Restore Context Macros.\r
  86  */\r
  87 extern volatile unsigned long *pxCurrentTCB;\r
  88 /*-----------------------------------------------------------*/\r
  89 \r
  90 /*\r
  91  * This file contains base definitions for all of the possible traps in the system.\r
  92  * It is suggested to provide implementations for all of the traps but for\r
  93  * the time being they simply trigger a DEBUG instruction so that it is easy\r
  94  * to see what caused a particular trap.\r
  95  *\r
  96  * Trap Class 6, the SYSCALL, is used exclusively by the operating system.\r
  97  */\r
  98 \r
  99 /* The Trap Classes. */\r
 100 #define portMMU_TRAP                                                                            0\r
 101 #define portIPT_TRAP                                                                            1\r
 102 #define portIE_TRAP                                                                                     2\r
 103 #define portCM_TRAP                                                                                     3\r
 104 #define portSBP_TRAP                                                                            4\r
 105 #define portASSERT_TRAP                                                                         5\r
 106 #define portNMI_TRAP                                                                            7\r
 107 \r
 108 /* MMU Trap Identifications. */\r
 109 #define portTIN_MMU_VIRTUAL_ADDRESS_FILL                                        0\r
 110 #define portTIN_MMU_VIRTUAL_ADDRESS_PROTECTION                          1\r
 111 \r
 112 /* Internal Protection Trap Identifications. */\r
 113 #define portTIN_IPT_PRIVILIGED_INSTRUCTION                                      1\r
 114 #define portTIN_IPT_MEMORY_PROTECTION_READ                                      2\r
 115 #define portTIN_IPT_MEMORY_PROTECTION_WRITE                                     3\r
 116 #define portTIN_IPT_MEMORY_PROTECTION_EXECUTION                         4\r
 117 #define portTIN_IPT_MEMORY_PROTECTION_PERIPHERAL_ACCESS         5\r
 118 #define portTIN_IPT_MEMORY_PROTECTION_NULL_ADDRESS                      6\r
 119 #define portTIN_IPT_MEMORY_PROTECTION_GLOBAL_REGISTER_WRITE_PROTECTION  7\r
 120 \r
 121 /* Instruction Error Trap Identifications. */\r
 122 #define portTIN_IE_ILLEGAL_OPCODE                                                       1\r
 123 #define portTIN_IE_UNIMPLEMENTED_OPCODE                                         2\r
 124 #define portTIN_IE_INVALID_OPERAND                                                      3\r
 125 #define portTIN_IE_DATA_ADDRESS_ALIGNMENT                                       4\r
 126 #define portTIN_IE_INVALID_LOCAL_MEMORY_ADDRESS                         5\r
 127 \r
 128 /* Context Management Trap Identifications. */\r
 129 #define portTIN_CM_FREE_CONTEXT_LIST_DEPLETION                          1\r
 130 #define portTIN_CM_CALL_DEPTH_OVERFLOW                                          2\r
 131 #define portTIN_CM_CALL_DEPTH_UNDEFLOW                                          3\r
 132 #define portTIN_CM_FREE_CONTEXT_LIST_UNDERFLOW                          4\r
 133 #define portTIN_CM_CALL_STACK_UNDERFLOW                                         5\r
 134 #define portTIN_CM_CONTEXT_TYPE                                                         6\r
 135 #define portTIN_CM_NESTING_ERROR                                                        7\r
 136 \r
 137 /* System Bus and Peripherals Trap Identifications. */\r
 138 #define portTIN_SBP_PROGRAM_FETCH_SYNCHRONOUS_ERROR                     1\r
 139 #define portTIN_SBP_DATA_ACCESS_SYNCHRONOUS_ERROR                       2\r
 140 #define portTIN_SBP_DATA_ACCESS_ASYNCHRONOUS_ERROR                      3\r
 141 #define portTIN_SBP_COPROCESSOR_TRAP_ASYNCHRONOUS_ERROR         4\r
 142 #define portTIN_SBP_PROGRAM_MEMORY_INTEGRITY_ERROR                      5\r
 143 #define portTIN_SBP_DATA_MEMORY_INTEGRITY_ERROR                         6\r
 144 \r
 145 /* Assertion Trap Identifications. */\r
 146 #define portTIN_ASSERT_ARITHMETIC_OVERFLOW                                      1\r
 147 #define portTIN_ASSERT_STICKY_ARITHMETIC_OVERFLOW                       2\r
 148 \r
 149 /* Non-maskable Interrupt Trap Identifications. */\r
 150 #define portTIN_NMI_NON_MASKABLE_INTERRUPT                                      0\r
 151 /*---------------------------------------------------------------------------*/\r
 152 \r
 153 void vMMUTrap( int iTrapIdentification ) __attribute__( ( longcall, weak ) );\r
 154 void vInternalProtectionTrap( int iTrapIdentification ) __attribute__( ( longcall, weak ) );\r
 155 void vInstructionErrorTrap( int iTrapIdentification ) __attribute__( ( longcall, weak ) );\r
 156 void vContextManagementTrap( int iTrapIdentification ) __attribute__( ( longcall, weak ) );\r
 157 void vSystemBusAndPeripheralsTrap( int iTrapIdentification ) __attribute__( ( longcall, weak ) );\r
 158 void vAssertionTrap( int iTrapIdentification ) __attribute__( ( longcall, weak ) );\r
 159 void vNonMaskableInterruptTrap( int iTrapIdentification ) __attribute__( ( longcall, weak ) );\r
 160 /*---------------------------------------------------------------------------*/\r
 161 \r
 162 void vTrapInstallHandlers( void )\r
 163 {\r
 164         if( 0 == _install_trap_handler ( portMMU_TRAP, vMMUTrap ) )\r
 165         {\r
 166                 _debug();\r
 167         }\r
 168 \r
 169         if( 0 == _install_trap_handler ( portIPT_TRAP, vInternalProtectionTrap ) )\r
 170         {\r
 171                 _debug();\r
 172         }\r
 173 \r
 174         if( 0 == _install_trap_handler ( portIE_TRAP, vInstructionErrorTrap ) )\r
 175         {\r
 176                 _debug();\r
 177         }\r
 178 \r
 179         if( 0 == _install_trap_handler ( portCM_TRAP, vContextManagementTrap ) )\r
 180         {\r
 181                 _debug();\r
 182         }\r
 183 \r
 184         if( 0 == _install_trap_handler ( portSBP_TRAP, vSystemBusAndPeripheralsTrap ) )\r
 185         {\r
 186                 _debug();\r
 187         }\r
 188 \r
 189         if( 0 == _install_trap_handler ( portASSERT_TRAP, vAssertionTrap ) )\r
 190         {\r
 191                 _debug();\r
 192         }\r
 193 \r
 194         if( 0 == _install_trap_handler ( portNMI_TRAP, vNonMaskableInterruptTrap ) )\r
 195         {\r
 196                 _debug();\r
 197         }\r
 198 }\r
 199 /*-----------------------------------------------------------*/\r
 200 \r
 201 void vMMUTrap( int iTrapIdentification )\r
 202 {\r
 203         switch( iTrapIdentification )\r
 204         {\r
 205         case portTIN_MMU_VIRTUAL_ADDRESS_FILL:\r
 206         case portTIN_MMU_VIRTUAL_ADDRESS_PROTECTION:\r
 207         default:\r
 208                 _debug();\r
 209                 break;\r
 210         }\r
 211 }\r
 212 /*---------------------------------------------------------------------------*/\r
 213 \r
 214 void vInternalProtectionTrap( int iTrapIdentification )\r
 215 {\r
 216         /* Deliberate fall through to default. */\r
 217         switch( iTrapIdentification )\r
 218         {\r
 219                 case portTIN_IPT_PRIVILIGED_INSTRUCTION:\r
 220                         /* Instruction is not allowed at current execution level, eg DISABLE at User-0. */\r
 221 \r
 222                 case portTIN_IPT_MEMORY_PROTECTION_READ:\r
 223                         /* Load word using invalid address. */\r
 224                         \r
 225                 case portTIN_IPT_MEMORY_PROTECTION_WRITE:\r
 226                         /* Store Word using invalid address. */\r
 227                         \r
 228                 case portTIN_IPT_MEMORY_PROTECTION_EXECUTION:\r
 229                         /* PC jumped to an address outside of the valid range. */\r
 230                         \r
 231                 case portTIN_IPT_MEMORY_PROTECTION_PERIPHERAL_ACCESS:\r
 232                         /* Access to a peripheral denied at current execution level. */\r
 233                         \r
 234                 case portTIN_IPT_MEMORY_PROTECTION_NULL_ADDRESS:\r
 235                         /* NULL Pointer. */\r
 236                         \r
 237                 case portTIN_IPT_MEMORY_PROTECTION_GLOBAL_REGISTER_WRITE_PROTECTION:\r
 238                         /* Tried to modify a global address pointer register. */\r
 239                         \r
 240                 default:\r
 241                 \r
 242                         pxCurrentTCB[ 0 ] = _mfcr( $PCXI );\r
 243                         _debug();\r
 244                         break;\r
 245         }\r
 246 }\r
 247 /*---------------------------------------------------------------------------*/\r
 248 \r
 249 void vInstructionErrorTrap( int iTrapIdentification )\r
 250 {\r
 251         /* Deliberate fall through to default. */\r
 252         switch( iTrapIdentification )\r
 253         {\r
 254                 case portTIN_IE_ILLEGAL_OPCODE:\r
 255                 case portTIN_IE_UNIMPLEMENTED_OPCODE:\r
 256                 case portTIN_IE_INVALID_OPERAND:\r
 257                 case portTIN_IE_DATA_ADDRESS_ALIGNMENT:\r
 258                 case portTIN_IE_INVALID_LOCAL_MEMORY_ADDRESS:\r
 259                 default:\r
 260                         _debug();\r
 261                         break;\r
 262         }\r
 263 }\r
 264 /*---------------------------------------------------------------------------*/\r
 265 \r
 266 void vContextManagementTrap( int iTrapIdentification )\r
 267 {\r
 268         /* Deliberate fall through to default. */\r
 269         switch( iTrapIdentification )\r
 270         {\r
 271                 case portTIN_CM_FREE_CONTEXT_LIST_DEPLETION:\r
 272                 case portTIN_CM_CALL_DEPTH_OVERFLOW:\r
 273                 case portTIN_CM_CALL_DEPTH_UNDEFLOW:\r
 274                 case portTIN_CM_FREE_CONTEXT_LIST_UNDERFLOW:\r
 275                 case portTIN_CM_CALL_STACK_UNDERFLOW:\r
 276                 case portTIN_CM_CONTEXT_TYPE:\r
 277                 case portTIN_CM_NESTING_ERROR:\r
 278                 default:\r
 279                         _debug();\r
 280                         break;\r
 281         }\r
 282 }\r
 283 /*---------------------------------------------------------------------------*/\r
 284 \r
 285 void vSystemBusAndPeripheralsTrap( int iTrapIdentification )\r
 286 {\r
 287         /* Deliberate fall through to default. */\r
 288         switch( iTrapIdentification )\r
 289         {\r
 290                 case portTIN_SBP_PROGRAM_FETCH_SYNCHRONOUS_ERROR:\r
 291                 case portTIN_SBP_DATA_ACCESS_SYNCHRONOUS_ERROR:\r
 292                 case portTIN_SBP_DATA_ACCESS_ASYNCHRONOUS_ERROR:\r
 293                 case portTIN_SBP_COPROCESSOR_TRAP_ASYNCHRONOUS_ERROR:\r
 294                 case portTIN_SBP_PROGRAM_MEMORY_INTEGRITY_ERROR:\r
 295                 case portTIN_SBP_DATA_MEMORY_INTEGRITY_ERROR:\r
 296                 default:\r
 297                         _debug();\r
 298                         break;\r
 299         }\r
 300 }\r
 301 /*---------------------------------------------------------------------------*/\r
 302 \r
 303 void vAssertionTrap( int iTrapIdentification )\r
 304 {\r
 305         /* Deliberate fall through to default. */\r
 306         switch( iTrapIdentification )\r
 307         {\r
 308                 case portTIN_ASSERT_ARITHMETIC_OVERFLOW:\r
 309                 case portTIN_ASSERT_STICKY_ARITHMETIC_OVERFLOW:\r
 310                 default:\r
 311                         _debug();\r
 312                         break;\r
 313         }\r
 314 }\r
 315 /*---------------------------------------------------------------------------*/\r
 316 \r
 317 void vNonMaskableInterruptTrap( int iTrapIdentification )\r
 318 {\r
 319         /* Deliberate fall through to default. */\r
 320         switch( iTrapIdentification )\r
 321         {\r
 322                 case portTIN_NMI_NON_MASKABLE_INTERRUPT:\r
 323                 default:\r
 324                         _debug();\r
 325                         break;\r
 326         }\r
 327 }\r
 328 /*---------------------------------------------------------------------------*/\r