git.sur5r.net Git - freertos/blob - FreeRTOS/Source/portable/GCC/TriCore_1782/porttrap.c

   1 /*\r
   2  * FreeRTOS Kernel V10.2.0\r
   3  * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\r
   4  *\r
   5  * Permission is hereby granted, free of charge, to any person obtaining a copy of\r
   6  * this software and associated documentation files (the "Software"), to deal in\r
   7  * the Software without restriction, including without limitation the rights to\r
   8  * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\r
   9  * the Software, and to permit persons to whom the Software is furnished to do so,\r
  10  * subject to the following conditions:\r
  11  *\r
  12  * The above copyright notice and this permission notice shall be included in all\r
  13  * copies or substantial portions of the Software.\r
  14  *\r
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\r
  17  * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\r
  18  * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r
  19  * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
  20  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
  21  *\r
  22  * http://www.FreeRTOS.org\r
  23  * http://aws.amazon.com/freertos\r
  24  *\r
  25  * 1 tab == 4 spaces!\r
  26  */\r
  27 \r
  28 /* Kernel includes. */\r
  29 #include "FreeRTOS.h"\r
  30 \r
  31 /* Machine includes */\r
  32 #include <tc1782.h>\r
  33 #include <machine/intrinsics.h>\r
  34 #include <machine/cint.h>\r
  35 /*---------------------------------------------------------------------------*/\r
  36 \r
  37 /*\r
  38  * This reference is required by the Save/Restore Context Macros.\r
  39  */\r
  40 extern volatile uint32_t *pxCurrentTCB;\r
  41 /*-----------------------------------------------------------*/\r
  42 \r
  43 /*\r
  44  * This file contains base definitions for all of the possible traps in the system.\r
  45  * It is suggested to provide implementations for all of the traps but for\r
  46  * the time being they simply trigger a DEBUG instruction so that it is easy\r
  47  * to see what caused a particular trap.\r
  48  *\r
  49  * Trap Class 6, the SYSCALL, is used exclusively by the operating system.\r
  50  */\r
  51 \r
  52 /* The Trap Classes. */\r
  53 #define portMMU_TRAP                                                                            0\r
  54 #define portIPT_TRAP                                                                            1\r
  55 #define portIE_TRAP                                                                                     2\r
  56 #define portCM_TRAP                                                                                     3\r
  57 #define portSBP_TRAP                                                                            4\r
  58 #define portASSERT_TRAP                                                                         5\r
  59 #define portNMI_TRAP                                                                            7\r
  60 \r
  61 /* MMU Trap Identifications. */\r
  62 #define portTIN_MMU_VIRTUAL_ADDRESS_FILL                                        0\r
  63 #define portTIN_MMU_VIRTUAL_ADDRESS_PROTECTION                          1\r
  64 \r
  65 /* Internal Protection Trap Identifications. */\r
  66 #define portTIN_IPT_PRIVILIGED_INSTRUCTION                                      1\r
  67 #define portTIN_IPT_MEMORY_PROTECTION_READ                                      2\r
  68 #define portTIN_IPT_MEMORY_PROTECTION_WRITE                                     3\r
  69 #define portTIN_IPT_MEMORY_PROTECTION_EXECUTION                         4\r
  70 #define portTIN_IPT_MEMORY_PROTECTION_PERIPHERAL_ACCESS         5\r
  71 #define portTIN_IPT_MEMORY_PROTECTION_NULL_ADDRESS                      6\r
  72 #define portTIN_IPT_MEMORY_PROTECTION_GLOBAL_REGISTER_WRITE_PROTECTION  7\r
  73 \r
  74 /* Instruction Error Trap Identifications. */\r
  75 #define portTIN_IE_ILLEGAL_OPCODE                                                       1\r
  76 #define portTIN_IE_UNIMPLEMENTED_OPCODE                                         2\r
  77 #define portTIN_IE_INVALID_OPERAND                                                      3\r
  78 #define portTIN_IE_DATA_ADDRESS_ALIGNMENT                                       4\r
  79 #define portTIN_IE_INVALID_LOCAL_MEMORY_ADDRESS                         5\r
  80 \r
  81 /* Context Management Trap Identifications. */\r
  82 #define portTIN_CM_FREE_CONTEXT_LIST_DEPLETION                          1\r
  83 #define portTIN_CM_CALL_DEPTH_OVERFLOW                                          2\r
  84 #define portTIN_CM_CALL_DEPTH_UNDEFLOW                                          3\r
  85 #define portTIN_CM_FREE_CONTEXT_LIST_UNDERFLOW                          4\r
  86 #define portTIN_CM_CALL_STACK_UNDERFLOW                                         5\r
  87 #define portTIN_CM_CONTEXT_TYPE                                                         6\r
  88 #define portTIN_CM_NESTING_ERROR                                                        7\r
  89 \r
  90 /* System Bus and Peripherals Trap Identifications. */\r
  91 #define portTIN_SBP_PROGRAM_FETCH_SYNCHRONOUS_ERROR                     1\r
  92 #define portTIN_SBP_DATA_ACCESS_SYNCHRONOUS_ERROR                       2\r
  93 #define portTIN_SBP_DATA_ACCESS_ASYNCHRONOUS_ERROR                      3\r
  94 #define portTIN_SBP_COPROCESSOR_TRAP_ASYNCHRONOUS_ERROR         4\r
  95 #define portTIN_SBP_PROGRAM_MEMORY_INTEGRITY_ERROR                      5\r
  96 #define portTIN_SBP_DATA_MEMORY_INTEGRITY_ERROR                         6\r
  97 \r
  98 /* Assertion Trap Identifications. */\r
  99 #define portTIN_ASSERT_ARITHMETIC_OVERFLOW                                      1\r
 100 #define portTIN_ASSERT_STICKY_ARITHMETIC_OVERFLOW                       2\r
 101 \r
 102 /* Non-maskable Interrupt Trap Identifications. */\r
 103 #define portTIN_NMI_NON_MASKABLE_INTERRUPT                                      0\r
 104 /*---------------------------------------------------------------------------*/\r
 105 \r
 106 void vMMUTrap( int iTrapIdentification ) __attribute__( ( longcall, weak ) );\r
 107 void vInternalProtectionTrap( int iTrapIdentification ) __attribute__( ( longcall, weak ) );\r
 108 void vInstructionErrorTrap( int iTrapIdentification ) __attribute__( ( longcall, weak ) );\r
 109 void vContextManagementTrap( int iTrapIdentification ) __attribute__( ( longcall, weak ) );\r
 110 void vSystemBusAndPeripheralsTrap( int iTrapIdentification ) __attribute__( ( longcall, weak ) );\r
 111 void vAssertionTrap( int iTrapIdentification ) __attribute__( ( longcall, weak ) );\r
 112 void vNonMaskableInterruptTrap( int iTrapIdentification ) __attribute__( ( longcall, weak ) );\r
 113 /*---------------------------------------------------------------------------*/\r
 114 \r
 115 void vTrapInstallHandlers( void )\r
 116 {\r
 117         if( 0 == _install_trap_handler ( portMMU_TRAP, vMMUTrap ) )\r
 118         {\r
 119                 _debug();\r
 120         }\r
 121 \r
 122         if( 0 == _install_trap_handler ( portIPT_TRAP, vInternalProtectionTrap ) )\r
 123         {\r
 124                 _debug();\r
 125         }\r
 126 \r
 127         if( 0 == _install_trap_handler ( portIE_TRAP, vInstructionErrorTrap ) )\r
 128         {\r
 129                 _debug();\r
 130         }\r
 131 \r
 132         if( 0 == _install_trap_handler ( portCM_TRAP, vContextManagementTrap ) )\r
 133         {\r
 134                 _debug();\r
 135         }\r
 136 \r
 137         if( 0 == _install_trap_handler ( portSBP_TRAP, vSystemBusAndPeripheralsTrap ) )\r
 138         {\r
 139                 _debug();\r
 140         }\r
 141 \r
 142         if( 0 == _install_trap_handler ( portASSERT_TRAP, vAssertionTrap ) )\r
 143         {\r
 144                 _debug();\r
 145         }\r
 146 \r
 147         if( 0 == _install_trap_handler ( portNMI_TRAP, vNonMaskableInterruptTrap ) )\r
 148         {\r
 149                 _debug();\r
 150         }\r
 151 }\r
 152 /*-----------------------------------------------------------*/\r
 153 \r
 154 void vMMUTrap( int iTrapIdentification )\r
 155 {\r
 156         switch( iTrapIdentification )\r
 157         {\r
 158         case portTIN_MMU_VIRTUAL_ADDRESS_FILL:\r
 159         case portTIN_MMU_VIRTUAL_ADDRESS_PROTECTION:\r
 160         default:\r
 161                 _debug();\r
 162                 break;\r
 163         }\r
 164 }\r
 165 /*---------------------------------------------------------------------------*/\r
 166 \r
 167 void vInternalProtectionTrap( int iTrapIdentification )\r
 168 {\r
 169         /* Deliberate fall through to default. */\r
 170         switch( iTrapIdentification )\r
 171         {\r
 172                 case portTIN_IPT_PRIVILIGED_INSTRUCTION:\r
 173                         /* Instruction is not allowed at current execution level, eg DISABLE at User-0. */\r
 174 \r
 175                 case portTIN_IPT_MEMORY_PROTECTION_READ:\r
 176                         /* Load word using invalid address. */\r
 177                         \r
 178                 case portTIN_IPT_MEMORY_PROTECTION_WRITE:\r
 179                         /* Store Word using invalid address. */\r
 180                         \r
 181                 case portTIN_IPT_MEMORY_PROTECTION_EXECUTION:\r
 182                         /* PC jumped to an address outside of the valid range. */\r
 183                         \r
 184                 case portTIN_IPT_MEMORY_PROTECTION_PERIPHERAL_ACCESS:\r
 185                         /* Access to a peripheral denied at current execution level. */\r
 186                         \r
 187                 case portTIN_IPT_MEMORY_PROTECTION_NULL_ADDRESS:\r
 188                         /* NULL Pointer. */\r
 189                         \r
 190                 case portTIN_IPT_MEMORY_PROTECTION_GLOBAL_REGISTER_WRITE_PROTECTION:\r
 191                         /* Tried to modify a global address pointer register. */\r
 192                         \r
 193                 default:\r
 194                 \r
 195                         pxCurrentTCB[ 0 ] = __MFCR( $PCXI );\r
 196                         _debug();\r
 197                         break;\r
 198         }\r
 199 }\r
 200 /*---------------------------------------------------------------------------*/\r
 201 \r
 202 void vInstructionErrorTrap( int iTrapIdentification )\r
 203 {\r
 204         /* Deliberate fall through to default. */\r
 205         switch( iTrapIdentification )\r
 206         {\r
 207                 case portTIN_IE_ILLEGAL_OPCODE:\r
 208                 case portTIN_IE_UNIMPLEMENTED_OPCODE:\r
 209                 case portTIN_IE_INVALID_OPERAND:\r
 210                 case portTIN_IE_DATA_ADDRESS_ALIGNMENT:\r
 211                 case portTIN_IE_INVALID_LOCAL_MEMORY_ADDRESS:\r
 212                 default:\r
 213                         _debug();\r
 214                         break;\r
 215         }\r
 216 }\r
 217 /*---------------------------------------------------------------------------*/\r
 218 \r
 219 void vContextManagementTrap( int iTrapIdentification )\r
 220 {\r
 221         /* Deliberate fall through to default. */\r
 222         switch( iTrapIdentification )\r
 223         {\r
 224                 case portTIN_CM_FREE_CONTEXT_LIST_DEPLETION:\r
 225                 case portTIN_CM_CALL_DEPTH_OVERFLOW:\r
 226                 case portTIN_CM_CALL_DEPTH_UNDEFLOW:\r
 227                 case portTIN_CM_FREE_CONTEXT_LIST_UNDERFLOW:\r
 228                 case portTIN_CM_CALL_STACK_UNDERFLOW:\r
 229                 case portTIN_CM_CONTEXT_TYPE:\r
 230                 case portTIN_CM_NESTING_ERROR:\r
 231                 default:\r
 232                         _debug();\r
 233                         break;\r
 234         }\r
 235 }\r
 236 /*---------------------------------------------------------------------------*/\r
 237 \r
 238 void vSystemBusAndPeripheralsTrap( int iTrapIdentification )\r
 239 {\r
 240         /* Deliberate fall through to default. */\r
 241         switch( iTrapIdentification )\r
 242         {\r
 243                 case portTIN_SBP_PROGRAM_FETCH_SYNCHRONOUS_ERROR:\r
 244                 case portTIN_SBP_DATA_ACCESS_SYNCHRONOUS_ERROR:\r
 245                 case portTIN_SBP_DATA_ACCESS_ASYNCHRONOUS_ERROR:\r
 246                 case portTIN_SBP_COPROCESSOR_TRAP_ASYNCHRONOUS_ERROR:\r
 247                 case portTIN_SBP_PROGRAM_MEMORY_INTEGRITY_ERROR:\r
 248                 case portTIN_SBP_DATA_MEMORY_INTEGRITY_ERROR:\r
 249                 default:\r
 250                         _debug();\r
 251                         break;\r
 252         }\r
 253 }\r
 254 /*---------------------------------------------------------------------------*/\r
 255 \r
 256 void vAssertionTrap( int iTrapIdentification )\r
 257 {\r
 258         /* Deliberate fall through to default. */\r
 259         switch( iTrapIdentification )\r
 260         {\r
 261                 case portTIN_ASSERT_ARITHMETIC_OVERFLOW:\r
 262                 case portTIN_ASSERT_STICKY_ARITHMETIC_OVERFLOW:\r
 263                 default:\r
 264                         _debug();\r
 265                         break;\r
 266         }\r
 267 }\r
 268 /*---------------------------------------------------------------------------*/\r
 269 \r
 270 void vNonMaskableInterruptTrap( int iTrapIdentification )\r
 271 {\r
 272         /* Deliberate fall through to default. */\r
 273         switch( iTrapIdentification )\r
 274         {\r
 275                 case portTIN_NMI_NON_MASKABLE_INTERRUPT:\r
 276                 default:\r
 277                         _debug();\r
 278                         break;\r
 279         }\r
 280 }\r
 281 /*---------------------------------------------------------------------------*/\r