git.sur5r.net Git - freertos/blob - FreeRTOS/Source/portable/GCC/TriCore_1782/porttrap.c

   1 /*\r
   2     FreeRTOS V8.2.0rc1 - Copyright (C) 2014 Real Time Engineers Ltd.\r
   3     All rights reserved\r
   4 \r
   5     VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.\r
   6 \r
   7     This file is part of the FreeRTOS distribution.\r
   8 \r
   9     FreeRTOS is free software; you can redistribute it and/or modify it under\r
  10     the terms of the GNU General Public License (version 2) as published by the\r
  11     Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.\r
  12 \r
  13     >>!   NOTE: The modification to the GPL is included to allow you to     !<<\r
  14     >>!   distribute a combined work that includes FreeRTOS without being   !<<\r
  15     >>!   obliged to provide the source code for proprietary components     !<<\r
  16     >>!   outside of the FreeRTOS kernel.                                   !<<\r
  17 \r
  18     FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY\r
  19     WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS\r
  20     FOR A PARTICULAR PURPOSE.  Full license text is available on the following\r
  21     link: http://www.freertos.org/a00114.html\r
  22 \r
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  24 \r
  25     ***************************************************************************\r
  26      *                                                                       *\r
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  33 \r
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  47 \r
  48     ***************************************************************************\r
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  53      *   earlier than would otherwise be possible.  Richard Barry is both    *\r
  54      *   the architect and key author of FreeRTOS, and so also the world's   *\r
  55      *   leading authority on what is the world's most popular real time     *\r
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  61      *                                                                       *\r
  62     ***************************************************************************\r
  63 \r
  64     ***************************************************************************\r
  65      *                                                                       *\r
  66      *    You are receiving this top quality software for free.  Please play *\r
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  73     ***************************************************************************\r
  74 \r
  75     http://www.FreeRTOS.org - Documentation, books, training, latest versions,\r
  76     license and Real Time Engineers Ltd. contact details.\r
  77 \r
  78     http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
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  88 \r
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  90     engineered and independently SIL3 certified version for use in safety and\r
  91     mission critical applications that require provable dependability.\r
  92 \r
  93     1 tab == 4 spaces!\r
  94 */\r
  95 \r
  96 /* Kernel includes. */\r
  97 #include "FreeRTOS.h"\r
  98 \r
  99 /* Machine includes */\r
 100 #include <tc1782.h>\r
 101 #include <machine/intrinsics.h>\r
 102 #include <machine/cint.h>\r
 103 /*---------------------------------------------------------------------------*/\r
 104 \r
 105 /*\r
 106  * This reference is required by the Save/Restore Context Macros.\r
 107  */\r
 108 extern volatile uint32_t *pxCurrentTCB;\r
 109 /*-----------------------------------------------------------*/\r
 110 \r
 111 /*\r
 112  * This file contains base definitions for all of the possible traps in the system.\r
 113  * It is suggested to provide implementations for all of the traps but for\r
 114  * the time being they simply trigger a DEBUG instruction so that it is easy\r
 115  * to see what caused a particular trap.\r
 116  *\r
 117  * Trap Class 6, the SYSCALL, is used exclusively by the operating system.\r
 118  */\r
 119 \r
 120 /* The Trap Classes. */\r
 121 #define portMMU_TRAP                                                                            0\r
 122 #define portIPT_TRAP                                                                            1\r
 123 #define portIE_TRAP                                                                                     2\r
 124 #define portCM_TRAP                                                                                     3\r
 125 #define portSBP_TRAP                                                                            4\r
 126 #define portASSERT_TRAP                                                                         5\r
 127 #define portNMI_TRAP                                                                            7\r
 128 \r
 129 /* MMU Trap Identifications. */\r
 130 #define portTIN_MMU_VIRTUAL_ADDRESS_FILL                                        0\r
 131 #define portTIN_MMU_VIRTUAL_ADDRESS_PROTECTION                          1\r
 132 \r
 133 /* Internal Protection Trap Identifications. */\r
 134 #define portTIN_IPT_PRIVILIGED_INSTRUCTION                                      1\r
 135 #define portTIN_IPT_MEMORY_PROTECTION_READ                                      2\r
 136 #define portTIN_IPT_MEMORY_PROTECTION_WRITE                                     3\r
 137 #define portTIN_IPT_MEMORY_PROTECTION_EXECUTION                         4\r
 138 #define portTIN_IPT_MEMORY_PROTECTION_PERIPHERAL_ACCESS         5\r
 139 #define portTIN_IPT_MEMORY_PROTECTION_NULL_ADDRESS                      6\r
 140 #define portTIN_IPT_MEMORY_PROTECTION_GLOBAL_REGISTER_WRITE_PROTECTION  7\r
 141 \r
 142 /* Instruction Error Trap Identifications. */\r
 143 #define portTIN_IE_ILLEGAL_OPCODE                                                       1\r
 144 #define portTIN_IE_UNIMPLEMENTED_OPCODE                                         2\r
 145 #define portTIN_IE_INVALID_OPERAND                                                      3\r
 146 #define portTIN_IE_DATA_ADDRESS_ALIGNMENT                                       4\r
 147 #define portTIN_IE_INVALID_LOCAL_MEMORY_ADDRESS                         5\r
 148 \r
 149 /* Context Management Trap Identifications. */\r
 150 #define portTIN_CM_FREE_CONTEXT_LIST_DEPLETION                          1\r
 151 #define portTIN_CM_CALL_DEPTH_OVERFLOW                                          2\r
 152 #define portTIN_CM_CALL_DEPTH_UNDEFLOW                                          3\r
 153 #define portTIN_CM_FREE_CONTEXT_LIST_UNDERFLOW                          4\r
 154 #define portTIN_CM_CALL_STACK_UNDERFLOW                                         5\r
 155 #define portTIN_CM_CONTEXT_TYPE                                                         6\r
 156 #define portTIN_CM_NESTING_ERROR                                                        7\r
 157 \r
 158 /* System Bus and Peripherals Trap Identifications. */\r
 159 #define portTIN_SBP_PROGRAM_FETCH_SYNCHRONOUS_ERROR                     1\r
 160 #define portTIN_SBP_DATA_ACCESS_SYNCHRONOUS_ERROR                       2\r
 161 #define portTIN_SBP_DATA_ACCESS_ASYNCHRONOUS_ERROR                      3\r
 162 #define portTIN_SBP_COPROCESSOR_TRAP_ASYNCHRONOUS_ERROR         4\r
 163 #define portTIN_SBP_PROGRAM_MEMORY_INTEGRITY_ERROR                      5\r
 164 #define portTIN_SBP_DATA_MEMORY_INTEGRITY_ERROR                         6\r
 165 \r
 166 /* Assertion Trap Identifications. */\r
 167 #define portTIN_ASSERT_ARITHMETIC_OVERFLOW                                      1\r
 168 #define portTIN_ASSERT_STICKY_ARITHMETIC_OVERFLOW                       2\r
 169 \r
 170 /* Non-maskable Interrupt Trap Identifications. */\r
 171 #define portTIN_NMI_NON_MASKABLE_INTERRUPT                                      0\r
 172 /*---------------------------------------------------------------------------*/\r
 173 \r
 174 void vMMUTrap( int iTrapIdentification ) __attribute__( ( longcall, weak ) );\r
 175 void vInternalProtectionTrap( int iTrapIdentification ) __attribute__( ( longcall, weak ) );\r
 176 void vInstructionErrorTrap( int iTrapIdentification ) __attribute__( ( longcall, weak ) );\r
 177 void vContextManagementTrap( int iTrapIdentification ) __attribute__( ( longcall, weak ) );\r
 178 void vSystemBusAndPeripheralsTrap( int iTrapIdentification ) __attribute__( ( longcall, weak ) );\r
 179 void vAssertionTrap( int iTrapIdentification ) __attribute__( ( longcall, weak ) );\r
 180 void vNonMaskableInterruptTrap( int iTrapIdentification ) __attribute__( ( longcall, weak ) );\r
 181 /*---------------------------------------------------------------------------*/\r
 182 \r
 183 void vTrapInstallHandlers( void )\r
 184 {\r
 185         if( 0 == _install_trap_handler ( portMMU_TRAP, vMMUTrap ) )\r
 186         {\r
 187                 _debug();\r
 188         }\r
 189 \r
 190         if( 0 == _install_trap_handler ( portIPT_TRAP, vInternalProtectionTrap ) )\r
 191         {\r
 192                 _debug();\r
 193         }\r
 194 \r
 195         if( 0 == _install_trap_handler ( portIE_TRAP, vInstructionErrorTrap ) )\r
 196         {\r
 197                 _debug();\r
 198         }\r
 199 \r
 200         if( 0 == _install_trap_handler ( portCM_TRAP, vContextManagementTrap ) )\r
 201         {\r
 202                 _debug();\r
 203         }\r
 204 \r
 205         if( 0 == _install_trap_handler ( portSBP_TRAP, vSystemBusAndPeripheralsTrap ) )\r
 206         {\r
 207                 _debug();\r
 208         }\r
 209 \r
 210         if( 0 == _install_trap_handler ( portASSERT_TRAP, vAssertionTrap ) )\r
 211         {\r
 212                 _debug();\r
 213         }\r
 214 \r
 215         if( 0 == _install_trap_handler ( portNMI_TRAP, vNonMaskableInterruptTrap ) )\r
 216         {\r
 217                 _debug();\r
 218         }\r
 219 }\r
 220 /*-----------------------------------------------------------*/\r
 221 \r
 222 void vMMUTrap( int iTrapIdentification )\r
 223 {\r
 224         switch( iTrapIdentification )\r
 225         {\r
 226         case portTIN_MMU_VIRTUAL_ADDRESS_FILL:\r
 227         case portTIN_MMU_VIRTUAL_ADDRESS_PROTECTION:\r
 228         default:\r
 229                 _debug();\r
 230                 break;\r
 231         }\r
 232 }\r
 233 /*---------------------------------------------------------------------------*/\r
 234 \r
 235 void vInternalProtectionTrap( int iTrapIdentification )\r
 236 {\r
 237         /* Deliberate fall through to default. */\r
 238         switch( iTrapIdentification )\r
 239         {\r
 240                 case portTIN_IPT_PRIVILIGED_INSTRUCTION:\r
 241                         /* Instruction is not allowed at current execution level, eg DISABLE at User-0. */\r
 242 \r
 243                 case portTIN_IPT_MEMORY_PROTECTION_READ:\r
 244                         /* Load word using invalid address. */\r
 245                         \r
 246                 case portTIN_IPT_MEMORY_PROTECTION_WRITE:\r
 247                         /* Store Word using invalid address. */\r
 248                         \r
 249                 case portTIN_IPT_MEMORY_PROTECTION_EXECUTION:\r
 250                         /* PC jumped to an address outside of the valid range. */\r
 251                         \r
 252                 case portTIN_IPT_MEMORY_PROTECTION_PERIPHERAL_ACCESS:\r
 253                         /* Access to a peripheral denied at current execution level. */\r
 254                         \r
 255                 case portTIN_IPT_MEMORY_PROTECTION_NULL_ADDRESS:\r
 256                         /* NULL Pointer. */\r
 257                         \r
 258                 case portTIN_IPT_MEMORY_PROTECTION_GLOBAL_REGISTER_WRITE_PROTECTION:\r
 259                         /* Tried to modify a global address pointer register. */\r
 260                         \r
 261                 default:\r
 262                 \r
 263                         pxCurrentTCB[ 0 ] = _mfcr( $PCXI );\r
 264                         _debug();\r
 265                         break;\r
 266         }\r
 267 }\r
 268 /*---------------------------------------------------------------------------*/\r
 269 \r
 270 void vInstructionErrorTrap( int iTrapIdentification )\r
 271 {\r
 272         /* Deliberate fall through to default. */\r
 273         switch( iTrapIdentification )\r
 274         {\r
 275                 case portTIN_IE_ILLEGAL_OPCODE:\r
 276                 case portTIN_IE_UNIMPLEMENTED_OPCODE:\r
 277                 case portTIN_IE_INVALID_OPERAND:\r
 278                 case portTIN_IE_DATA_ADDRESS_ALIGNMENT:\r
 279                 case portTIN_IE_INVALID_LOCAL_MEMORY_ADDRESS:\r
 280                 default:\r
 281                         _debug();\r
 282                         break;\r
 283         }\r
 284 }\r
 285 /*---------------------------------------------------------------------------*/\r
 286 \r
 287 void vContextManagementTrap( int iTrapIdentification )\r
 288 {\r
 289         /* Deliberate fall through to default. */\r
 290         switch( iTrapIdentification )\r
 291         {\r
 292                 case portTIN_CM_FREE_CONTEXT_LIST_DEPLETION:\r
 293                 case portTIN_CM_CALL_DEPTH_OVERFLOW:\r
 294                 case portTIN_CM_CALL_DEPTH_UNDEFLOW:\r
 295                 case portTIN_CM_FREE_CONTEXT_LIST_UNDERFLOW:\r
 296                 case portTIN_CM_CALL_STACK_UNDERFLOW:\r
 297                 case portTIN_CM_CONTEXT_TYPE:\r
 298                 case portTIN_CM_NESTING_ERROR:\r
 299                 default:\r
 300                         _debug();\r
 301                         break;\r
 302         }\r
 303 }\r
 304 /*---------------------------------------------------------------------------*/\r
 305 \r
 306 void vSystemBusAndPeripheralsTrap( int iTrapIdentification )\r
 307 {\r
 308         /* Deliberate fall through to default. */\r
 309         switch( iTrapIdentification )\r
 310         {\r
 311                 case portTIN_SBP_PROGRAM_FETCH_SYNCHRONOUS_ERROR:\r
 312                 case portTIN_SBP_DATA_ACCESS_SYNCHRONOUS_ERROR:\r
 313                 case portTIN_SBP_DATA_ACCESS_ASYNCHRONOUS_ERROR:\r
 314                 case portTIN_SBP_COPROCESSOR_TRAP_ASYNCHRONOUS_ERROR:\r
 315                 case portTIN_SBP_PROGRAM_MEMORY_INTEGRITY_ERROR:\r
 316                 case portTIN_SBP_DATA_MEMORY_INTEGRITY_ERROR:\r
 317                 default:\r
 318                         _debug();\r
 319                         break;\r
 320         }\r
 321 }\r
 322 /*---------------------------------------------------------------------------*/\r
 323 \r
 324 void vAssertionTrap( int iTrapIdentification )\r
 325 {\r
 326         /* Deliberate fall through to default. */\r
 327         switch( iTrapIdentification )\r
 328         {\r
 329                 case portTIN_ASSERT_ARITHMETIC_OVERFLOW:\r
 330                 case portTIN_ASSERT_STICKY_ARITHMETIC_OVERFLOW:\r
 331                 default:\r
 332                         _debug();\r
 333                         break;\r
 334         }\r
 335 }\r
 336 /*---------------------------------------------------------------------------*/\r
 337 \r
 338 void vNonMaskableInterruptTrap( int iTrapIdentification )\r
 339 {\r
 340         /* Deliberate fall through to default. */\r
 341         switch( iTrapIdentification )\r
 342         {\r
 343                 case portTIN_NMI_NON_MASKABLE_INTERRUPT:\r
 344                 default:\r
 345                         _debug();\r
 346                         break;\r
 347         }\r
 348 }\r
 349 /*---------------------------------------------------------------------------*/\r