git.sur5r.net Git - freertos/blob - FreeRTOS/Source/portable/GCC/TriCore_1782/porttrap.c

   1 /*\r
   2     FreeRTOS V7.2.0 - Copyright (C) 2012 Real Time Engineers Ltd.\r
   3 \r
   4 \r
   5     ***************************************************************************\r
   6      *                                                                       *\r
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  22     ***************************************************************************\r
  23 \r
  24 \r
  25     This file is part of the FreeRTOS distribution.\r
  26 \r
  27     FreeRTOS is free software; you can redistribute it and/or modify it under\r
  28     the terms of the GNU General Public License (version 2) as published by the\r
  29     Free Software Foundation AND MODIFIED BY the FreeRTOS exception.\r
  30     >>>NOTE<<< The modification to the GPL is included to allow you to\r
  31     distribute a combined work that includes FreeRTOS without being obliged to\r
  32     provide the source code for proprietary components outside of the FreeRTOS\r
  33     kernel.  FreeRTOS is distributed in the hope that it will be useful, but\r
  34     WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY\r
  35     or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for\r
  36     more details. You should have received a copy of the GNU General Public\r
  37     License and the FreeRTOS license exception along with FreeRTOS; if not it\r
  38     can be viewed here: http://www.freertos.org/a00114.html and also obtained\r
  39     by writing to Richard Barry, contact details for whom are available on the\r
  40     FreeRTOS WEB site.\r
  41 \r
  42     1 tab == 4 spaces!\r
  43     \r
  44     ***************************************************************************\r
  45      *                                                                       *\r
  46      *    Having a problem?  Start by reading the FAQ "My application does   *\r
  47      *    not run, what could be wrong?                                      *\r
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  51     ***************************************************************************\r
  52 \r
  53     \r
  54     http://www.FreeRTOS.org - Documentation, training, latest information, \r
  55     license and contact details.\r
  56     \r
  57     http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,\r
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  59 \r
  60     Real Time Engineers ltd license FreeRTOS to High Integrity Systems, who sell \r
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  65 */\r
  66 \r
  67 /* Kernel includes. */\r
  68 #include "FreeRTOS.h"\r
  69 \r
  70 /* Machine includes */\r
  71 #include <tc1782.h>\r
  72 #include <machine/intrinsics.h>\r
  73 #include <machine/cint.h>\r
  74 /*---------------------------------------------------------------------------*/\r
  75 \r
  76 /*\r
  77  * This reference is required by the Save/Restore Context Macros.\r
  78  */\r
  79 extern volatile unsigned long *pxCurrentTCB;\r
  80 /*-----------------------------------------------------------*/\r
  81 \r
  82 /*\r
  83  * This file contains base definitions for all of the possible traps in the system.\r
  84  * It is suggested to provide implementations for all of the traps but for\r
  85  * the time being they simply trigger a DEBUG instruction so that it is easy\r
  86  * to see what caused a particular trap.\r
  87  *\r
  88  * Trap Class 6, the SYSCALL, is used exclusively by the operating system.\r
  89  */\r
  90 \r
  91 /* The Trap Classes. */\r
  92 #define portMMU_TRAP                                                                            0\r
  93 #define portIPT_TRAP                                                                            1\r
  94 #define portIE_TRAP                                                                                     2\r
  95 #define portCM_TRAP                                                                                     3\r
  96 #define portSBP_TRAP                                                                            4\r
  97 #define portASSERT_TRAP                                                                         5\r
  98 #define portNMI_TRAP                                                                            7\r
  99 \r
 100 /* MMU Trap Identifications. */\r
 101 #define portTIN_MMU_VIRTUAL_ADDRESS_FILL                                        0\r
 102 #define portTIN_MMU_VIRTUAL_ADDRESS_PROTECTION                          1\r
 103 \r
 104 /* Internal Protection Trap Identifications. */\r
 105 #define portTIN_IPT_PRIVILIGED_INSTRUCTION                                      1\r
 106 #define portTIN_IPT_MEMORY_PROTECTION_READ                                      2\r
 107 #define portTIN_IPT_MEMORY_PROTECTION_WRITE                                     3\r
 108 #define portTIN_IPT_MEMORY_PROTECTION_EXECUTION                         4\r
 109 #define portTIN_IPT_MEMORY_PROTECTION_PERIPHERAL_ACCESS         5\r
 110 #define portTIN_IPT_MEMORY_PROTECTION_NULL_ADDRESS                      6\r
 111 #define portTIN_IPT_MEMORY_PROTECTION_GLOBAL_REGISTER_WRITE_PROTECTION  7\r
 112 \r
 113 /* Instruction Error Trap Identifications. */\r
 114 #define portTIN_IE_ILLEGAL_OPCODE                                                       1\r
 115 #define portTIN_IE_UNIMPLEMENTED_OPCODE                                         2\r
 116 #define portTIN_IE_INVALID_OPERAND                                                      3\r
 117 #define portTIN_IE_DATA_ADDRESS_ALIGNMENT                                       4\r
 118 #define portTIN_IE_INVALID_LOCAL_MEMORY_ADDRESS                         5\r
 119 \r
 120 /* Context Management Trap Identifications. */\r
 121 #define portTIN_CM_FREE_CONTEXT_LIST_DEPLETION                          1\r
 122 #define portTIN_CM_CALL_DEPTH_OVERFLOW                                          2\r
 123 #define portTIN_CM_CALL_DEPTH_UNDEFLOW                                          3\r
 124 #define portTIN_CM_FREE_CONTEXT_LIST_UNDERFLOW                          4\r
 125 #define portTIN_CM_CALL_STACK_UNDERFLOW                                         5\r
 126 #define portTIN_CM_CONTEXT_TYPE                                                         6\r
 127 #define portTIN_CM_NESTING_ERROR                                                        7\r
 128 \r
 129 /* System Bus and Peripherals Trap Identifications. */\r
 130 #define portTIN_SBP_PROGRAM_FETCH_SYNCHRONOUS_ERROR                     1\r
 131 #define portTIN_SBP_DATA_ACCESS_SYNCHRONOUS_ERROR                       2\r
 132 #define portTIN_SBP_DATA_ACCESS_ASYNCHRONOUS_ERROR                      3\r
 133 #define portTIN_SBP_COPROCESSOR_TRAP_ASYNCHRONOUS_ERROR         4\r
 134 #define portTIN_SBP_PROGRAM_MEMORY_INTEGRITY_ERROR                      5\r
 135 #define portTIN_SBP_DATA_MEMORY_INTEGRITY_ERROR                         6\r
 136 \r
 137 /* Assertion Trap Identifications. */\r
 138 #define portTIN_ASSERT_ARITHMETIC_OVERFLOW                                      1\r
 139 #define portTIN_ASSERT_STICKY_ARITHMETIC_OVERFLOW                       2\r
 140 \r
 141 /* Non-maskable Interrupt Trap Identifications. */\r
 142 #define portTIN_NMI_NON_MASKABLE_INTERRUPT                                      0\r
 143 /*---------------------------------------------------------------------------*/\r
 144 \r
 145 void vMMUTrap( int iTrapIdentification ) __attribute__( ( longcall, weak ) );\r
 146 void vInternalProtectionTrap( int iTrapIdentification ) __attribute__( ( longcall, weak ) );\r
 147 void vInstructionErrorTrap( int iTrapIdentification ) __attribute__( ( longcall, weak ) );\r
 148 void vContextManagementTrap( int iTrapIdentification ) __attribute__( ( longcall, weak ) );\r
 149 void vSystemBusAndPeripheralsTrap( int iTrapIdentification ) __attribute__( ( longcall, weak ) );\r
 150 void vAssertionTrap( int iTrapIdentification ) __attribute__( ( longcall, weak ) );\r
 151 void vNonMaskableInterruptTrap( int iTrapIdentification ) __attribute__( ( longcall, weak ) );\r
 152 /*---------------------------------------------------------------------------*/\r
 153 \r
 154 void vTrapInstallHandlers( void )\r
 155 {\r
 156         if( 0 == _install_trap_handler ( portMMU_TRAP, vMMUTrap ) )\r
 157         {\r
 158                 _debug();\r
 159         }\r
 160 \r
 161         if( 0 == _install_trap_handler ( portIPT_TRAP, vInternalProtectionTrap ) )\r
 162         {\r
 163                 _debug();\r
 164         }\r
 165 \r
 166         if( 0 == _install_trap_handler ( portIE_TRAP, vInstructionErrorTrap ) )\r
 167         {\r
 168                 _debug();\r
 169         }\r
 170 \r
 171         if( 0 == _install_trap_handler ( portCM_TRAP, vContextManagementTrap ) )\r
 172         {\r
 173                 _debug();\r
 174         }\r
 175 \r
 176         if( 0 == _install_trap_handler ( portSBP_TRAP, vSystemBusAndPeripheralsTrap ) )\r
 177         {\r
 178                 _debug();\r
 179         }\r
 180 \r
 181         if( 0 == _install_trap_handler ( portASSERT_TRAP, vAssertionTrap ) )\r
 182         {\r
 183                 _debug();\r
 184         }\r
 185 \r
 186         if( 0 == _install_trap_handler ( portNMI_TRAP, vNonMaskableInterruptTrap ) )\r
 187         {\r
 188                 _debug();\r
 189         }\r
 190 }\r
 191 /*-----------------------------------------------------------*/\r
 192 \r
 193 void vMMUTrap( int iTrapIdentification )\r
 194 {\r
 195         switch( iTrapIdentification )\r
 196         {\r
 197         case portTIN_MMU_VIRTUAL_ADDRESS_FILL:\r
 198         case portTIN_MMU_VIRTUAL_ADDRESS_PROTECTION:\r
 199         default:\r
 200                 _debug();\r
 201                 break;\r
 202         }\r
 203 }\r
 204 /*---------------------------------------------------------------------------*/\r
 205 \r
 206 void vInternalProtectionTrap( int iTrapIdentification )\r
 207 {\r
 208         /* Deliberate fall through to default. */\r
 209         switch( iTrapIdentification )\r
 210         {\r
 211                 case portTIN_IPT_PRIVILIGED_INSTRUCTION:\r
 212                         /* Instruction is not allowed at current execution level, eg DISABLE at User-0. */\r
 213 \r
 214                 case portTIN_IPT_MEMORY_PROTECTION_READ:\r
 215                         /* Load word using invalid address. */\r
 216                         \r
 217                 case portTIN_IPT_MEMORY_PROTECTION_WRITE:\r
 218                         /* Store Word using invalid address. */\r
 219                         \r
 220                 case portTIN_IPT_MEMORY_PROTECTION_EXECUTION:\r
 221                         /* PC jumped to an address outside of the valid range. */\r
 222                         \r
 223                 case portTIN_IPT_MEMORY_PROTECTION_PERIPHERAL_ACCESS:\r
 224                         /* Access to a peripheral denied at current execution level. */\r
 225                         \r
 226                 case portTIN_IPT_MEMORY_PROTECTION_NULL_ADDRESS:\r
 227                         /* NULL Pointer. */\r
 228                         \r
 229                 case portTIN_IPT_MEMORY_PROTECTION_GLOBAL_REGISTER_WRITE_PROTECTION:\r
 230                         /* Tried to modify a global address pointer register. */\r
 231                         \r
 232                 default:\r
 233                 \r
 234                         pxCurrentTCB[ 0 ] = _mfcr( $PCXI );\r
 235                         _debug();\r
 236                         break;\r
 237         }\r
 238 }\r
 239 /*---------------------------------------------------------------------------*/\r
 240 \r
 241 void vInstructionErrorTrap( int iTrapIdentification )\r
 242 {\r
 243         /* Deliberate fall through to default. */\r
 244         switch( iTrapIdentification )\r
 245         {\r
 246                 case portTIN_IE_ILLEGAL_OPCODE:\r
 247                 case portTIN_IE_UNIMPLEMENTED_OPCODE:\r
 248                 case portTIN_IE_INVALID_OPERAND:\r
 249                 case portTIN_IE_DATA_ADDRESS_ALIGNMENT:\r
 250                 case portTIN_IE_INVALID_LOCAL_MEMORY_ADDRESS:\r
 251                 default:\r
 252                         _debug();\r
 253                         break;\r
 254         }\r
 255 }\r
 256 /*---------------------------------------------------------------------------*/\r
 257 \r
 258 void vContextManagementTrap( int iTrapIdentification )\r
 259 {\r
 260         /* Deliberate fall through to default. */\r
 261         switch( iTrapIdentification )\r
 262         {\r
 263                 case portTIN_CM_FREE_CONTEXT_LIST_DEPLETION:\r
 264                 case portTIN_CM_CALL_DEPTH_OVERFLOW:\r
 265                 case portTIN_CM_CALL_DEPTH_UNDEFLOW:\r
 266                 case portTIN_CM_FREE_CONTEXT_LIST_UNDERFLOW:\r
 267                 case portTIN_CM_CALL_STACK_UNDERFLOW:\r
 268                 case portTIN_CM_CONTEXT_TYPE:\r
 269                 case portTIN_CM_NESTING_ERROR:\r
 270                 default:\r
 271                         _debug();\r
 272                         break;\r
 273         }\r
 274 }\r
 275 /*---------------------------------------------------------------------------*/\r
 276 \r
 277 void vSystemBusAndPeripheralsTrap( int iTrapIdentification )\r
 278 {\r
 279         /* Deliberate fall through to default. */\r
 280         switch( iTrapIdentification )\r
 281         {\r
 282                 case portTIN_SBP_PROGRAM_FETCH_SYNCHRONOUS_ERROR:\r
 283                 case portTIN_SBP_DATA_ACCESS_SYNCHRONOUS_ERROR:\r
 284                 case portTIN_SBP_DATA_ACCESS_ASYNCHRONOUS_ERROR:\r
 285                 case portTIN_SBP_COPROCESSOR_TRAP_ASYNCHRONOUS_ERROR:\r
 286                 case portTIN_SBP_PROGRAM_MEMORY_INTEGRITY_ERROR:\r
 287                 case portTIN_SBP_DATA_MEMORY_INTEGRITY_ERROR:\r
 288                 default:\r
 289                         _debug();\r
 290                         break;\r
 291         }\r
 292 }\r
 293 /*---------------------------------------------------------------------------*/\r
 294 \r
 295 void vAssertionTrap( int iTrapIdentification )\r
 296 {\r
 297         /* Deliberate fall through to default. */\r
 298         switch( iTrapIdentification )\r
 299         {\r
 300                 case portTIN_ASSERT_ARITHMETIC_OVERFLOW:\r
 301                 case portTIN_ASSERT_STICKY_ARITHMETIC_OVERFLOW:\r
 302                 default:\r
 303                         _debug();\r
 304                         break;\r
 305         }\r
 306 }\r
 307 /*---------------------------------------------------------------------------*/\r
 308 \r
 309 void vNonMaskableInterruptTrap( int iTrapIdentification )\r
 310 {\r
 311         /* Deliberate fall through to default. */\r
 312         switch( iTrapIdentification )\r
 313         {\r
 314                 case portTIN_NMI_NON_MASKABLE_INTERRUPT:\r
 315                 default:\r
 316                         _debug();\r
 317                         break;\r
 318         }\r
 319 }\r
 320 /*---------------------------------------------------------------------------*/\r