2 * FreeRTOS Kernel V10.3.0
\r
3 * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
\r
5 * Permission is hereby granted, free of charge, to any person obtaining a copy of
\r
6 * this software and associated documentation files (the "Software"), to deal in
\r
7 * the Software without restriction, including without limitation the rights to
\r
8 * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
\r
9 * the Software, and to permit persons to whom the Software is furnished to do so,
\r
10 * subject to the following conditions:
\r
12 * The above copyright notice and this permission notice shall be included in all
\r
13 * copies or substantial portions of the Software.
\r
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
\r
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
\r
17 * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
\r
18 * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
\r
19 * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
\r
20 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
\r
22 * http://www.FreeRTOS.org
\r
23 * http://aws.amazon.com/freertos
\r
25 * 1 tab == 4 spaces!
\r
28 #include <FreeRTOSConfig.h>
\r
33 EXTERN vPortYieldFromISR
\r
35 EXTERN vTaskSwitchContext
\r
38 PUBLIC xPortPendSVHandler
\r
39 PUBLIC vPortSVCHandler
\r
40 PUBLIC vPortStartFirstTask
\r
41 PUBLIC ulSetInterruptMaskFromISR
\r
42 PUBLIC vClearInterruptMaskFromISR
\r
44 /*-----------------------------------------------------------*/
\r
50 /*-----------------------------------------------------------*/
\r
55 ldr r3, =pxCurrentTCB /* Get the location of the current TCB. */
\r
58 subs r0, r0, #32 /* Make space for the remaining low registers. */
\r
59 str r0, [r2] /* Save the new top of stack. */
\r
60 stmia r0!, {r4-r7} /* Store the low registers that are not saved automatically. */
\r
61 mov r4, r8 /* Store the high registers. */
\r
69 bl vTaskSwitchContext
\r
71 pop {r2, r3} /* lr goes in r3. r2 now holds tcb pointer. */
\r
74 ldr r0, [r1] /* The first item in pxCurrentTCB is the task top of stack. */
\r
75 adds r0, r0, #16 /* Move to the high registers. */
\r
76 ldmia r0!, {r4-r7} /* Pop the high registers. */
\r
82 msr psp, r0 /* Remember the new top of stack for the task. */
\r
84 subs r0, r0, #32 /* Go back for the low registers that are not automatically restored. */
\r
85 ldmia r0!, {r4-r7} /* Pop low registers. */
\r
89 /*-----------------------------------------------------------*/
\r
92 /* This function is no longer used, but retained for backward
\r
96 /*-----------------------------------------------------------*/
\r
99 /* The MSP stack is not reset as, unlike on M3/4 parts, there is no vector
\r
100 table offset register that can be used to locate the initial stack value.
\r
101 Not all M0 parts have the application vector table at address 0. */
\r
103 ldr r3, =pxCurrentTCB /* Obtain location of pxCurrentTCB. */
\r
105 ldr r0, [r1] /* The first item in pxCurrentTCB is the task top of stack. */
\r
106 adds r0, #32 /* Discard everything up to r0. */
\r
107 msr psp, r0 /* This is now the new top of stack to use in the task. */
\r
108 movs r0, #2 /* Switch to the psp stack. */
\r
111 pop {r0-r5} /* Pop the registers that are saved automatically. */
\r
112 mov lr, r5 /* lr is now in r5. */
\r
113 pop {r3} /* The return address is now in r3. */
\r
114 pop {r2} /* Pop and discard the XPSR. */
\r
115 cpsie i /* The first task has its context and interrupts can be enabled. */
\r
116 bx r3 /* Jump to the user defined task code. */
\r
118 /*-----------------------------------------------------------*/
\r
120 ulSetInterruptMaskFromISR
\r
125 /*-----------------------------------------------------------*/
\r
127 vClearInterruptMaskFromISR
\r