2 * FreeRTOS Kernel V10.2.0
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3 * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved.
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5 * Permission is hereby granted, free of charge, to any person obtaining a copy of
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6 * this software and associated documentation files (the "Software"), to deal in
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7 * the Software without restriction, including without limitation the rights to
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8 * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
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9 * the Software, and to permit persons to whom the Software is furnished to do so,
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10 * subject to the following conditions:
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12 * The above copyright notice and this permission notice shall be included in all
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13 * copies or substantial portions of the Software.
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15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
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17 * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
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18 * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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19 * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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20 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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22 * http://www.FreeRTOS.org
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23 * http://aws.amazon.com/freertos
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25 * 1 tab == 4 spaces!
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28 SECTION .text:CODE:NOROOT(2)
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31 PUBLIC SecureContext_LoadContextAsm
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32 PUBLIC SecureContext_SaveContextAsm
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34 #if ( configENABLE_FPU == 1 )
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35 #error Cortex-M23 does not have a Floating Point Unit (FPU) and therefore configENABLE_FPU must be set to 0.
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37 /*-----------------------------------------------------------*/
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39 SecureContext_LoadContextAsm:
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40 /* xSecureContextHandle value is in r0. */
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41 mrs r1, ipsr /* r1 = IPSR. */
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42 cbz r1, load_ctx_therad_mode /* Do nothing if the processor is running in the Thread Mode. */
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43 ldmia r0!, {r1, r2} /* r1 = xSecureContextHandle->pucCurrentStackPointer, r2 = xSecureContextHandle->pucStackLimit. */
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44 #if ( configENABLE_MPU == 1 )
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45 ldmia r1!, {r3} /* Read CONTROL register value from task's stack. r3 = CONTROL. */
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46 msr control, r3 /* CONTROL = r3. */
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47 #endif /* configENABLE_MPU */
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48 msr psplim, r2 /* PSPLIM = r2. */
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49 msr psp, r1 /* PSP = r1. */
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51 load_ctx_therad_mode:
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53 /*-----------------------------------------------------------*/
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55 SecureContext_SaveContextAsm:
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56 /* xSecureContextHandle value is in r0. */
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57 mrs r1, ipsr /* r1 = IPSR. */
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58 cbz r1, save_ctx_therad_mode /* Do nothing if the processor is running in the Thread Mode. */
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59 mrs r1, psp /* r1 = PSP. */
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60 #if ( configENABLE_MPU == 1 )
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61 mrs r2, control /* r2 = CONTROL. */
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62 subs r1, r1, #4 /* Make space for the CONTROL value on the stack. */
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63 str r1, [r0] /* Save the top of stack in context. xSecureContextHandle->pucCurrentStackPointer = r1. */
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64 stmia r1!, {r2} /* Store CONTROL value on the stack. */
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65 #else /* configENABLE_MPU */
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66 str r1, [r0] /* Save the top of stack in context. xSecureContextHandle->pucCurrentStackPointer = r1. */
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67 #endif /* configENABLE_MPU */
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68 movs r1, #0 /* r1 = securecontextNO_STACK. */
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69 msr psplim, r1 /* PSPLIM = securecontextNO_STACK. */
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70 msr psp, r1 /* PSP = securecontextNO_STACK i.e. No stack for thread mode until next task's context is loaded. */
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72 save_ctx_therad_mode:
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74 /*-----------------------------------------------------------*/
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