2 FreeRTOS V8.2.0rc1 - Copyright (C) 2014 Real Time Engineers Ltd.
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5 VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
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7 This file is part of the FreeRTOS distribution.
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9 FreeRTOS is free software; you can redistribute it and/or modify it under
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10 the terms of the GNU General Public License (version 2) as published by the
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11 Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.
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13 >>! NOTE: The modification to the GPL is included to allow you to !<<
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14 >>! distribute a combined work that includes FreeRTOS without being !<<
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15 >>! obliged to provide the source code for proprietary components !<<
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16 >>! outside of the FreeRTOS kernel. !<<
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18 FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
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19 WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
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20 FOR A PARTICULAR PURPOSE. Full license text is available on the following
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21 link: http://www.freertos.org/a00114.html
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25 ***************************************************************************
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27 * Having a problem? Start by reading the FAQ "My application does *
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28 * not run, what could be wrong?". Have you defined configASSERT()? *
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30 * http://www.FreeRTOS.org/FAQHelp.html *
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32 ***************************************************************************
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34 ***************************************************************************
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36 * FreeRTOS provides completely free yet professionally developed, *
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37 * robust, strictly quality controlled, supported, and cross *
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38 * platform software that is more than just the market leader, it *
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39 * is the industry's de facto standard. *
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41 * Help yourself get started quickly while simultaneously helping *
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42 * to support the FreeRTOS project by purchasing a FreeRTOS *
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43 * tutorial book, reference manual, or both: *
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44 * http://www.FreeRTOS.org/Documentation *
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46 ***************************************************************************
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48 ***************************************************************************
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50 * Investing in training allows your team to be as productive as *
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51 * possible as early as possible, lowering your overall development *
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52 * cost, and enabling you to bring a more robust product to market *
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53 * earlier than would otherwise be possible. Richard Barry is both *
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54 * the architect and key author of FreeRTOS, and so also the world's *
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55 * leading authority on what is the world's most popular real time *
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56 * kernel for deeply embedded MCU designs. Obtaining your training *
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57 * from Richard ensures your team will gain directly from his in-depth *
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58 * product knowledge and years of usage experience. Contact Real Time *
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59 * Engineers Ltd to enquire about the FreeRTOS Masterclass, presented *
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60 * by Richard Barry: http://www.FreeRTOS.org/contact
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62 ***************************************************************************
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64 ***************************************************************************
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66 * You are receiving this top quality software for free. Please play *
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67 * fair and reciprocate by reporting any suspected issues and *
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68 * participating in the community forum: *
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69 * http://www.FreeRTOS.org/support *
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73 ***************************************************************************
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75 http://www.FreeRTOS.org - Documentation, books, training, latest versions,
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76 license and Real Time Engineers Ltd. contact details.
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78 http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
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79 including FreeRTOS+Trace - an indispensable productivity tool, a DOS
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80 compatible FAT file system, and our tiny thread aware UDP/IP stack.
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82 http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.
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83 Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.
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85 http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High
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86 Integrity Systems ltd. to sell under the OpenRTOS brand. Low cost OpenRTOS
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87 licenses offer ticketed support, indemnification and commercial middleware.
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89 http://www.SafeRTOS.com - High Integrity Systems also provide a safety
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90 engineered and independently SIL3 certified version for use in safety and
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91 mission critical applications that require provable dependability.
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96 /*-----------------------------------------------------------
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97 * Implementation of functions defined in portable.h for the ARM CM3 port.
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98 *----------------------------------------------------------*/
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100 /* IAR includes. */
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101 #include <intrinsics.h>
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103 /* Scheduler includes. */
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104 #include "FreeRTOS.h"
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107 #if configMAX_SYSCALL_INTERRUPT_PRIORITY == 0
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108 #error configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0. See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html
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111 #ifndef configSYSTICK_CLOCK_HZ
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112 #define configSYSTICK_CLOCK_HZ configCPU_CLOCK_HZ
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113 /* Ensure the SysTick is clocked at the same frequency as the core. */
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114 #define portNVIC_SYSTICK_CLK_BIT ( 1UL << 2UL )
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116 /* The way the SysTick is clocked is not modified in case it is not the same
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118 #define portNVIC_SYSTICK_CLK_BIT ( 0 )
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121 /* Constants required to manipulate the core. Registers first... */
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122 #define portNVIC_SYSTICK_CTRL_REG ( * ( ( volatile uint32_t * ) 0xe000e010 ) )
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123 #define portNVIC_SYSTICK_LOAD_REG ( * ( ( volatile uint32_t * ) 0xe000e014 ) )
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124 #define portNVIC_SYSTICK_CURRENT_VALUE_REG ( * ( ( volatile uint32_t * ) 0xe000e018 ) )
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125 #define portNVIC_SYSPRI2_REG ( * ( ( volatile uint32_t * ) 0xe000ed20 ) )
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126 /* ...then bits in the registers. */
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127 #define portNVIC_SYSTICK_INT_BIT ( 1UL << 1UL )
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128 #define portNVIC_SYSTICK_ENABLE_BIT ( 1UL << 0UL )
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129 #define portNVIC_SYSTICK_COUNT_FLAG_BIT ( 1UL << 16UL )
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130 #define portNVIC_PENDSVCLEAR_BIT ( 1UL << 27UL )
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131 #define portNVIC_PEND_SYSTICK_CLEAR_BIT ( 1UL << 25UL )
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133 #define portNVIC_PENDSV_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL )
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134 #define portNVIC_SYSTICK_PRI ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL )
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136 /* Constants required to check the validity of an interrupt priority. */
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137 #define portFIRST_USER_INTERRUPT_NUMBER ( 16 )
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138 #define portNVIC_IP_REGISTERS_OFFSET_16 ( 0xE000E3F0 )
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139 #define portAIRCR_REG ( * ( ( volatile uint32_t * ) 0xE000ED0C ) )
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140 #define portMAX_8_BIT_VALUE ( ( uint8_t ) 0xff )
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141 #define portTOP_BIT_OF_BYTE ( ( uint8_t ) 0x80 )
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142 #define portMAX_PRIGROUP_BITS ( ( uint8_t ) 7 )
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143 #define portPRIORITY_GROUP_MASK ( 0x07UL << 8UL )
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144 #define portPRIGROUP_SHIFT ( 8UL )
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146 /* Masks off all bits but the VECTACTIVE bits in the ICSR register. */
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147 #define portVECTACTIVE_MASK ( 0xFFUL )
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149 /* Constants required to set up the initial stack. */
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150 #define portINITIAL_XPSR ( 0x01000000 )
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152 /* The systick is a 24-bit counter. */
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153 #define portMAX_24_BIT_NUMBER ( 0xffffffUL )
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155 /* A fiddle factor to estimate the number of SysTick counts that would have
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156 occurred while the SysTick counter is stopped during tickless idle
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158 #define portMISSED_COUNTS_FACTOR ( 45UL )
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160 /* For backward compatibility, ensure configKERNEL_INTERRUPT_PRIORITY is
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161 defined. The value 255 should also ensure backward compatibility.
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162 FreeRTOS.org versions prior to V4.3.0 did not include this definition. */
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163 #ifndef configKERNEL_INTERRUPT_PRIORITY
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164 #define configKERNEL_INTERRUPT_PRIORITY 255
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167 /* Each task maintains its own interrupt status in the critical nesting
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169 static UBaseType_t uxCriticalNesting = 0xaaaaaaaa;
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172 * Setup the timer to generate the tick interrupts. The implementation in this
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173 * file is weak to allow application writers to change the timer used to
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174 * generate the tick interrupt.
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176 void vPortSetupTimerInterrupt( void );
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179 * Exception handlers.
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181 void xPortSysTickHandler( void );
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184 * Start first task is a separate function so it can be tested in isolation.
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186 extern void vPortStartFirstTask( void );
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189 * Used to catch tasks that attempt to return from their implementing function.
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191 static void prvTaskExitError( void );
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193 /*-----------------------------------------------------------*/
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196 * The number of SysTick increments that make up one tick period.
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198 #if configUSE_TICKLESS_IDLE == 1
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199 static uint32_t ulTimerCountsForOneTick = 0;
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200 #endif /* configUSE_TICKLESS_IDLE */
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203 * The maximum number of tick periods that can be suppressed is limited by the
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204 * 24 bit resolution of the SysTick timer.
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206 #if configUSE_TICKLESS_IDLE == 1
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207 static uint32_t xMaximumPossibleSuppressedTicks = 0;
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208 #endif /* configUSE_TICKLESS_IDLE */
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211 * Compensate for the CPU cycles that pass while the SysTick is stopped (low
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212 * power functionality only.
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214 #if configUSE_TICKLESS_IDLE == 1
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215 static uint32_t ulStoppedTimerCompensation = 0;
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216 #endif /* configUSE_TICKLESS_IDLE */
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219 * Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure
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220 * FreeRTOS API functions are not called from interrupts that have been assigned
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221 * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY.
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223 #if ( configASSERT_DEFINED == 1 )
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224 static uint8_t ucMaxSysCallPriority = 0;
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225 static uint32_t ulMaxPRIGROUPValue = 0;
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226 static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const volatile uint8_t * const ) portNVIC_IP_REGISTERS_OFFSET_16;
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227 #endif /* configASSERT_DEFINED */
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229 /*-----------------------------------------------------------*/
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232 * See header file for description.
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234 StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
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236 /* Simulate the stack frame as it would be created by a context switch
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238 pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
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239 *pxTopOfStack = portINITIAL_XPSR; /* xPSR */
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241 *pxTopOfStack = ( StackType_t ) pxCode; /* PC */
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243 *pxTopOfStack = ( StackType_t ) prvTaskExitError; /* LR */
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244 pxTopOfStack -= 5; /* R12, R3, R2 and R1. */
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245 *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
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246 pxTopOfStack -= 8; /* R11, R10, R9, R8, R7, R6, R5 and R4. */
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248 return pxTopOfStack;
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250 /*-----------------------------------------------------------*/
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252 static void prvTaskExitError( void )
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254 /* A function that implements a task must not exit or attempt to return to
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255 its caller as there is nothing to return to. If a task wants to exit it
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256 should instead call vTaskDelete( NULL ).
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258 Artificially force an assert() to be triggered if configASSERT() is
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259 defined, then stop here so application writers can catch the error. */
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260 configASSERT( uxCriticalNesting == ~0UL );
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261 portDISABLE_INTERRUPTS();
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264 /*-----------------------------------------------------------*/
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267 * See header file for description.
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269 BaseType_t xPortStartScheduler( void )
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271 #if( configASSERT_DEFINED == 1 )
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273 volatile uint32_t ulOriginalPriority;
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274 volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER );
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275 volatile uint8_t ucMaxPriorityValue;
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277 /* Determine the maximum priority from which ISR safe FreeRTOS API
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278 functions can be called. ISR safe functions are those that end in
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279 "FromISR". FreeRTOS maintains separate thread and ISR API functions to
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280 ensure interrupt entry is as fast and simple as possible.
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282 Save the interrupt priority value that is about to be clobbered. */
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283 ulOriginalPriority = *pucFirstUserPriorityRegister;
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285 /* Determine the number of priority bits available. First write to all
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287 *pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;
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289 /* Read the value back to see how many bits stuck. */
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290 ucMaxPriorityValue = *pucFirstUserPriorityRegister;
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292 /* Use the same mask on the maximum system call priority. */
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293 ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;
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295 /* Calculate the maximum acceptable priority group value for the number
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296 of bits read back. */
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297 ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;
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298 while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
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300 ulMaxPRIGROUPValue--;
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301 ucMaxPriorityValue <<= ( uint8_t ) 0x01;
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304 /* Shift the priority group value back to its position within the AIRCR
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306 ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;
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307 ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;
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309 /* Restore the clobbered interrupt priority register to its original
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311 *pucFirstUserPriorityRegister = ulOriginalPriority;
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313 #endif /* conifgASSERT_DEFINED */
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315 /* Make PendSV and SysTick the lowest priority interrupts. */
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316 portNVIC_SYSPRI2_REG |= portNVIC_PENDSV_PRI;
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317 portNVIC_SYSPRI2_REG |= portNVIC_SYSTICK_PRI;
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319 /* Start the timer that generates the tick ISR. Interrupts are disabled
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321 vPortSetupTimerInterrupt();
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323 /* Initialise the critical nesting count ready for the first task. */
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324 uxCriticalNesting = 0;
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326 /* Start the first task. */
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327 vPortStartFirstTask();
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329 /* Should not get here! */
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332 /*-----------------------------------------------------------*/
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334 void vPortEndScheduler( void )
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336 /* Not implemented in ports where there is nothing to return to.
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337 Artificially force an assert. */
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338 configASSERT( uxCriticalNesting == 1000UL );
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340 /*-----------------------------------------------------------*/
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342 void vPortYield( void )
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344 /* Set a PendSV to request a context switch. */
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345 portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
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347 /* Barriers are normally not required but do ensure the code is completely
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348 within the specified behaviour for the architecture. */
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352 /*-----------------------------------------------------------*/
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354 void vPortEnterCritical( void )
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356 portDISABLE_INTERRUPTS();
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357 uxCriticalNesting++;
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361 /* This is not the interrupt safe version of the enter critical function so
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362 assert() if it is being called from an interrupt context. Only API
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363 functions that end in "FromISR" can be used in an interrupt. Only assert if
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364 the critical nesting count is 1 to protect against recursive calls if the
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365 assert function also uses a critical section. */
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366 if( uxCriticalNesting == 1 )
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368 configASSERT( ( portNVIC_INT_CTRL_REG & portVECTACTIVE_MASK ) == 0 );
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371 /*-----------------------------------------------------------*/
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373 void vPortExitCritical( void )
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375 configASSERT( uxCriticalNesting );
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376 uxCriticalNesting--;
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377 if( uxCriticalNesting == 0 )
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379 portENABLE_INTERRUPTS();
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382 /*-----------------------------------------------------------*/
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384 void xPortSysTickHandler( void )
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386 /* The SysTick runs at the lowest interrupt priority, so when this interrupt
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387 executes all interrupts must be unmasked. There is therefore no need to
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388 save and then restore the interrupt mask value as its value is already
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390 ( void ) portSET_INTERRUPT_MASK_FROM_ISR();
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392 /* Increment the RTOS tick. */
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393 if( xTaskIncrementTick() != pdFALSE )
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395 /* A context switch is required. Context switching is performed in
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396 the PendSV interrupt. Pend the PendSV interrupt. */
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397 portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
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400 portCLEAR_INTERRUPT_MASK_FROM_ISR( 0 );
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402 /*-----------------------------------------------------------*/
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404 #if configUSE_TICKLESS_IDLE == 1
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406 __weak void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )
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408 uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements, ulSysTickCTRL;
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409 TickType_t xModifiableIdleTime;
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411 /* Make sure the SysTick reload value does not overflow the counter. */
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412 if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks )
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414 xExpectedIdleTime = xMaximumPossibleSuppressedTicks;
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417 /* Stop the SysTick momentarily. The time the SysTick is stopped for
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418 is accounted for as best it can be, but using the tickless mode will
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419 inevitably result in some tiny drift of the time maintained by the
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420 kernel with respect to calendar time. */
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421 portNVIC_SYSTICK_CTRL_REG &= ~portNVIC_SYSTICK_ENABLE_BIT;
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423 /* Calculate the reload value required to wait xExpectedIdleTime
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424 tick periods. -1 is used because this code will execute part way
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425 through one of the tick periods. */
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426 ulReloadValue = portNVIC_SYSTICK_CURRENT_VALUE_REG + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) );
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427 if( ulReloadValue > ulStoppedTimerCompensation )
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429 ulReloadValue -= ulStoppedTimerCompensation;
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432 /* Enter a critical section but don't use the taskENTER_CRITICAL()
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433 method as that will mask interrupts that should exit sleep mode. */
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434 __disable_interrupt();
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436 /* If a context switch is pending or a task is waiting for the scheduler
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437 to be unsuspended then abandon the low power entry. */
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438 if( eTaskConfirmSleepModeStatus() == eAbortSleep )
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440 /* Restart from whatever is left in the count register to complete
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441 this tick period. */
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442 portNVIC_SYSTICK_LOAD_REG = portNVIC_SYSTICK_CURRENT_VALUE_REG;
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444 /* Restart SysTick. */
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445 portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
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447 /* Reset the reload register to the value required for normal tick
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449 portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
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451 /* Re-enable interrupts - see comments above __disable_interrupt()
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453 __enable_interrupt();
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457 /* Set the new reload value. */
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458 portNVIC_SYSTICK_LOAD_REG = ulReloadValue;
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460 /* Clear the SysTick count flag and set the count value back to
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462 portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
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464 /* Restart SysTick. */
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465 portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
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467 /* Sleep until something happens. configPRE_SLEEP_PROCESSING() can
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468 set its parameter to 0 to indicate that its implementation contains
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469 its own wait for interrupt or wait for event instruction, and so wfi
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470 should not be executed again. However, the original expected idle
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471 time variable must remain unmodified, so a copy is taken. */
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472 xModifiableIdleTime = xExpectedIdleTime;
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473 configPRE_SLEEP_PROCESSING( xModifiableIdleTime );
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474 if( xModifiableIdleTime > 0 )
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480 configPOST_SLEEP_PROCESSING( xExpectedIdleTime );
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482 /* Stop SysTick. Again, the time the SysTick is stopped for is
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483 accounted for as best it can be, but using the tickless mode will
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484 inevitably result in some tiny drift of the time maintained by the
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485 kernel with respect to calendar time. */
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486 ulSysTickCTRL = portNVIC_SYSTICK_CTRL_REG;
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487 portNVIC_SYSTICK_CTRL_REG = ( ulSysTickCTRL & ~portNVIC_SYSTICK_ENABLE_BIT );
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489 /* Re-enable interrupts - see comments above __disable_interrupt()
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491 __enable_interrupt();
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493 if( ( ulSysTickCTRL & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )
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495 uint32_t ulCalculatedLoadValue;
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497 /* The tick interrupt has already executed, and the SysTick
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498 count reloaded with ulReloadValue. Reset the
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499 portNVIC_SYSTICK_LOAD_REG with whatever remains of this tick
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501 ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG );
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503 /* Don't allow a tiny value, or values that have somehow
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504 underflowed because the post sleep hook did something
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505 that took too long. */
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506 if( ( ulCalculatedLoadValue < ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) )
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508 ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL );
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511 portNVIC_SYSTICK_LOAD_REG = ulCalculatedLoadValue;
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513 /* The tick interrupt handler will already have pended the tick
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514 processing in the kernel. As the pending tick will be
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515 processed as soon as this function exits, the tick value
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516 maintained by the tick is stepped forward by one less than the
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517 time spent waiting. */
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518 ulCompleteTickPeriods = xExpectedIdleTime - 1UL;
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522 /* Something other than the tick interrupt ended the sleep.
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523 Work out how long the sleep lasted rounded to complete tick
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524 periods (not the ulReload value which accounted for part
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526 ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - portNVIC_SYSTICK_CURRENT_VALUE_REG;
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528 /* How many complete tick periods passed while the processor
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530 ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick;
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532 /* The reload value is set to whatever fraction of a single tick
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534 portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1 ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements;
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537 /* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG
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538 again, then set portNVIC_SYSTICK_LOAD_REG back to its standard
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539 value. The critical section is used to ensure the tick interrupt
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540 can only execute once in the case that the reload register is near
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542 portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
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543 portENTER_CRITICAL();
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545 portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
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546 vTaskStepTick( ulCompleteTickPeriods );
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547 portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
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549 portEXIT_CRITICAL();
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553 #endif /* #if configUSE_TICKLESS_IDLE */
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554 /*-----------------------------------------------------------*/
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557 * Setup the systick timer to generate the tick interrupts at the required
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560 __weak void vPortSetupTimerInterrupt( void )
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562 /* Calculate the constants required to configure the tick interrupt. */
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563 #if configUSE_TICKLESS_IDLE == 1
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565 ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ );
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566 xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick;
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567 ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ );
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569 #endif /* configUSE_TICKLESS_IDLE */
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571 /* Configure SysTick to interrupt at the requested rate. */
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572 portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
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573 portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT );
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575 /*-----------------------------------------------------------*/
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577 #if( configASSERT_DEFINED == 1 )
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579 void vPortValidateInterruptPriority( void )
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581 uint32_t ulCurrentInterrupt;
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582 uint8_t ucCurrentPriority;
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584 /* Obtain the number of the currently executing interrupt. */
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585 __asm volatile( "mrs %0, ipsr" : "=r"( ulCurrentInterrupt ) );
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587 /* Is the interrupt number a user defined interrupt? */
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588 if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER )
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590 /* Look up the interrupt's priority. */
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591 ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ];
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593 /* The following assertion will fail if a service routine (ISR) for
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594 an interrupt that has been assigned a priority above
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595 configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API
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596 function. ISR safe FreeRTOS API functions must *only* be called
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597 from interrupts that have been assigned a priority at or below
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598 configMAX_SYSCALL_INTERRUPT_PRIORITY.
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600 Numerically low interrupt priority numbers represent logically high
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601 interrupt priorities, therefore the priority of the interrupt must
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602 be set to a value equal to or numerically *higher* than
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603 configMAX_SYSCALL_INTERRUPT_PRIORITY.
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605 Interrupts that use the FreeRTOS API must not be left at their
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606 default priority of zero as that is the highest possible priority,
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607 which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY,
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608 and therefore also guaranteed to be invalid.
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610 FreeRTOS maintains separate thread and ISR API functions to ensure
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611 interrupt entry is as fast and simple as possible.
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613 The following links provide detailed information:
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614 http://www.freertos.org/RTOS-Cortex-M3-M4.html
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615 http://www.freertos.org/FAQHelp.html */
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616 configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );
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619 /* Priority grouping: The interrupt controller (NVIC) allows the bits
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620 that define each interrupt's priority to be split between bits that
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621 define the interrupt's pre-emption priority bits and bits that define
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622 the interrupt's sub-priority. For simplicity all bits must be defined
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623 to be pre-emption priority bits. The following assertion will fail if
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624 this is not the case (if some bits represent a sub-priority).
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626 If the application only uses CMSIS libraries for interrupt
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627 configuration then the correct setting can be achieved on all Cortex-M
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628 devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the
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629 scheduler. Note however that some vendor specific peripheral libraries
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630 assume a non-zero priority group setting, in which cases using a value
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631 of zero will result in unpredicable behaviour. */
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632 configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );
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635 #endif /* configASSERT_DEFINED */
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