git.sur5r.net Git - freertos/blob - FreeRTOS/Source/portable/IAR/ARM_CM33/non_secure/port.c

   1 /*\r
   2  * FreeRTOS Kernel V10.2.1\r
   3  * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\r
   4  *\r
   5  * Permission is hereby granted, free of charge, to any person obtaining a copy of\r
   6  * this software and associated documentation files (the "Software"), to deal in\r
   7  * the Software without restriction, including without limitation the rights to\r
   8  * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\r
   9  * the Software, and to permit persons to whom the Software is furnished to do so,\r
  10  * subject to the following conditions:\r
  11  *\r
  12  * The above copyright notice and this permission notice shall be included in all\r
  13  * copies or substantial portions of the Software.\r
  14  *\r
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\r
  17  * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\r
  18  * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r
  19  * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
  20  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
  21  *\r
  22  * http://www.FreeRTOS.org\r
  23  * http://aws.amazon.com/freertos\r
  24  *\r
  25  * 1 tab == 4 spaces!\r
  26  */\r
  27 \r
  28 /* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining\r
  29  * all the API functions to use the MPU wrappers. That should only be done when\r
  30  * task.h is included from an application file. */\r
  31 #define MPU_WRAPPERS_INCLUDED_FROM_API_FILE\r
  32 \r
  33 /* Scheduler includes. */\r
  34 #include "FreeRTOS.h"\r
  35 #include "task.h"\r
  36 \r
  37 /* MPU wrappers includes. */\r
  38 #include "mpu_wrappers.h"\r
  39 \r
  40 /* Portasm includes. */\r
  41 #include "portasm.h"\r
  42 \r
  43 #if( configENABLE_TRUSTZONE == 1 )\r
  44         /* Secure components includes. */\r
  45         #include "secure_context.h"\r
  46         #include "secure_init.h"\r
  47 #endif /* configENABLE_TRUSTZONE */\r
  48 \r
  49 #undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE\r
  50 \r
  51 /**\r
  52  * The FreeRTOS Cortex M33 port can be configured to run on the Secure Side only\r
  53  * i.e. the processor boots as secure and never jumps to the non-secure side.\r
  54  * The Trust Zone support in the port must be disabled in order to run FreeRTOS\r
  55  * on the secure side. The following are the valid configuration seetings:\r
  56  *\r
  57  * 1. Run FreeRTOS on the Secure Side:\r
  58  *              configRUN_FREERTOS_SECURE_ONLY = 1 and configENABLE_TRUSTZONE = 0\r
  59  *\r
  60  * 2. Run FreeRTOS on the Non-Secure Side with Secure Side function call support:\r
  61  *              configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 1\r
  62  *\r
  63  * 3. Run FreeRTOS on the Non-Secure Side only i.e. no Secure Side function call support:\r
  64  *              configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 0\r
  65  */\r
  66 #if( ( configRUN_FREERTOS_SECURE_ONLY == 1 ) && ( configENABLE_TRUSTZONE == 1 ) )\r
  67         #error TrustZone needs to be disabled in order to run FreeRTOS on the Secure Side.\r
  68 #endif\r
  69 /*-----------------------------------------------------------*/\r
  70 \r
  71 /**\r
  72  * @brief Constants required to manipulate the NVIC.\r
  73  */\r
  74 #define portNVIC_SYSTICK_CTRL                           ( ( volatile uint32_t * ) 0xe000e010 )\r
  75 #define portNVIC_SYSTICK_LOAD                           ( ( volatile uint32_t * ) 0xe000e014 )\r
  76 #define portNVIC_SYSTICK_CURRENT_VALUE          ( ( volatile uint32_t * ) 0xe000e018 )\r
  77 #define portNVIC_INT_CTRL                                       ( ( volatile uint32_t * ) 0xe000ed04 )\r
  78 #define portNVIC_SYSPRI2                                        ( ( volatile uint32_t * ) 0xe000ed20 )\r
  79 #define portNVIC_SYSTICK_CLK                            ( 0x00000004 )\r
  80 #define portNVIC_SYSTICK_INT                            ( 0x00000002 )\r
  81 #define portNVIC_SYSTICK_ENABLE                         ( 0x00000001 )\r
  82 #define portNVIC_PENDSVSET                                      ( 0x10000000 )\r
  83 #define portMIN_INTERRUPT_PRIORITY                      ( 255UL )\r
  84 #define portNVIC_PENDSV_PRI                                     ( portMIN_INTERRUPT_PRIORITY << 16UL )\r
  85 #define portNVIC_SYSTICK_PRI                            ( portMIN_INTERRUPT_PRIORITY << 24UL )\r
  86 /*-----------------------------------------------------------*/\r
  87 \r
  88 /**\r
  89  * @brief Constants required to manipulate the SCB.\r
  90  */\r
  91 #define portSCB_SYS_HANDLER_CTRL_STATE_REG      ( * ( volatile uint32_t * ) 0xe000ed24 )\r
  92 #define portSCB_MEM_FAULT_ENABLE                        ( 1UL << 16UL )\r
  93 /*-----------------------------------------------------------*/\r
  94 \r
  95 /**\r
  96  * @brief Constants required to manipulate the FPU.\r
  97  */\r
  98 #define portCPACR                                                       ( ( volatile uint32_t * ) 0xe000ed88 )  /* Coprocessor Access Control Register. */\r
  99 #define portCPACR_CP10_VALUE                            ( 3UL )\r
 100 #define portCPACR_CP11_VALUE                            portCPACR_CP10_VALUE\r
 101 #define portCPACR_CP10_POS                                      ( 20UL )\r
 102 #define portCPACR_CP11_POS                                      ( 22UL )\r
 103 \r
 104 #define portFPCCR                                                       ( ( volatile uint32_t * ) 0xe000ef34 )  /* Floating Point Context Control Register. */\r
 105 #define portFPCCR_ASPEN_POS                                     ( 31UL )\r
 106 #define portFPCCR_ASPEN_MASK                            ( 1UL << portFPCCR_ASPEN_POS )\r
 107 #define portFPCCR_LSPEN_POS                                     ( 30UL )\r
 108 #define portFPCCR_LSPEN_MASK                            ( 1UL << portFPCCR_LSPEN_POS )\r
 109 /*-----------------------------------------------------------*/\r
 110 \r
 111 /**\r
 112  * @brief Constants required to manipulate the MPU.\r
 113  */\r
 114 #define portMPU_TYPE_REG                                        ( * ( ( volatile uint32_t * ) 0xe000ed90 ) )\r
 115 #define portMPU_CTRL_REG                                        ( * ( ( volatile uint32_t * ) 0xe000ed94 ) )\r
 116 #define portMPU_RNR_REG                                         ( * ( ( volatile uint32_t * ) 0xe000ed98 ) )\r
 117 \r
 118 #define portMPU_RBAR_REG                                        ( * ( ( volatile uint32_t * ) 0xe000ed9c ) )\r
 119 #define portMPU_RLAR_REG                                        ( * ( ( volatile uint32_t * ) 0xe000eda0 ) )\r
 120 \r
 121 #define portMPU_RBAR_A1_REG                                     ( * ( ( volatile uint32_t * ) 0xe000eda4 ) )\r
 122 #define portMPU_RLAR_A1_REG                                     ( * ( ( volatile uint32_t * ) 0xe000eda8 ) )\r
 123 \r
 124 #define portMPU_RBAR_A2_REG                                     ( * ( ( volatile uint32_t * ) 0xe000edac ) )\r
 125 #define portMPU_RLAR_A2_REG                                     ( * ( ( volatile uint32_t * ) 0xe000edb0 ) )\r
 126 \r
 127 #define portMPU_RBAR_A3_REG                                     ( * ( ( volatile uint32_t * ) 0xe000edb4 ) )\r
 128 #define portMPU_RLAR_A3_REG                                     ( * ( ( volatile uint32_t * ) 0xe000edb8 ) )\r
 129 \r
 130 #define portMPU_MAIR0_REG                                       ( * ( ( volatile uint32_t * ) 0xe000edc0 ) )\r
 131 #define portMPU_MAIR1_REG                                       ( * ( ( volatile uint32_t * ) 0xe000edc4 ) )\r
 132 \r
 133 #define portMPU_RBAR_ADDRESS_MASK                       ( 0xffffffe0 ) /* Must be 32-byte aligned. */\r
 134 #define portMPU_RLAR_ADDRESS_MASK                       ( 0xffffffe0 ) /* Must be 32-byte aligned. */\r
 135 \r
 136 #define portMPU_MAIR_ATTR0_POS                          ( 0UL )\r
 137 #define portMPU_MAIR_ATTR0_MASK                         ( 0x000000ff )\r
 138 \r
 139 #define portMPU_MAIR_ATTR1_POS                          ( 8UL )\r
 140 #define portMPU_MAIR_ATTR1_MASK                         ( 0x0000ff00 )\r
 141 \r
 142 #define portMPU_MAIR_ATTR2_POS                          ( 16UL )\r
 143 #define portMPU_MAIR_ATTR2_MASK                         ( 0x00ff0000 )\r
 144 \r
 145 #define portMPU_MAIR_ATTR3_POS                          ( 24UL )\r
 146 #define portMPU_MAIR_ATTR3_MASK                         ( 0xff000000 )\r
 147 \r
 148 #define portMPU_MAIR_ATTR4_POS                          ( 0UL )\r
 149 #define portMPU_MAIR_ATTR4_MASK                         ( 0x000000ff )\r
 150 \r
 151 #define portMPU_MAIR_ATTR5_POS                          ( 8UL )\r
 152 #define portMPU_MAIR_ATTR5_MASK                         ( 0x0000ff00 )\r
 153 \r
 154 #define portMPU_MAIR_ATTR6_POS                          ( 16UL )\r
 155 #define portMPU_MAIR_ATTR6_MASK                         ( 0x00ff0000 )\r
 156 \r
 157 #define portMPU_MAIR_ATTR7_POS                          ( 24UL )\r
 158 #define portMPU_MAIR_ATTR7_MASK                         ( 0xff000000 )\r
 159 \r
 160 #define portMPU_RLAR_ATTR_INDEX0                        ( 0UL << 1UL )\r
 161 #define portMPU_RLAR_ATTR_INDEX1                        ( 1UL << 1UL )\r
 162 #define portMPU_RLAR_ATTR_INDEX2                        ( 2UL << 1UL )\r
 163 #define portMPU_RLAR_ATTR_INDEX3                        ( 3UL << 1UL )\r
 164 #define portMPU_RLAR_ATTR_INDEX4                        ( 4UL << 1UL )\r
 165 #define portMPU_RLAR_ATTR_INDEX5                        ( 5UL << 1UL )\r
 166 #define portMPU_RLAR_ATTR_INDEX6                        ( 6UL << 1UL )\r
 167 #define portMPU_RLAR_ATTR_INDEX7                        ( 7UL << 1UL )\r
 168 \r
 169 #define portMPU_RLAR_REGION_ENABLE                      ( 1UL )\r
 170 \r
 171 /* Enable privileged access to unmapped region. */\r
 172 #define portMPU_PRIV_BACKGROUND_ENABLE          ( 1UL << 2UL )\r
 173 \r
 174 /* Enable MPU. */\r
 175 #define portMPU_ENABLE                                          ( 1UL << 0UL )\r
 176 \r
 177 /* Expected value of the portMPU_TYPE register. */\r
 178 #define portEXPECTED_MPU_TYPE_VALUE                     ( 8UL << 8UL ) /* 8 regions, unified. */\r
 179 /*-----------------------------------------------------------*/\r
 180 \r
 181 /**\r
 182  * @brief Constants required to set up the initial stack.\r
 183  */\r
 184 #define portINITIAL_XPSR                                        ( 0x01000000 )\r
 185 \r
 186 #if( configRUN_FREERTOS_SECURE_ONLY == 1 )\r
 187         /**\r
 188          * @brief Initial EXC_RETURN value.\r
 189          *\r
 190          *     FF         FF         FF         FD\r
 191          * 1111 1111  1111 1111  1111 1111  1111 1101\r
 192          *\r
 193          * Bit[6] - 1 --> The exception was taken from the Secure state.\r
 194          * Bit[5] - 1 --> Do not skip stacking of additional state context.\r
 195          * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.\r
 196          * Bit[3] - 1 --> Return to the Thread mode.\r
 197          * Bit[2] - 1 --> Restore registers from the process stack.\r
 198          * Bit[1] - 0 --> Reserved, 0.\r
 199          * Bit[0] - 1 --> The exception was taken to the Secure state.\r
 200          */\r
 201         #define portINITIAL_EXC_RETURN                  ( 0xfffffffd )\r
 202 #else\r
 203         /**\r
 204          * @brief Initial EXC_RETURN value.\r
 205          *\r
 206          *     FF         FF         FF         BC\r
 207          * 1111 1111  1111 1111  1111 1111  1011 1100\r
 208          *\r
 209          * Bit[6] - 0 --> The exception was taken from the Non-Secure state.\r
 210          * Bit[5] - 1 --> Do not skip stacking of additional state context.\r
 211          * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.\r
 212          * Bit[3] - 1 --> Return to the Thread mode.\r
 213          * Bit[2] - 1 --> Restore registers from the process stack.\r
 214          * Bit[1] - 0 --> Reserved, 0.\r
 215          * Bit[0] - 0 --> The exception was taken to the Non-Secure state.\r
 216          */\r
 217         #define portINITIAL_EXC_RETURN                  ( 0xffffffbc )\r
 218 #endif /* configRUN_FREERTOS_SECURE_ONLY */\r
 219 \r
 220 /**\r
 221  * @brief CONTROL register privileged bit mask.\r
 222  *\r
 223  * Bit[0] in CONTROL register tells the privilege:\r
 224  *  Bit[0] = 0 ==> The task is privileged.\r
 225  *  Bit[0] = 1 ==> The task is not privileged.\r
 226  */\r
 227 #define portCONTROL_PRIVILEGED_MASK                     ( 1UL << 0UL )\r
 228 \r
 229 /**\r
 230  * @brief Initial CONTROL register values.\r
 231  */\r
 232 #define portINITIAL_CONTROL_UNPRIVILEGED        ( 0x3 )\r
 233 #define portINITIAL_CONTROL_PRIVILEGED          ( 0x2 )\r
 234 \r
 235 /**\r
 236  * @brief Let the user override the pre-loading of the initial LR with the\r
 237  * address of prvTaskExitError() in case it messes up unwinding of the stack\r
 238  * in the debugger.\r
 239  */\r
 240 #ifdef configTASK_RETURN_ADDRESS\r
 241         #define portTASK_RETURN_ADDRESS                 configTASK_RETURN_ADDRESS\r
 242 #else\r
 243         #define portTASK_RETURN_ADDRESS                 prvTaskExitError\r
 244 #endif\r
 245 \r
 246 /**\r
 247  * @brief If portPRELOAD_REGISTERS then registers will be given an initial value\r
 248  * when a task is created. This helps in debugging at the cost of code size.\r
 249  */\r
 250 #define portPRELOAD_REGISTERS                           1\r
 251 \r
 252 /**\r
 253  * @brief A task is created without a secure context, and must call\r
 254  * portALLOCATE_SECURE_CONTEXT() to give itself a secure context before it makes\r
 255  * any secure calls.\r
 256  */\r
 257 #define portNO_SECURE_CONTEXT                           0\r
 258 /*-----------------------------------------------------------*/\r
 259 \r
 260 /**\r
 261  * @brief Used to catch tasks that attempt to return from their implementing\r
 262  * function.\r
 263  */\r
 264 static void prvTaskExitError( void );\r
 265 \r
 266 #if( configENABLE_MPU == 1 )\r
 267         /**\r
 268          * @brief Setup the Memory Protection Unit (MPU).\r
 269          */\r
 270         static void prvSetupMPU( void ) PRIVILEGED_FUNCTION;\r
 271 #endif /* configENABLE_MPU */\r
 272 \r
 273 #if( configENABLE_FPU == 1 )\r
 274         /**\r
 275          * @brief Setup the Floating Point Unit (FPU).\r
 276          */\r
 277         static void prvSetupFPU( void ) PRIVILEGED_FUNCTION;\r
 278 #endif /* configENABLE_FPU */\r
 279 \r
 280 /**\r
 281  * @brief Setup the timer to generate the tick interrupts.\r
 282  *\r
 283  * The implementation in this file is weak to allow application writers to\r
 284  * change the timer used to generate the tick interrupt.\r
 285  */\r
 286 void vPortSetupTimerInterrupt( void ) PRIVILEGED_FUNCTION;\r
 287 \r
 288 /**\r
 289  * @brief Checks whether the current execution context is interrupt.\r
 290  *\r
 291  * @return pdTRUE if the current execution context is interrupt, pdFALSE\r
 292  * otherwise.\r
 293  */\r
 294 BaseType_t xPortIsInsideInterrupt( void );\r
 295 \r
 296 /**\r
 297  * @brief Yield the processor.\r
 298  */\r
 299 void vPortYield( void ) PRIVILEGED_FUNCTION;\r
 300 \r
 301 /**\r
 302  * @brief Enter critical section.\r
 303  */\r
 304 void vPortEnterCritical( void ) PRIVILEGED_FUNCTION;\r
 305 \r
 306 /**\r
 307  * @brief Exit from critical section.\r
 308  */\r
 309 void vPortExitCritical( void ) PRIVILEGED_FUNCTION;\r
 310 \r
 311 /**\r
 312  * @brief SysTick handler.\r
 313  */\r
 314 void SysTick_Handler( void ) PRIVILEGED_FUNCTION;\r
 315 \r
 316 /**\r
 317  * @brief C part of SVC handler.\r
 318  */\r
 319 portDONT_DISCARD void vPortSVCHandler_C( uint32_t *pulCallerStackAddress ) PRIVILEGED_FUNCTION;\r
 320 /*-----------------------------------------------------------*/\r
 321 \r
 322 /**\r
 323  * @brief Each task maintains its own interrupt status in the critical nesting\r
 324  * variable.\r
 325  */\r
 326 static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL;\r
 327 \r
 328 #if( configENABLE_TRUSTZONE == 1 )\r
 329         /**\r
 330          * @brief Saved as part of the task context to indicate which context the\r
 331          * task is using on the secure side.\r
 332          */\r
 333         portDONT_DISCARD volatile SecureContextHandle_t xSecureContext = portNO_SECURE_CONTEXT;\r
 334 #endif /* configENABLE_TRUSTZONE */\r
 335 /*-----------------------------------------------------------*/\r
 336 \r
 337 __attribute__(( weak )) void vPortSetupTimerInterrupt( void ) /* PRIVILEGED_FUNCTION */\r
 338 {\r
 339         /* Stop and reset the SysTick. */\r
 340         *( portNVIC_SYSTICK_CTRL ) = 0UL;\r
 341         *( portNVIC_SYSTICK_CURRENT_VALUE ) = 0UL;\r
 342 \r
 343         /* Configure SysTick to interrupt at the requested rate. */\r
 344         *( portNVIC_SYSTICK_LOAD ) = ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;\r
 345         *( portNVIC_SYSTICK_CTRL ) = portNVIC_SYSTICK_CLK | portNVIC_SYSTICK_INT | portNVIC_SYSTICK_ENABLE;\r
 346 }\r
 347 /*-----------------------------------------------------------*/\r
 348 \r
 349 static void prvTaskExitError( void )\r
 350 {\r
 351 volatile uint32_t ulDummy = 0UL;\r
 352 \r
 353         /* A function that implements a task must not exit or attempt to return to\r
 354          * its caller as there is nothing to return to. If a task wants to exit it\r
 355          * should instead call vTaskDelete( NULL ). Artificially force an assert()\r
 356          * to be triggered if configASSERT() is defined, then stop here so\r
 357          * application writers can catch the error. */\r
 358         configASSERT( ulCriticalNesting == ~0UL );\r
 359         portDISABLE_INTERRUPTS();\r
 360 \r
 361         while( ulDummy == 0 )\r
 362         {\r
 363                 /* This file calls prvTaskExitError() after the scheduler has been\r
 364                  * started to remove a compiler warning about the function being\r
 365                  * defined but never called.  ulDummy is used purely to quieten other\r
 366                  * warnings about code appearing after this function is called - making\r
 367                  * ulDummy volatile makes the compiler think the function could return\r
 368                  * and therefore not output an 'unreachable code' warning for code that\r
 369                  * appears after it. */\r
 370         }\r
 371 }\r
 372 /*-----------------------------------------------------------*/\r
 373 \r
 374 #if( configENABLE_MPU == 1 )\r
 375         static void prvSetupMPU( void ) /* PRIVILEGED_FUNCTION */\r
 376         {\r
 377         #if defined( __ARMCC_VERSION )\r
 378                 /* Declaration when these variable are defined in code instead of being\r
 379                  * exported from linker scripts. */\r
 380                 extern uint32_t * __privileged_functions_start__;\r
 381                 extern uint32_t * __privileged_functions_end__;\r
 382                 extern uint32_t * __syscalls_flash_start__;\r
 383                 extern uint32_t * __syscalls_flash_end__;\r
 384                 extern uint32_t * __unprivileged_flash_start__;\r
 385                 extern uint32_t * __unprivileged_flash_end__;\r
 386                 extern uint32_t * __privileged_sram_start__;\r
 387                 extern uint32_t * __privileged_sram_end__;\r
 388         #else\r
 389                 /* Declaration when these variable are exported from linker scripts. */\r
 390                 extern uint32_t __privileged_functions_start__[];\r
 391                 extern uint32_t __privileged_functions_end__[];\r
 392                 extern uint32_t __syscalls_flash_start__[];\r
 393                 extern uint32_t __syscalls_flash_end__[];\r
 394                 extern uint32_t __unprivileged_flash_start__[];\r
 395                 extern uint32_t __unprivileged_flash_end__[];\r
 396                 extern uint32_t __privileged_sram_start__[];\r
 397                 extern uint32_t __privileged_sram_end__[];\r
 398         #endif /* defined( __ARMCC_VERSION ) */\r
 399 \r
 400                 /* Check that the MPU is present. */\r
 401                 if( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE )\r
 402                 {\r
 403                         /* MAIR0 - Index 0. */\r
 404                         portMPU_MAIR0_REG |= ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );\r
 405                         /* MAIR0 - Index 1. */\r
 406                         portMPU_MAIR0_REG |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK );\r
 407 \r
 408                         /* Setup privileged flash as Read Only so that privileged tasks can\r
 409                          * read it but not modify. */\r
 410                         portMPU_RNR_REG = portPRIVILEGED_FLASH_REGION;\r
 411                         portMPU_RBAR_REG =      ( ( ( uint32_t ) __privileged_functions_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |\r
 412                                                                 ( portMPU_REGION_NON_SHAREABLE ) |\r
 413                                                                 ( portMPU_REGION_PRIVILEGED_READ_ONLY );\r
 414                         portMPU_RLAR_REG =      ( ( ( uint32_t ) __privileged_functions_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |\r
 415                                                                 ( portMPU_RLAR_ATTR_INDEX0 ) |\r
 416                                                                 ( portMPU_RLAR_REGION_ENABLE );\r
 417 \r
 418                         /* Setup unprivileged flash as Read Only by both privileged and\r
 419                          * unprivileged tasks. All tasks can read it but no-one can modify. */\r
 420                         portMPU_RNR_REG = portUNPRIVILEGED_FLASH_REGION;\r
 421                         portMPU_RBAR_REG =      ( ( ( uint32_t ) __unprivileged_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |\r
 422                                                                 ( portMPU_REGION_NON_SHAREABLE ) |\r
 423                                                                 ( portMPU_REGION_READ_ONLY );\r
 424                         portMPU_RLAR_REG =      ( ( ( uint32_t ) __unprivileged_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |\r
 425                                                                 ( portMPU_RLAR_ATTR_INDEX0 ) |\r
 426                                                                 ( portMPU_RLAR_REGION_ENABLE );\r
 427 \r
 428                         /* Setup unprivileged syscalls flash as Read Only by both privileged\r
 429                          * and unprivileged tasks. All tasks can read it but no-one can modify. */\r
 430                         portMPU_RNR_REG = portUNPRIVILEGED_SYSCALLS_REGION;\r
 431                         portMPU_RBAR_REG =      ( ( ( uint32_t ) __syscalls_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |\r
 432                                                                 ( portMPU_REGION_NON_SHAREABLE ) |\r
 433                                                                 ( portMPU_REGION_READ_ONLY );\r
 434                         portMPU_RLAR_REG =      ( ( ( uint32_t ) __syscalls_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |\r
 435                                                                 ( portMPU_RLAR_ATTR_INDEX0 ) |\r
 436                                                                 ( portMPU_RLAR_REGION_ENABLE );\r
 437 \r
 438                         /* Setup RAM containing kernel data for privileged access only. */\r
 439                         portMPU_RNR_REG = portPRIVILEGED_RAM_REGION;\r
 440                         portMPU_RBAR_REG =      ( ( ( uint32_t ) __privileged_sram_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |\r
 441                                                                 ( portMPU_REGION_NON_SHAREABLE ) |\r
 442                                                                 ( portMPU_REGION_PRIVILEGED_READ_WRITE ) |\r
 443                                                                 ( portMPU_REGION_EXECUTE_NEVER );\r
 444                         portMPU_RLAR_REG =      ( ( ( uint32_t ) __privileged_sram_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |\r
 445                                                                 ( portMPU_RLAR_ATTR_INDEX0 ) |\r
 446                                                                 ( portMPU_RLAR_REGION_ENABLE );\r
 447 \r
 448                         /* Enable mem fault. */\r
 449                         portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_MEM_FAULT_ENABLE;\r
 450 \r
 451                         /* Enable MPU with privileged background access i.e. unmapped\r
 452                          * regions have privileged access. */\r
 453                         portMPU_CTRL_REG |= ( portMPU_PRIV_BACKGROUND_ENABLE | portMPU_ENABLE );\r
 454                 }\r
 455         }\r
 456 #endif /* configENABLE_MPU */\r
 457 /*-----------------------------------------------------------*/\r
 458 \r
 459 #if( configENABLE_FPU == 1 )\r
 460         static void prvSetupFPU( void ) /* PRIVILEGED_FUNCTION */\r
 461         {\r
 462                 #if( configENABLE_TRUSTZONE == 1 )\r
 463                 {\r
 464                         /* Enable non-secure access to the FPU. */\r
 465                         SecureInit_EnableNSFPUAccess();\r
 466                 }\r
 467                 #endif /* configENABLE_TRUSTZONE */\r
 468 \r
 469                 /* CP10 = 11 ==> Full access to FPU i.e. both privileged and\r
 470                  * unprivileged code should be able to access FPU. CP11 should be\r
 471                  * programmed to the same value as CP10. */\r
 472                 *( portCPACR ) |=       (       ( portCPACR_CP10_VALUE << portCPACR_CP10_POS ) |\r
 473                                                                 ( portCPACR_CP11_VALUE << portCPACR_CP11_POS )\r
 474                                                         );\r
 475 \r
 476                 /* ASPEN = 1 ==> Hardware should automatically preserve floating point\r
 477                  * context on exception entry and restore on exception return.\r
 478                  * LSPEN = 1 ==> Enable lazy context save of FP state. */\r
 479                 *( portFPCCR ) |= ( portFPCCR_ASPEN_MASK | portFPCCR_LSPEN_MASK );\r
 480         }\r
 481 #endif /* configENABLE_FPU */\r
 482 /*-----------------------------------------------------------*/\r
 483 \r
 484 void vPortYield( void ) /* PRIVILEGED_FUNCTION */\r
 485 {\r
 486         /* Set a PendSV to request a context switch. */\r
 487         *( portNVIC_INT_CTRL ) = portNVIC_PENDSVSET;\r
 488 \r
 489         /* Barriers are normally not required but do ensure the code is\r
 490          * completely within the specified behaviour for the architecture. */\r
 491         __asm volatile( "dsb" ::: "memory" );\r
 492         __asm volatile( "isb" );\r
 493 }\r
 494 /*-----------------------------------------------------------*/\r
 495 \r
 496 void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */\r
 497 {\r
 498         portDISABLE_INTERRUPTS();\r
 499         ulCriticalNesting++;\r
 500 \r
 501         /* Barriers are normally not required but do ensure the code is\r
 502          * completely within the specified behaviour for the architecture. */\r
 503         __asm volatile( "dsb" ::: "memory" );\r
 504         __asm volatile( "isb" );\r
 505 }\r
 506 /*-----------------------------------------------------------*/\r
 507 \r
 508 void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */\r
 509 {\r
 510         configASSERT( ulCriticalNesting );\r
 511         ulCriticalNesting--;\r
 512 \r
 513         if( ulCriticalNesting == 0 )\r
 514         {\r
 515                 portENABLE_INTERRUPTS();\r
 516         }\r
 517 }\r
 518 /*-----------------------------------------------------------*/\r
 519 \r
 520 void SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */\r
 521 {\r
 522 uint32_t ulPreviousMask;\r
 523 \r
 524         ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR();\r
 525         {\r
 526                 /* Increment the RTOS tick. */\r
 527                 if( xTaskIncrementTick() != pdFALSE )\r
 528                 {\r
 529                         /* Pend a context switch. */\r
 530                         *( portNVIC_INT_CTRL ) = portNVIC_PENDSVSET;\r
 531                 }\r
 532         }\r
 533         portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask );\r
 534 }\r
 535 /*-----------------------------------------------------------*/\r
 536 \r
 537 void vPortSVCHandler_C( uint32_t *pulCallerStackAddress ) /* PRIVILEGED_FUNCTION portDONT_DISCARD */\r
 538 {\r
 539 #if( configENABLE_MPU == 1 )\r
 540         #if defined( __ARMCC_VERSION )\r
 541                 /* Declaration when these variable are defined in code instead of being\r
 542                  * exported from linker scripts. */\r
 543                 extern uint32_t * __syscalls_flash_start__;\r
 544                 extern uint32_t * __syscalls_flash_end__;\r
 545         #else\r
 546                 /* Declaration when these variable are exported from linker scripts. */\r
 547                 extern uint32_t __syscalls_flash_start__[];\r
 548                 extern uint32_t __syscalls_flash_end__[];\r
 549         #endif /* defined( __ARMCC_VERSION ) */\r
 550 #endif /* configENABLE_MPU */\r
 551 \r
 552 uint32_t ulPC;\r
 553 \r
 554 #if( configENABLE_TRUSTZONE == 1 )\r
 555         uint32_t ulR0;\r
 556         #if( configENABLE_MPU == 1 )\r
 557                 uint32_t ulControl, ulIsTaskPrivileged;\r
 558         #endif /* configENABLE_MPU */\r
 559 #endif /* configENABLE_TRUSTZONE */\r
 560 uint8_t ucSVCNumber;\r
 561 \r
 562         /* Register are stored on the stack in the following order - R0, R1, R2, R3,\r
 563          * R12, LR, PC, xPSR. */\r
 564         ulPC = pulCallerStackAddress[ 6 ];\r
 565         ucSVCNumber = ( ( uint8_t *) ulPC )[ -2 ];\r
 566 \r
 567         switch( ucSVCNumber )\r
 568         {\r
 569                 #if( configENABLE_TRUSTZONE == 1 )\r
 570                         case portSVC_ALLOCATE_SECURE_CONTEXT:\r
 571                         {\r
 572                                 /* R0 contains the stack size passed as parameter to the\r
 573                                  * vPortAllocateSecureContext function. */\r
 574                                 ulR0 = pulCallerStackAddress[ 0 ];\r
 575 \r
 576                                 #if( configENABLE_MPU == 1 )\r
 577                                 {\r
 578                                         /* Read the CONTROL register value. */\r
 579                                         __asm volatile ( "mrs %0, control"  : "=r" ( ulControl ) );\r
 580 \r
 581                                         /* The task that raised the SVC is privileged if Bit[0]\r
 582                                          * in the CONTROL register is 0. */\r
 583                                         ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 );\r
 584 \r
 585                                         /* Allocate and load a context for the secure task. */\r
 586                                         xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged );\r
 587                                 }\r
 588                                 #else\r
 589                                 {\r
 590                                         /* Allocate and load a context for the secure task. */\r
 591                                         xSecureContext = SecureContext_AllocateContext( ulR0 );\r
 592                                 }\r
 593                                 #endif /* configENABLE_MPU */\r
 594 \r
 595                                 configASSERT( xSecureContext != NULL );\r
 596                                 SecureContext_LoadContext( xSecureContext );\r
 597                         }\r
 598                         break;\r
 599 \r
 600                         case portSVC_FREE_SECURE_CONTEXT:\r
 601                         {\r
 602                                 /* R0 contains the secure context handle to be freed. */\r
 603                                 ulR0 = pulCallerStackAddress[ 0 ];\r
 604 \r
 605                                 /* Free the secure context. */\r
 606                                 SecureContext_FreeContext( ( SecureContextHandle_t ) ulR0 );\r
 607                         }\r
 608                         break;\r
 609                 #endif /* configENABLE_TRUSTZONE */\r
 610 \r
 611                 case portSVC_START_SCHEDULER:\r
 612                 {\r
 613                         #if( configENABLE_TRUSTZONE == 1 )\r
 614                         {\r
 615                                 /* De-prioritize the non-secure exceptions so that the\r
 616                                  * non-secure pendSV runs at the lowest priority. */\r
 617                                 SecureInit_DePrioritizeNSExceptions();\r
 618 \r
 619                                 /* Initialize the secure context management system. */\r
 620                                 SecureContext_Init();\r
 621                         }\r
 622                         #endif /* configENABLE_TRUSTZONE */\r
 623 \r
 624                         #if( configENABLE_FPU == 1 )\r
 625                         {\r
 626                                 /* Setup the Floating Point Unit (FPU). */\r
 627                                 prvSetupFPU();\r
 628                         }\r
 629                         #endif /* configENABLE_FPU */\r
 630 \r
 631                         /* Setup the context of the first task so that the first task starts\r
 632                          * executing. */\r
 633                         vRestoreContextOfFirstTask();\r
 634                 }\r
 635                 break;\r
 636 \r
 637                 #if( configENABLE_MPU == 1 )\r
 638                         case portSVC_RAISE_PRIVILEGE:\r
 639                         {\r
 640                                 /* Only raise the privilege, if the svc was raised from any of\r
 641                                  * the system calls. */\r
 642                                 if( ulPC >= ( uint32_t ) __syscalls_flash_start__ &&\r
 643                                         ulPC <= ( uint32_t ) __syscalls_flash_end__ )\r
 644                                 {\r
 645                                         vRaisePrivilege();\r
 646                                 }\r
 647                         }\r
 648                         break;\r
 649                 #endif /* configENABLE_MPU */\r
 650 \r
 651                 default:\r
 652                 {\r
 653                         /* Incorrect SVC call. */\r
 654                         configASSERT( pdFALSE );\r
 655                 }\r
 656         }\r
 657 }\r
 658 /*-----------------------------------------------------------*/\r
 659 \r
 660 #if( configENABLE_MPU == 1 )\r
 661         StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, StackType_t *pxEndOfStack, TaskFunction_t pxCode, void *pvParameters, BaseType_t xRunPrivileged ) /* PRIVILEGED_FUNCTION */\r
 662 #else\r
 663         StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, StackType_t *pxEndOfStack, TaskFunction_t pxCode, void *pvParameters ) /* PRIVILEGED_FUNCTION */\r
 664 #endif /* configENABLE_MPU */\r
 665 {\r
 666         /* Simulate the stack frame as it would be created by a context switch\r
 667          * interrupt. */\r
 668         #if( portPRELOAD_REGISTERS == 0 )\r
 669         {\r
 670                 pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */\r
 671                 *pxTopOfStack = portINITIAL_XPSR;                                                       /* xPSR */\r
 672                 pxTopOfStack--;\r
 673                 *pxTopOfStack = ( StackType_t ) pxCode;                                         /* PC */\r
 674                 pxTopOfStack--;\r
 675                 *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS;        /* LR */\r
 676                 pxTopOfStack -= 5;                                                                                      /* R12, R3, R2 and R1. */\r
 677                 *pxTopOfStack = ( StackType_t ) pvParameters;                           /* R0 */\r
 678                 pxTopOfStack -= 9;                                                                                      /* R11..R4, EXC_RETURN. */\r
 679                 *pxTopOfStack = portINITIAL_EXC_RETURN;\r
 680 \r
 681                 #if( configENABLE_MPU == 1 )\r
 682                 {\r
 683                         pxTopOfStack--;\r
 684                         if( xRunPrivileged == pdTRUE )\r
 685                         {\r
 686                                 *pxTopOfStack = portINITIAL_CONTROL_PRIVILEGED;         /* Slot used to hold this task's CONTROL value. */\r
 687                         }\r
 688                         else\r
 689                         {\r
 690                                 *pxTopOfStack = portINITIAL_CONTROL_UNPRIVILEGED;       /* Slot used to hold this task's CONTROL value. */\r
 691                         }\r
 692                 }\r
 693                 #endif /* configENABLE_MPU */\r
 694 \r
 695                 pxTopOfStack--;\r
 696                 *pxTopOfStack = ( StackType_t ) pxEndOfStack;   /* Slot used to hold this task's PSPLIM value. */\r
 697 \r
 698                 #if( configENABLE_TRUSTZONE == 1 )\r
 699                 {\r
 700                         pxTopOfStack--;\r
 701                         *pxTopOfStack = portNO_SECURE_CONTEXT;          /* Slot used to hold this task's xSecureContext value. */\r
 702                 }\r
 703                 #endif /* configENABLE_TRUSTZONE */\r
 704         }\r
 705         #else /* portPRELOAD_REGISTERS */\r
 706         {\r
 707                 pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */\r
 708                 *pxTopOfStack = portINITIAL_XPSR;                                                       /* xPSR */\r
 709                 pxTopOfStack--;\r
 710                 *pxTopOfStack = ( StackType_t ) pxCode;                                         /* PC */\r
 711                 pxTopOfStack--;\r
 712                 *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS;        /* LR */\r
 713                 pxTopOfStack--;\r
 714                 *pxTopOfStack = ( StackType_t ) 0x12121212UL;                           /* R12 */\r
 715                 pxTopOfStack--;\r
 716                 *pxTopOfStack = ( StackType_t ) 0x03030303UL;                           /* R3 */\r
 717                 pxTopOfStack--;\r
 718                 *pxTopOfStack = ( StackType_t ) 0x02020202UL;                           /* R2 */\r
 719                 pxTopOfStack--;\r
 720                 *pxTopOfStack = ( StackType_t ) 0x01010101UL;                           /* R1 */\r
 721                 pxTopOfStack--;\r
 722                 *pxTopOfStack = ( StackType_t ) pvParameters;                           /* R0 */\r
 723                 pxTopOfStack--;\r
 724                 *pxTopOfStack = ( StackType_t ) 0x11111111UL;                           /* R11 */\r
 725                 pxTopOfStack--;\r
 726                 *pxTopOfStack = ( StackType_t ) 0x10101010UL;                           /* R10 */\r
 727                 pxTopOfStack--;\r
 728                 *pxTopOfStack = ( StackType_t ) 0x09090909UL;                           /* R09 */\r
 729                 pxTopOfStack--;\r
 730                 *pxTopOfStack = ( StackType_t ) 0x08080808UL;                           /* R08 */\r
 731                 pxTopOfStack--;\r
 732                 *pxTopOfStack = ( StackType_t ) 0x07070707UL;                           /* R07 */\r
 733                 pxTopOfStack--;\r
 734                 *pxTopOfStack = ( StackType_t ) 0x06060606UL;                           /* R06 */\r
 735                 pxTopOfStack--;\r
 736                 *pxTopOfStack = ( StackType_t ) 0x05050505UL;                           /* R05 */\r
 737                 pxTopOfStack--;\r
 738                 *pxTopOfStack = ( StackType_t ) 0x04040404UL;                           /* R04 */\r
 739                 pxTopOfStack--;\r
 740                 *pxTopOfStack = portINITIAL_EXC_RETURN;                                         /* EXC_RETURN */\r
 741 \r
 742                 #if( configENABLE_MPU == 1 )\r
 743                 {\r
 744                         pxTopOfStack--;\r
 745                         if( xRunPrivileged == pdTRUE )\r
 746                         {\r
 747                                 *pxTopOfStack = portINITIAL_CONTROL_PRIVILEGED;         /* Slot used to hold this task's CONTROL value. */\r
 748                         }\r
 749                         else\r
 750                         {\r
 751                                 *pxTopOfStack = portINITIAL_CONTROL_UNPRIVILEGED;       /* Slot used to hold this task's CONTROL value. */\r
 752                         }\r
 753                 }\r
 754                 #endif /* configENABLE_MPU */\r
 755 \r
 756                 pxTopOfStack--;\r
 757                 *pxTopOfStack = ( StackType_t ) pxEndOfStack;   /* Slot used to hold this task's PSPLIM value. */\r
 758 \r
 759                 #if( configENABLE_TRUSTZONE == 1 )\r
 760                 {\r
 761                         pxTopOfStack--;\r
 762                         *pxTopOfStack = portNO_SECURE_CONTEXT;          /* Slot used to hold this task's xSecureContext value. */\r
 763                 }\r
 764                 #endif /* configENABLE_TRUSTZONE */\r
 765         }\r
 766         #endif /* portPRELOAD_REGISTERS */\r
 767 \r
 768         return pxTopOfStack;\r
 769 }\r
 770 /*-----------------------------------------------------------*/\r
 771 \r
 772 BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */\r
 773 {\r
 774         /* Make PendSV, CallSV and SysTick the same priority as the kernel. */\r
 775         *( portNVIC_SYSPRI2 ) |= portNVIC_PENDSV_PRI;\r
 776         *( portNVIC_SYSPRI2 ) |= portNVIC_SYSTICK_PRI;\r
 777 \r
 778         #if( configENABLE_MPU == 1 )\r
 779         {\r
 780                 /* Setup the Memory Protection Unit (MPU). */\r
 781                 prvSetupMPU();\r
 782         }\r
 783         #endif /* configENABLE_MPU */\r
 784 \r
 785         /* Start the timer that generates the tick ISR. Interrupts are disabled\r
 786          * here already. */\r
 787         vPortSetupTimerInterrupt();\r
 788 \r
 789         /* Initialize the critical nesting count ready for the first task. */\r
 790         ulCriticalNesting = 0;\r
 791 \r
 792         /* Start the first task. */\r
 793         vStartFirstTask();\r
 794 \r
 795         /* Should never get here as the tasks will now be executing. Call the task\r
 796          * exit error function to prevent compiler warnings about a static function\r
 797          * not being called in the case that the application writer overrides this\r
 798          * functionality by defining configTASK_RETURN_ADDRESS. Call\r
 799          * vTaskSwitchContext() so link time optimization does not remove the\r
 800          * symbol. */\r
 801         vTaskSwitchContext();\r
 802         prvTaskExitError();\r
 803 \r
 804         /* Should not get here. */\r
 805         return 0;\r
 806 }\r
 807 /*-----------------------------------------------------------*/\r
 808 \r
 809 void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */\r
 810 {\r
 811         /* Not implemented in ports where there is nothing to return to.\r
 812          * Artificially force an assert. */\r
 813         configASSERT( ulCriticalNesting == 1000UL );\r
 814 }\r
 815 /*-----------------------------------------------------------*/\r
 816 \r
 817 #if( configENABLE_MPU == 1 )\r
 818         void vPortStoreTaskMPUSettings( xMPU_SETTINGS *xMPUSettings, const struct xMEMORY_REGION * const xRegions, StackType_t *pxBottomOfStack, uint32_t ulStackDepth )\r
 819         {\r
 820         uint32_t ulRegionStartAddress, ulRegionEndAddress, ulRegionNumber;\r
 821         int32_t lIndex = 0;\r
 822 \r
 823                 /* Setup MAIR0. */\r
 824                 xMPUSettings->ulMAIR0 = ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );\r
 825                 xMPUSettings->ulMAIR0 |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK );\r
 826 \r
 827                 /* This function is called automatically when the task is created - in\r
 828                  * which case the stack region parameters will be valid.  At all other\r
 829                  * times the stack parameters will not be valid and it is assumed that\r
 830                  * the stack region has already been configured. */\r
 831                 if( ulStackDepth > 0 )\r
 832                 {\r
 833                         /* Define the region that allows access to the stack. */\r
 834                         ulRegionStartAddress = ( ( uint32_t ) pxBottomOfStack ) & portMPU_RBAR_ADDRESS_MASK;\r
 835                         ulRegionEndAddress = ( uint32_t ) pxBottomOfStack + ( ulStackDepth * ( uint32_t ) sizeof( StackType_t ) ) - 1;\r
 836                         ulRegionEndAddress  &= portMPU_RLAR_ADDRESS_MASK;\r
 837 \r
 838                         xMPUSettings->xRegionsSettings[ 0 ].ulRBAR =    ( ulRegionStartAddress ) |\r
 839                                                                                                                         ( portMPU_REGION_NON_SHAREABLE ) |\r
 840                                                                                                                         ( portMPU_REGION_READ_WRITE ) |\r
 841                                                                                                                         ( portMPU_REGION_EXECUTE_NEVER );\r
 842 \r
 843                         xMPUSettings->xRegionsSettings[ 0 ].ulRLAR =    ( ulRegionEndAddress ) |\r
 844                                                                                                                         ( portMPU_RLAR_ATTR_INDEX0 ) |\r
 845                                                                                                                         ( portMPU_RLAR_REGION_ENABLE );\r
 846                 }\r
 847 \r
 848                 /* User supplied configurable regions. */\r
 849                 for( ulRegionNumber = 1; ulRegionNumber <= portNUM_CONFIGURABLE_REGIONS; ulRegionNumber++ )\r
 850                 {\r
 851                         /* If xRegions is NULL i.e. the task has not specified any MPU\r
 852                          * region, the else part ensures that all the configurable MPU\r
 853                          * regions are invalidated. */\r
 854                         if( ( xRegions != NULL ) && ( xRegions[ lIndex ].ulLengthInBytes > 0UL ) )\r
 855                         {\r
 856                                 /* Translate the generic region definition contained in xRegions\r
 857                                  * into the ARMv8 specific MPU settings that are then stored in\r
 858                                  * xMPUSettings. */\r
 859                                 ulRegionStartAddress = ( ( uint32_t ) xRegions[ lIndex ].pvBaseAddress ) & portMPU_RBAR_ADDRESS_MASK;\r
 860                                 ulRegionEndAddress = ( uint32_t ) xRegions[ lIndex ].pvBaseAddress + xRegions[ lIndex ].ulLengthInBytes - 1;\r
 861                                 ulRegionEndAddress  &= portMPU_RLAR_ADDRESS_MASK;\r
 862 \r
 863                                 /* Start address. */\r
 864                                 xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR =       ( ulRegionStartAddress ) |\r
 865                                                                                                                                                         ( portMPU_REGION_NON_SHAREABLE );\r
 866 \r
 867                                 /* RO/RW. */\r
 868                                 if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_READ_ONLY ) != 0 )\r
 869                                 {\r
 870                                         xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_ONLY );\r
 871                                 }\r
 872                                 else\r
 873                                 {\r
 874                                         xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_WRITE );\r
 875                                 }\r
 876 \r
 877                                 /* XN. */\r
 878                                 if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_EXECUTE_NEVER ) != 0 )\r
 879                                 {\r
 880                                         xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_EXECUTE_NEVER );\r
 881                                 }\r
 882 \r
 883                                 /* End Address. */\r
 884                                 xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR =       ( ulRegionEndAddress ) |\r
 885                                                                                                                                                         ( portMPU_RLAR_REGION_ENABLE );\r
 886 \r
 887                                 /* Normal memory/ Device memory. */\r
 888                                 if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_DEVICE_MEMORY ) != 0 )\r
 889                                 {\r
 890                                         /* Attr1 in MAIR0 is configured as device memory. */\r
 891                                         xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX1;\r
 892                                 }\r
 893                                 else\r
 894                                 {\r
 895                                         /* Attr1 in MAIR0 is configured as normal memory. */\r
 896                                         xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX0;\r
 897                                 }\r
 898                         }\r
 899                         else\r
 900                         {\r
 901                                 /* Invalidate the region. */\r
 902                                 xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR = 0UL;\r
 903                                 xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = 0UL;\r
 904                         }\r
 905 \r
 906                         lIndex++;\r
 907                 }\r
 908         }\r
 909 #endif /* configENABLE_MPU */\r
 910 /*-----------------------------------------------------------*/\r
 911 \r
 912 BaseType_t xPortIsInsideInterrupt( void )\r
 913 {\r
 914 uint32_t ulCurrentInterrupt;\r
 915 BaseType_t xReturn;\r
 916 \r
 917         /* Obtain the number of the currently executing interrupt. Interrupt Program\r
 918          * Status Register (IPSR) holds the exception number of the currently-executing\r
 919          * exception or zero for Thread mode.*/\r
 920         __asm volatile( "mrs %0, ipsr" : "=r"( ulCurrentInterrupt ) :: "memory" );\r
 921 \r
 922         if( ulCurrentInterrupt == 0 )\r
 923         {\r
 924                 xReturn = pdFALSE;\r
 925         }\r
 926         else\r
 927         {\r
 928                 xReturn = pdTRUE;\r
 929         }\r
 930 \r
 931         return xReturn;\r
 932 }\r
 933 /*-----------------------------------------------------------*/