git.sur5r.net Git - freertos/blob - FreeRTOS/Source/portable/IAR/ARM_CM33_NTZ/non_secure/port.c

   1 /*\r
   2  * FreeRTOS Kernel V10.2.1\r
   3  * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\r
   4  *\r
   5  * Permission is hereby granted, free of charge, to any person obtaining a copy of\r
   6  * this software and associated documentation files (the "Software"), to deal in\r
   7  * the Software without restriction, including without limitation the rights to\r
   8  * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\r
   9  * the Software, and to permit persons to whom the Software is furnished to do so,\r
  10  * subject to the following conditions:\r
  11  *\r
  12  * The above copyright notice and this permission notice shall be included in all\r
  13  * copies or substantial portions of the Software.\r
  14  *\r
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\r
  17  * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\r
  18  * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r
  19  * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
  20  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
  21  *\r
  22  * http://www.FreeRTOS.org\r
  23  * http://aws.amazon.com/freertos\r
  24  *\r
  25  * 1 tab == 4 spaces!\r
  26  */\r
  27 \r
  28 /* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining\r
  29  * all the API functions to use the MPU wrappers. That should only be done when\r
  30  * task.h is included from an application file. */\r
  31 #define MPU_WRAPPERS_INCLUDED_FROM_API_FILE\r
  32 \r
  33 /* Scheduler includes. */\r
  34 #include "FreeRTOS.h"\r
  35 #include "task.h"\r
  36 \r
  37 /* MPU wrappers includes. */\r
  38 #include "mpu_wrappers.h"\r
  39 \r
  40 /* Portasm includes. */\r
  41 #include "portasm.h"\r
  42 \r
  43 #if( configENABLE_TRUSTZONE == 1 )\r
  44         /* Secure components includes. */\r
  45         #include "secure_context.h"\r
  46         #include "secure_init.h"\r
  47 #endif /* configENABLE_TRUSTZONE */\r
  48 \r
  49 #undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE\r
  50 \r
  51 /**\r
  52  * The FreeRTOS Cortex M33 port can be configured to run on the Secure Side only\r
  53  * i.e. the processor boots as secure and never jumps to the non-secure side.\r
  54  * The Trust Zone support in the port must be disabled in order to run FreeRTOS\r
  55  * on the secure side. The following are the valid configuration seetings:\r
  56  *\r
  57  * 1. Run FreeRTOS on the Secure Side:\r
  58  *              configRUN_FREERTOS_SECURE_ONLY = 1 and configENABLE_TRUSTZONE = 0\r
  59  *\r
  60  * 2. Run FreeRTOS on the Non-Secure Side with Secure Side function call support:\r
  61  *              configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 1\r
  62  *\r
  63  * 3. Run FreeRTOS on the Non-Secure Side only i.e. no Secure Side function call support:\r
  64  *              configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 0\r
  65  */\r
  66 #if( ( configRUN_FREERTOS_SECURE_ONLY == 1 ) && ( configENABLE_TRUSTZONE == 1 ) )\r
  67         #error TrustZone needs to be disabled in order to run FreeRTOS on the Secure Side.\r
  68 #endif\r
  69 /*-----------------------------------------------------------*/\r
  70 \r
  71 /**\r
  72  * @brief Constants required to manipulate the NVIC.\r
  73  */\r
  74 #define portNVIC_SYSTICK_CTRL                           ( ( volatile uint32_t * ) 0xe000e010 )\r
  75 #define portNVIC_SYSTICK_LOAD                           ( ( volatile uint32_t * ) 0xe000e014 )\r
  76 #define portNVIC_SYSTICK_CURRENT_VALUE          ( ( volatile uint32_t * ) 0xe000e018 )\r
  77 #define portNVIC_INT_CTRL                                       ( ( volatile uint32_t * ) 0xe000ed04 )\r
  78 #define portNVIC_SYSPRI2                                        ( ( volatile uint32_t * ) 0xe000ed20 )\r
  79 #define portNVIC_SYSTICK_CLK                            ( 0x00000004 )\r
  80 #define portNVIC_SYSTICK_INT                            ( 0x00000002 )\r
  81 #define portNVIC_SYSTICK_ENABLE                         ( 0x00000001 )\r
  82 #define portNVIC_PENDSVSET                                      ( 0x10000000 )\r
  83 #define portMIN_INTERRUPT_PRIORITY                      ( 255UL )\r
  84 #define portNVIC_PENDSV_PRI                                     ( portMIN_INTERRUPT_PRIORITY << 16UL )\r
  85 #define portNVIC_SYSTICK_PRI                            ( portMIN_INTERRUPT_PRIORITY << 24UL )\r
  86 /*-----------------------------------------------------------*/\r
  87 \r
  88 /**\r
  89  * @brief Constants required to manipulate the SCB.\r
  90  */\r
  91 #define portSCB_SYS_HANDLER_CTRL_STATE_REG      ( * ( volatile uint32_t * ) 0xe000ed24 )\r
  92 #define portSCB_MEM_FAULT_ENABLE                        ( 1UL << 16UL )\r
  93 /*-----------------------------------------------------------*/\r
  94 \r
  95 /**\r
  96  * @brief Constants required to manipulate the FPU.\r
  97  */\r
  98 #define portCPACR                                                       ( ( volatile uint32_t * ) 0xe000ed88 )  /* Coprocessor Access Control Register. */\r
  99 #define portCPACR_CP10_VALUE                            ( 3UL )\r
 100 #define portCPACR_CP11_VALUE                            portCPACR_CP10_VALUE\r
 101 #define portCPACR_CP10_POS                                      ( 20UL )\r
 102 #define portCPACR_CP11_POS                                      ( 22UL )\r
 103 \r
 104 #define portFPCCR                                                       ( ( volatile uint32_t * ) 0xe000ef34 )  /* Floating Point Context Control Register. */\r
 105 #define portFPCCR_ASPEN_POS                                     ( 31UL )\r
 106 #define portFPCCR_ASPEN_MASK                            ( 1UL << portFPCCR_ASPEN_POS )\r
 107 #define portFPCCR_LSPEN_POS                                     ( 30UL )\r
 108 #define portFPCCR_LSPEN_MASK                            ( 1UL << portFPCCR_LSPEN_POS )\r
 109 /*-----------------------------------------------------------*/\r
 110 \r
 111 /**\r
 112  * @brief Constants required to manipulate the MPU.\r
 113  */\r
 114 #define portMPU_TYPE_REG                                        ( * ( ( volatile uint32_t * ) 0xe000ed90 ) )\r
 115 #define portMPU_CTRL_REG                                        ( * ( ( volatile uint32_t * ) 0xe000ed94 ) )\r
 116 #define portMPU_RNR_REG                                         ( * ( ( volatile uint32_t * ) 0xe000ed98 ) )\r
 117 \r
 118 #define portMPU_RBAR_REG                                        ( * ( ( volatile uint32_t * ) 0xe000ed9c ) )\r
 119 #define portMPU_RLAR_REG                                        ( * ( ( volatile uint32_t * ) 0xe000eda0 ) )\r
 120 \r
 121 #define portMPU_RBAR_A1_REG                                     ( * ( ( volatile uint32_t * ) 0xe000eda4 ) )\r
 122 #define portMPU_RLAR_A1_REG                                     ( * ( ( volatile uint32_t * ) 0xe000eda8 ) )\r
 123 \r
 124 #define portMPU_RBAR_A2_REG                                     ( * ( ( volatile uint32_t * ) 0xe000edac ) )\r
 125 #define portMPU_RLAR_A2_REG                                     ( * ( ( volatile uint32_t * ) 0xe000edb0 ) )\r
 126 \r
 127 #define portMPU_RBAR_A3_REG                                     ( * ( ( volatile uint32_t * ) 0xe000edb4 ) )\r
 128 #define portMPU_RLAR_A3_REG                                     ( * ( ( volatile uint32_t * ) 0xe000edb8 ) )\r
 129 \r
 130 #define portMPU_MAIR0_REG                                       ( * ( ( volatile uint32_t * ) 0xe000edc0 ) )\r
 131 #define portMPU_MAIR1_REG                                       ( * ( ( volatile uint32_t * ) 0xe000edc4 ) )\r
 132 \r
 133 #define portMPU_RBAR_ADDRESS_MASK                       ( 0xffffffe0 ) /* Must be 32-byte aligned. */\r
 134 #define portMPU_RLAR_ADDRESS_MASK                       ( 0xffffffe0 ) /* Must be 32-byte aligned. */\r
 135 \r
 136 #define portMPU_MAIR_ATTR0_POS                          ( 0UL )\r
 137 #define portMPU_MAIR_ATTR0_MASK                         ( 0x000000ff )\r
 138 \r
 139 #define portMPU_MAIR_ATTR1_POS                          ( 8UL )\r
 140 #define portMPU_MAIR_ATTR1_MASK                         ( 0x0000ff00 )\r
 141 \r
 142 #define portMPU_MAIR_ATTR2_POS                          ( 16UL )\r
 143 #define portMPU_MAIR_ATTR2_MASK                         ( 0x00ff0000 )\r
 144 \r
 145 #define portMPU_MAIR_ATTR3_POS                          ( 24UL )\r
 146 #define portMPU_MAIR_ATTR3_MASK                         ( 0xff000000 )\r
 147 \r
 148 #define portMPU_MAIR_ATTR4_POS                          ( 0UL )\r
 149 #define portMPU_MAIR_ATTR4_MASK                         ( 0x000000ff )\r
 150 \r
 151 #define portMPU_MAIR_ATTR5_POS                          ( 8UL )\r
 152 #define portMPU_MAIR_ATTR5_MASK                         ( 0x0000ff00 )\r
 153 \r
 154 #define portMPU_MAIR_ATTR6_POS                          ( 16UL )\r
 155 #define portMPU_MAIR_ATTR6_MASK                         ( 0x00ff0000 )\r
 156 \r
 157 #define portMPU_MAIR_ATTR7_POS                          ( 24UL )\r
 158 #define portMPU_MAIR_ATTR7_MASK                         ( 0xff000000 )\r
 159 \r
 160 #define portMPU_RLAR_ATTR_INDEX0                        ( 0UL << 1UL )\r
 161 #define portMPU_RLAR_ATTR_INDEX1                        ( 1UL << 1UL )\r
 162 #define portMPU_RLAR_ATTR_INDEX2                        ( 2UL << 1UL )\r
 163 #define portMPU_RLAR_ATTR_INDEX3                        ( 3UL << 1UL )\r
 164 #define portMPU_RLAR_ATTR_INDEX4                        ( 4UL << 1UL )\r
 165 #define portMPU_RLAR_ATTR_INDEX5                        ( 5UL << 1UL )\r
 166 #define portMPU_RLAR_ATTR_INDEX6                        ( 6UL << 1UL )\r
 167 #define portMPU_RLAR_ATTR_INDEX7                        ( 7UL << 1UL )\r
 168 \r
 169 #define portMPU_RLAR_REGION_ENABLE                      ( 1UL )\r
 170 \r
 171 /* Enable privileged access to unmapped region. */\r
 172 #define portMPU_PRIV_BACKGROUND_ENABLE          ( 1UL << 2UL )\r
 173 \r
 174 /* Enable MPU. */\r
 175 #define portMPU_ENABLE                                          ( 1UL << 0UL )\r
 176 \r
 177 /* Expected value of the portMPU_TYPE register. */\r
 178 #define portEXPECTED_MPU_TYPE_VALUE                     ( 8UL << 8UL ) /* 8 regions, unified. */\r
 179 /*-----------------------------------------------------------*/\r
 180 \r
 181 /**\r
 182  * @brief Constants required to set up the initial stack.\r
 183  */\r
 184 #define portINITIAL_XPSR                                        ( 0x01000000 )\r
 185 \r
 186 #if( configRUN_FREERTOS_SECURE_ONLY == 1 )\r
 187         /**\r
 188          * @brief Initial EXC_RETURN value.\r
 189          *\r
 190          *     FF         FF         FF         FD\r
 191          * 1111 1111  1111 1111  1111 1111  1111 1101\r
 192          *\r
 193          * Bit[6] - 1 --> The exception was taken from the Secure state.\r
 194          * Bit[5] - 1 --> Do not skip stacking of additional state context.\r
 195          * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.\r
 196          * Bit[3] - 1 --> Return to the Thread mode.\r
 197          * Bit[2] - 1 --> Restore registers from the process stack.\r
 198          * Bit[1] - 0 --> Reserved, 0.\r
 199          * Bit[0] - 1 --> The exception was taken to the Secure state.\r
 200          */\r
 201         #define portINITIAL_EXC_RETURN                  ( 0xfffffffd )\r
 202 #else\r
 203         /**\r
 204          * @brief Initial EXC_RETURN value.\r
 205          *\r
 206          *     FF         FF         FF         BC\r
 207          * 1111 1111  1111 1111  1111 1111  1011 1100\r
 208          *\r
 209          * Bit[6] - 0 --> The exception was taken from the Non-Secure state.\r
 210          * Bit[5] - 1 --> Do not skip stacking of additional state context.\r
 211          * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.\r
 212          * Bit[3] - 1 --> Return to the Thread mode.\r
 213          * Bit[2] - 1 --> Restore registers from the process stack.\r
 214          * Bit[1] - 0 --> Reserved, 0.\r
 215          * Bit[0] - 0 --> The exception was taken to the Non-Secure state.\r
 216          */\r
 217         #define portINITIAL_EXC_RETURN                  ( 0xffffffbc )\r
 218 #endif /* configRUN_FREERTOS_SECURE_ONLY */\r
 219 \r
 220 /**\r
 221  * @brief CONTROL register privileged bit mask.\r
 222  *\r
 223  * Bit[0] in CONTROL register tells the privilege:\r
 224  *  Bit[0] = 0 ==> The task is privileged.\r
 225  *  Bit[0] = 1 ==> The task is not privileged.\r
 226  */\r
 227 #define portCONTROL_PRIVILEGED_MASK                     ( 1UL << 0UL )\r
 228 \r
 229 /**\r
 230  * @brief Initial CONTROL register values.\r
 231  */\r
 232 #define portINITIAL_CONTROL_UNPRIVILEGED        ( 0x3 )\r
 233 #define portINITIAL_CONTROL_PRIVILEGED          ( 0x2 )\r
 234 \r
 235 /**\r
 236  * @brief Let the user override the pre-loading of the initial LR with the\r
 237  * address of prvTaskExitError() in case it messes up unwinding of the stack\r
 238  * in the debugger.\r
 239  */\r
 240 #ifdef configTASK_RETURN_ADDRESS\r
 241         #define portTASK_RETURN_ADDRESS                 configTASK_RETURN_ADDRESS\r
 242 #else\r
 243         #define portTASK_RETURN_ADDRESS                 prvTaskExitError\r
 244 #endif\r
 245 \r
 246 /**\r
 247  * @brief If portPRELOAD_REGISTERS then registers will be given an initial value\r
 248  * when a task is created. This helps in debugging at the cost of code size.\r
 249  */\r
 250 #define portPRELOAD_REGISTERS                           1\r
 251 \r
 252 /**\r
 253  * @brief A task is created without a secure context, and must call\r
 254  * portALLOCATE_SECURE_CONTEXT() to give itself a secure context before it makes\r
 255  * any secure calls.\r
 256  */\r
 257 #define portNO_SECURE_CONTEXT                           0\r
 258 /*-----------------------------------------------------------*/\r
 259 \r
 260 /**\r
 261  * @brief Setup the timer to generate the tick interrupts.\r
 262  */\r
 263 static void prvSetupTimerInterrupt( void ) PRIVILEGED_FUNCTION;\r
 264 \r
 265 /**\r
 266  * @brief Used to catch tasks that attempt to return from their implementing\r
 267  * function.\r
 268  */\r
 269 static void prvTaskExitError( void );\r
 270 \r
 271 #if( configENABLE_MPU == 1 )\r
 272         /**\r
 273          * @brief Setup the Memory Protection Unit (MPU).\r
 274          */\r
 275         static void prvSetupMPU( void ) PRIVILEGED_FUNCTION;\r
 276 #endif /* configENABLE_MPU */\r
 277 \r
 278 #if( configENABLE_FPU == 1 )\r
 279         /**\r
 280          * @brief Setup the Floating Point Unit (FPU).\r
 281          */\r
 282         static void prvSetupFPU( void ) PRIVILEGED_FUNCTION;\r
 283 #endif /* configENABLE_FPU */\r
 284 \r
 285 /**\r
 286  * @brief Yield the processor.\r
 287  */\r
 288 void vPortYield( void ) PRIVILEGED_FUNCTION;\r
 289 \r
 290 /**\r
 291  * @brief Enter critical section.\r
 292  */\r
 293 void vPortEnterCritical( void ) PRIVILEGED_FUNCTION;\r
 294 \r
 295 /**\r
 296  * @brief Exit from critical section.\r
 297  */\r
 298 void vPortExitCritical( void ) PRIVILEGED_FUNCTION;\r
 299 \r
 300 /**\r
 301  * @brief SysTick handler.\r
 302  */\r
 303 void SysTick_Handler( void ) PRIVILEGED_FUNCTION;\r
 304 \r
 305 /**\r
 306  * @brief C part of SVC handler.\r
 307  */\r
 308 portDONT_DISCARD void vPortSVCHandler_C( uint32_t *pulCallerStackAddress ) PRIVILEGED_FUNCTION;\r
 309 /*-----------------------------------------------------------*/\r
 310 \r
 311 /**\r
 312  * @brief Each task maintains its own interrupt status in the critical nesting\r
 313  * variable.\r
 314  */\r
 315 static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL;\r
 316 \r
 317 #if( configENABLE_TRUSTZONE == 1 )\r
 318         /**\r
 319          * @brief Saved as part of the task context to indicate which context the\r
 320          * task is using on the secure side.\r
 321          */\r
 322         portDONT_DISCARD volatile SecureContextHandle_t xSecureContext = portNO_SECURE_CONTEXT;\r
 323 #endif /* configENABLE_TRUSTZONE */\r
 324 /*-----------------------------------------------------------*/\r
 325 \r
 326 static void prvSetupTimerInterrupt( void ) /* PRIVILEGED_FUNCTION */\r
 327 {\r
 328         /* Stop and reset the SysTick. */\r
 329         *( portNVIC_SYSTICK_CTRL ) = 0UL;\r
 330         *( portNVIC_SYSTICK_CURRENT_VALUE ) = 0UL;\r
 331 \r
 332         /* Configure SysTick to interrupt at the requested rate. */\r
 333         *( portNVIC_SYSTICK_LOAD ) = ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;\r
 334         *( portNVIC_SYSTICK_CTRL ) = portNVIC_SYSTICK_CLK | portNVIC_SYSTICK_INT | portNVIC_SYSTICK_ENABLE;\r
 335 }\r
 336 /*-----------------------------------------------------------*/\r
 337 \r
 338 static void prvTaskExitError( void )\r
 339 {\r
 340 volatile uint32_t ulDummy = 0UL;\r
 341 \r
 342         /* A function that implements a task must not exit or attempt to return to\r
 343          * its caller as there is nothing to return to. If a task wants to exit it\r
 344          * should instead call vTaskDelete( NULL ). Artificially force an assert()\r
 345          * to be triggered if configASSERT() is defined, then stop here so\r
 346          * application writers can catch the error. */\r
 347         configASSERT( ulCriticalNesting == ~0UL );\r
 348         portDISABLE_INTERRUPTS();\r
 349 \r
 350         while( ulDummy == 0 )\r
 351         {\r
 352                 /* This file calls prvTaskExitError() after the scheduler has been\r
 353                  * started to remove a compiler warning about the function being\r
 354                  * defined but never called.  ulDummy is used purely to quieten other\r
 355                  * warnings about code appearing after this function is called - making\r
 356                  * ulDummy volatile makes the compiler think the function could return\r
 357                  * and therefore not output an 'unreachable code' warning for code that\r
 358                  * appears after it. */\r
 359         }\r
 360 }\r
 361 /*-----------------------------------------------------------*/\r
 362 \r
 363 #if( configENABLE_MPU == 1 )\r
 364         static void prvSetupMPU( void ) /* PRIVILEGED_FUNCTION */\r
 365         {\r
 366         #if defined( __ARMCC_VERSION )\r
 367                 /* Declaration when these variable are defined in code instead of being\r
 368                  * exported from linker scripts. */\r
 369                 extern uint32_t * __privileged_functions_start__;\r
 370                 extern uint32_t * __privileged_functions_end__;\r
 371                 extern uint32_t * __syscalls_flash_start__;\r
 372                 extern uint32_t * __syscalls_flash_end__;\r
 373                 extern uint32_t * __unprivileged_flash_start__;\r
 374                 extern uint32_t * __unprivileged_flash_end__;\r
 375                 extern uint32_t * __privileged_sram_start__;\r
 376                 extern uint32_t * __privileged_sram_end__;\r
 377         #else\r
 378                 /* Declaration when these variable are exported from linker scripts. */\r
 379                 extern uint32_t __privileged_functions_start__[];\r
 380                 extern uint32_t __privileged_functions_end__[];\r
 381                 extern uint32_t __syscalls_flash_start__[];\r
 382                 extern uint32_t __syscalls_flash_end__[];\r
 383                 extern uint32_t __unprivileged_flash_start__[];\r
 384                 extern uint32_t __unprivileged_flash_end__[];\r
 385                 extern uint32_t __privileged_sram_start__[];\r
 386                 extern uint32_t __privileged_sram_end__[];\r
 387         #endif /* defined( __ARMCC_VERSION ) */\r
 388 \r
 389                 /* Check that the MPU is present. */\r
 390                 if( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE )\r
 391                 {\r
 392                         /* MAIR0 - Index 0. */\r
 393                         portMPU_MAIR0_REG |= ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );\r
 394                         /* MAIR0 - Index 1. */\r
 395                         portMPU_MAIR0_REG |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK );\r
 396 \r
 397                         /* Setup privileged flash as Read Only so that privileged tasks can\r
 398                          * read it but not modify. */\r
 399                         portMPU_RNR_REG = portPRIVILEGED_FLASH_REGION;\r
 400                         portMPU_RBAR_REG =      ( ( ( uint32_t ) __privileged_functions_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |\r
 401                                                                 ( portMPU_REGION_NON_SHAREABLE ) |\r
 402                                                                 ( portMPU_REGION_PRIVILEGED_READ_ONLY );\r
 403                         portMPU_RLAR_REG =      ( ( ( uint32_t ) __privileged_functions_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |\r
 404                                                                 ( portMPU_RLAR_ATTR_INDEX0 ) |\r
 405                                                                 ( portMPU_RLAR_REGION_ENABLE );\r
 406 \r
 407                         /* Setup unprivileged flash as Read Only by both privileged and\r
 408                          * unprivileged tasks. All tasks can read it but no-one can modify. */\r
 409                         portMPU_RNR_REG = portUNPRIVILEGED_FLASH_REGION;\r
 410                         portMPU_RBAR_REG =      ( ( ( uint32_t ) __unprivileged_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |\r
 411                                                                 ( portMPU_REGION_NON_SHAREABLE ) |\r
 412                                                                 ( portMPU_REGION_READ_ONLY );\r
 413                         portMPU_RLAR_REG =      ( ( ( uint32_t ) __unprivileged_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |\r
 414                                                                 ( portMPU_RLAR_ATTR_INDEX0 ) |\r
 415                                                                 ( portMPU_RLAR_REGION_ENABLE );\r
 416 \r
 417                         /* Setup unprivileged syscalls flash as Read Only by both privileged\r
 418                          * and unprivileged tasks. All tasks can read it but no-one can modify. */\r
 419                         portMPU_RNR_REG = portUNPRIVILEGED_SYSCALLS_REGION;\r
 420                         portMPU_RBAR_REG =      ( ( ( uint32_t ) __syscalls_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |\r
 421                                                                 ( portMPU_REGION_NON_SHAREABLE ) |\r
 422                                                                 ( portMPU_REGION_READ_ONLY );\r
 423                         portMPU_RLAR_REG =      ( ( ( uint32_t ) __syscalls_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |\r
 424                                                                 ( portMPU_RLAR_ATTR_INDEX0 ) |\r
 425                                                                 ( portMPU_RLAR_REGION_ENABLE );\r
 426 \r
 427                         /* Setup RAM containing kernel data for privileged access only. */\r
 428                         portMPU_RNR_REG = portPRIVILEGED_RAM_REGION;\r
 429                         portMPU_RBAR_REG =      ( ( ( uint32_t ) __privileged_sram_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |\r
 430                                                                 ( portMPU_REGION_NON_SHAREABLE ) |\r
 431                                                                 ( portMPU_REGION_PRIVILEGED_READ_WRITE ) |\r
 432                                                                 ( portMPU_REGION_EXECUTE_NEVER );\r
 433                         portMPU_RLAR_REG =      ( ( ( uint32_t ) __privileged_sram_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |\r
 434                                                                 ( portMPU_RLAR_ATTR_INDEX0 ) |\r
 435                                                                 ( portMPU_RLAR_REGION_ENABLE );\r
 436 \r
 437                         /* Enable mem fault. */\r
 438                         portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_MEM_FAULT_ENABLE;\r
 439 \r
 440                         /* Enable MPU with privileged background access i.e. unmapped\r
 441                          * regions have privileged access. */\r
 442                         portMPU_CTRL_REG |= ( portMPU_PRIV_BACKGROUND_ENABLE | portMPU_ENABLE );\r
 443                 }\r
 444         }\r
 445 #endif /* configENABLE_MPU */\r
 446 /*-----------------------------------------------------------*/\r
 447 \r
 448 #if( configENABLE_FPU == 1 )\r
 449         static void prvSetupFPU( void ) /* PRIVILEGED_FUNCTION */\r
 450         {\r
 451                 #if( configENABLE_TRUSTZONE == 1 )\r
 452                 {\r
 453                         /* Enable non-secure access to the FPU. */\r
 454                         SecureInit_EnableNSFPUAccess();\r
 455                 }\r
 456                 #endif /* configENABLE_TRUSTZONE */\r
 457 \r
 458                 /* CP10 = 11 ==> Full access to FPU i.e. both privileged and\r
 459                  * unprivileged code should be able to access FPU. CP11 should be\r
 460                  * programmed to the same value as CP10. */\r
 461                 *( portCPACR ) |=       (       ( portCPACR_CP10_VALUE << portCPACR_CP10_POS ) |\r
 462                                                                 ( portCPACR_CP11_VALUE << portCPACR_CP11_POS )\r
 463                                                         );\r
 464 \r
 465                 /* ASPEN = 1 ==> Hardware should automatically preserve floating point\r
 466                  * context on exception entry and restore on exception return.\r
 467                  * LSPEN = 1 ==> Enable lazy context save of FP state. */\r
 468                 *( portFPCCR ) |= ( portFPCCR_ASPEN_MASK | portFPCCR_LSPEN_MASK );\r
 469         }\r
 470 #endif /* configENABLE_FPU */\r
 471 /*-----------------------------------------------------------*/\r
 472 \r
 473 void vPortYield( void ) /* PRIVILEGED_FUNCTION */\r
 474 {\r
 475         /* Set a PendSV to request a context switch. */\r
 476         *( portNVIC_INT_CTRL ) = portNVIC_PENDSVSET;\r
 477 \r
 478         /* Barriers are normally not required but do ensure the code is\r
 479          * completely within the specified behaviour for the architecture. */\r
 480         __asm volatile( "dsb" ::: "memory" );\r
 481         __asm volatile( "isb" );\r
 482 }\r
 483 /*-----------------------------------------------------------*/\r
 484 \r
 485 void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */\r
 486 {\r
 487         portDISABLE_INTERRUPTS();\r
 488         ulCriticalNesting++;\r
 489 \r
 490         /* Barriers are normally not required but do ensure the code is\r
 491          * completely within the specified behaviour for the architecture. */\r
 492         __asm volatile( "dsb" ::: "memory" );\r
 493         __asm volatile( "isb" );\r
 494 }\r
 495 /*-----------------------------------------------------------*/\r
 496 \r
 497 void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */\r
 498 {\r
 499         configASSERT( ulCriticalNesting );\r
 500         ulCriticalNesting--;\r
 501 \r
 502         if( ulCriticalNesting == 0 )\r
 503         {\r
 504                 portENABLE_INTERRUPTS();\r
 505         }\r
 506 }\r
 507 /*-----------------------------------------------------------*/\r
 508 \r
 509 void SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */\r
 510 {\r
 511 uint32_t ulPreviousMask;\r
 512 \r
 513         ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR();\r
 514         {\r
 515                 /* Increment the RTOS tick. */\r
 516                 if( xTaskIncrementTick() != pdFALSE )\r
 517                 {\r
 518                         /* Pend a context switch. */\r
 519                         *( portNVIC_INT_CTRL ) = portNVIC_PENDSVSET;\r
 520                 }\r
 521         }\r
 522         portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask );\r
 523 }\r
 524 /*-----------------------------------------------------------*/\r
 525 \r
 526 void vPortSVCHandler_C( uint32_t *pulCallerStackAddress ) /* PRIVILEGED_FUNCTION portDONT_DISCARD */\r
 527 {\r
 528 #if( configENABLE_MPU == 1 )\r
 529         #if defined( __ARMCC_VERSION )\r
 530                 /* Declaration when these variable are defined in code instead of being\r
 531                  * exported from linker scripts. */\r
 532                 extern uint32_t * __syscalls_flash_start__;\r
 533                 extern uint32_t * __syscalls_flash_end__;\r
 534         #else\r
 535                 /* Declaration when these variable are exported from linker scripts. */\r
 536                 extern uint32_t __syscalls_flash_start__[];\r
 537                 extern uint32_t __syscalls_flash_end__[];\r
 538         #endif /* defined( __ARMCC_VERSION ) */\r
 539 #endif /* configENABLE_MPU */\r
 540 \r
 541 uint32_t ulPC;\r
 542 \r
 543 #if( configENABLE_TRUSTZONE == 1 )\r
 544         uint32_t ulR0;\r
 545         #if( configENABLE_MPU == 1 )\r
 546                 uint32_t ulControl, ulIsTaskPrivileged;\r
 547         #endif /* configENABLE_MPU */\r
 548 #endif /* configENABLE_TRUSTZONE */\r
 549 uint8_t ucSVCNumber;\r
 550 \r
 551         /* Register are stored on the stack in the following order - R0, R1, R2, R3,\r
 552          * R12, LR, PC, xPSR. */\r
 553         ulPC = pulCallerStackAddress[ 6 ];\r
 554         ucSVCNumber = ( ( uint8_t *) ulPC )[ -2 ];\r
 555 \r
 556         switch( ucSVCNumber )\r
 557         {\r
 558                 #if( configENABLE_TRUSTZONE == 1 )\r
 559                         case portSVC_ALLOCATE_SECURE_CONTEXT:\r
 560                         {\r
 561                                 /* R0 contains the stack size passed as parameter to the\r
 562                                  * vPortAllocateSecureContext function. */\r
 563                                 ulR0 = pulCallerStackAddress[ 0 ];\r
 564 \r
 565                                 #if( configENABLE_MPU == 1 )\r
 566                                 {\r
 567                                         /* Read the CONTROL register value. */\r
 568                                         __asm volatile ( "mrs %0, control"  : "=r" ( ulControl ) );\r
 569 \r
 570                                         /* The task that raised the SVC is privileged if Bit[0]\r
 571                                          * in the CONTROL register is 0. */\r
 572                                         ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 );\r
 573 \r
 574                                         /* Allocate and load a context for the secure task. */\r
 575                                         xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged );\r
 576                                 }\r
 577                                 #else\r
 578                                 {\r
 579                                         /* Allocate and load a context for the secure task. */\r
 580                                         xSecureContext = SecureContext_AllocateContext( ulR0 );\r
 581                                 }\r
 582                                 #endif /* configENABLE_MPU */\r
 583 \r
 584                                 configASSERT( xSecureContext != NULL );\r
 585                                 SecureContext_LoadContext( xSecureContext );\r
 586                         }\r
 587                         break;\r
 588 \r
 589                         case portSVC_FREE_SECURE_CONTEXT:\r
 590                         {\r
 591                                 /* R0 contains the secure context handle to be freed. */\r
 592                                 ulR0 = pulCallerStackAddress[ 0 ];\r
 593 \r
 594                                 /* Free the secure context. */\r
 595                                 SecureContext_FreeContext( ( SecureContextHandle_t ) ulR0 );\r
 596                         }\r
 597                         break;\r
 598                 #endif /* configENABLE_TRUSTZONE */\r
 599 \r
 600                 case portSVC_START_SCHEDULER:\r
 601                 {\r
 602                         #if( configENABLE_TRUSTZONE == 1 )\r
 603                         {\r
 604                                 /* De-prioritize the non-secure exceptions so that the\r
 605                                  * non-secure pendSV runs at the lowest priority. */\r
 606                                 SecureInit_DePrioritizeNSExceptions();\r
 607 \r
 608                                 /* Initialize the secure context management system. */\r
 609                                 SecureContext_Init();\r
 610                         }\r
 611                         #endif /* configENABLE_TRUSTZONE */\r
 612 \r
 613                         #if( configENABLE_FPU == 1 )\r
 614                         {\r
 615                                 /* Setup the Floating Point Unit (FPU). */\r
 616                                 prvSetupFPU();\r
 617                         }\r
 618                         #endif /* configENABLE_FPU */\r
 619 \r
 620                         /* Setup the context of the first task so that the first task starts\r
 621                          * executing. */\r
 622                         vRestoreContextOfFirstTask();\r
 623                 }\r
 624                 break;\r
 625 \r
 626                 #if( configENABLE_MPU == 1 )\r
 627                         case portSVC_RAISE_PRIVILEGE:\r
 628                         {\r
 629                                 /* Only raise the privilege, if the svc was raised from any of\r
 630                                  * the system calls. */\r
 631                                 if( ulPC >= ( uint32_t ) __syscalls_flash_start__ &&\r
 632                                         ulPC <= ( uint32_t ) __syscalls_flash_end__ )\r
 633                                 {\r
 634                                         vRaisePrivilege();\r
 635                                 }\r
 636                         }\r
 637                         break;\r
 638                 #endif /* configENABLE_MPU */\r
 639 \r
 640                 default:\r
 641                 {\r
 642                         /* Incorrect SVC call. */\r
 643                         configASSERT( pdFALSE );\r
 644                 }\r
 645         }\r
 646 }\r
 647 /*-----------------------------------------------------------*/\r
 648 \r
 649 #if( configENABLE_MPU == 1 )\r
 650         StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, StackType_t *pxEndOfStack, TaskFunction_t pxCode, void *pvParameters, BaseType_t xRunPrivileged ) /* PRIVILEGED_FUNCTION */\r
 651 #else\r
 652         StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, StackType_t *pxEndOfStack, TaskFunction_t pxCode, void *pvParameters ) /* PRIVILEGED_FUNCTION */\r
 653 #endif /* configENABLE_MPU */\r
 654 {\r
 655         /* Simulate the stack frame as it would be created by a context switch\r
 656          * interrupt. */\r
 657         #if( portPRELOAD_REGISTERS == 0 )\r
 658         {\r
 659                 pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */\r
 660                 *pxTopOfStack = portINITIAL_XPSR;                                                       /* xPSR */\r
 661                 pxTopOfStack--;\r
 662                 *pxTopOfStack = ( StackType_t ) pxCode;                                         /* PC */\r
 663                 pxTopOfStack--;\r
 664                 *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS;        /* LR */\r
 665                 pxTopOfStack -= 5;                                                                                      /* R12, R3, R2 and R1. */\r
 666                 *pxTopOfStack = ( StackType_t ) pvParameters;                           /* R0 */\r
 667                 pxTopOfStack -= 9;                                                                                      /* R11..R4, EXC_RETURN. */\r
 668                 *pxTopOfStack = portINITIAL_EXC_RETURN;\r
 669 \r
 670                 #if( configENABLE_MPU == 1 )\r
 671                 {\r
 672                         pxTopOfStack--;\r
 673                         if( xRunPrivileged == pdTRUE )\r
 674                         {\r
 675                                 *pxTopOfStack = portINITIAL_CONTROL_PRIVILEGED;         /* Slot used to hold this task's CONTROL value. */\r
 676                         }\r
 677                         else\r
 678                         {\r
 679                                 *pxTopOfStack = portINITIAL_CONTROL_UNPRIVILEGED;       /* Slot used to hold this task's CONTROL value. */\r
 680                         }\r
 681                 }\r
 682                 #endif /* configENABLE_MPU */\r
 683 \r
 684                 pxTopOfStack--;\r
 685                 *pxTopOfStack = ( StackType_t ) pxEndOfStack;   /* Slot used to hold this task's PSPLIM value. */\r
 686 \r
 687                 #if( configENABLE_TRUSTZONE == 1 )\r
 688                 {\r
 689                         pxTopOfStack--;\r
 690                         *pxTopOfStack = portNO_SECURE_CONTEXT;          /* Slot used to hold this task's xSecureContext value. */\r
 691                 }\r
 692                 #endif /* configENABLE_TRUSTZONE */\r
 693         }\r
 694         #else /* portPRELOAD_REGISTERS */\r
 695         {\r
 696                 pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */\r
 697                 *pxTopOfStack = portINITIAL_XPSR;                                                       /* xPSR */\r
 698                 pxTopOfStack--;\r
 699                 *pxTopOfStack = ( StackType_t ) pxCode;                                         /* PC */\r
 700                 pxTopOfStack--;\r
 701                 *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS;        /* LR */\r
 702                 pxTopOfStack--;\r
 703                 *pxTopOfStack = ( StackType_t ) 0x12121212UL;                           /* R12 */\r
 704                 pxTopOfStack--;\r
 705                 *pxTopOfStack = ( StackType_t ) 0x03030303UL;                           /* R3 */\r
 706                 pxTopOfStack--;\r
 707                 *pxTopOfStack = ( StackType_t ) 0x02020202UL;                           /* R2 */\r
 708                 pxTopOfStack--;\r
 709                 *pxTopOfStack = ( StackType_t ) 0x01010101UL;                           /* R1 */\r
 710                 pxTopOfStack--;\r
 711                 *pxTopOfStack = ( StackType_t ) pvParameters;                           /* R0 */\r
 712                 pxTopOfStack--;\r
 713                 *pxTopOfStack = ( StackType_t ) 0x11111111UL;                           /* R11 */\r
 714                 pxTopOfStack--;\r
 715                 *pxTopOfStack = ( StackType_t ) 0x10101010UL;                           /* R10 */\r
 716                 pxTopOfStack--;\r
 717                 *pxTopOfStack = ( StackType_t ) 0x09090909UL;                           /* R09 */\r
 718                 pxTopOfStack--;\r
 719                 *pxTopOfStack = ( StackType_t ) 0x08080808UL;                           /* R08 */\r
 720                 pxTopOfStack--;\r
 721                 *pxTopOfStack = ( StackType_t ) 0x07070707UL;                           /* R07 */\r
 722                 pxTopOfStack--;\r
 723                 *pxTopOfStack = ( StackType_t ) 0x06060606UL;                           /* R06 */\r
 724                 pxTopOfStack--;\r
 725                 *pxTopOfStack = ( StackType_t ) 0x05050505UL;                           /* R05 */\r
 726                 pxTopOfStack--;\r
 727                 *pxTopOfStack = ( StackType_t ) 0x04040404UL;                           /* R04 */\r
 728                 pxTopOfStack--;\r
 729                 *pxTopOfStack = portINITIAL_EXC_RETURN;                                         /* EXC_RETURN */\r
 730 \r
 731                 #if( configENABLE_MPU == 1 )\r
 732                 {\r
 733                         pxTopOfStack--;\r
 734                         if( xRunPrivileged == pdTRUE )\r
 735                         {\r
 736                                 *pxTopOfStack = portINITIAL_CONTROL_PRIVILEGED;         /* Slot used to hold this task's CONTROL value. */\r
 737                         }\r
 738                         else\r
 739                         {\r
 740                                 *pxTopOfStack = portINITIAL_CONTROL_UNPRIVILEGED;       /* Slot used to hold this task's CONTROL value. */\r
 741                         }\r
 742                 }\r
 743                 #endif /* configENABLE_MPU */\r
 744 \r
 745                 pxTopOfStack--;\r
 746                 *pxTopOfStack = ( StackType_t ) pxEndOfStack;   /* Slot used to hold this task's PSPLIM value. */\r
 747 \r
 748                 #if( configENABLE_TRUSTZONE == 1 )\r
 749                 {\r
 750                         pxTopOfStack--;\r
 751                         *pxTopOfStack = portNO_SECURE_CONTEXT;          /* Slot used to hold this task's xSecureContext value. */\r
 752                 }\r
 753                 #endif /* configENABLE_TRUSTZONE */\r
 754         }\r
 755         #endif /* portPRELOAD_REGISTERS */\r
 756 \r
 757         return pxTopOfStack;\r
 758 }\r
 759 /*-----------------------------------------------------------*/\r
 760 \r
 761 BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */\r
 762 {\r
 763         /* Make PendSV, CallSV and SysTick the same priority as the kernel. */\r
 764         *( portNVIC_SYSPRI2 ) |= portNVIC_PENDSV_PRI;\r
 765         *( portNVIC_SYSPRI2 ) |= portNVIC_SYSTICK_PRI;\r
 766 \r
 767         #if( configENABLE_MPU == 1 )\r
 768         {\r
 769                 /* Setup the Memory Protection Unit (MPU). */\r
 770                 prvSetupMPU();\r
 771         }\r
 772         #endif /* configENABLE_MPU */\r
 773 \r
 774         /* Start the timer that generates the tick ISR. Interrupts are disabled\r
 775          * here already. */\r
 776         prvSetupTimerInterrupt();\r
 777 \r
 778         /* Initialize the critical nesting count ready for the first task. */\r
 779         ulCriticalNesting = 0;\r
 780 \r
 781         /* Start the first task. */\r
 782         vStartFirstTask();\r
 783 \r
 784         /* Should never get here as the tasks will now be executing. Call the task\r
 785          * exit error function to prevent compiler warnings about a static function\r
 786          * not being called in the case that the application writer overrides this\r
 787          * functionality by defining configTASK_RETURN_ADDRESS. Call\r
 788          * vTaskSwitchContext() so link time optimization does not remove the\r
 789          * symbol. */\r
 790         vTaskSwitchContext();\r
 791         prvTaskExitError();\r
 792 \r
 793         /* Should not get here. */\r
 794         return 0;\r
 795 }\r
 796 /*-----------------------------------------------------------*/\r
 797 \r
 798 void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */\r
 799 {\r
 800         /* Not implemented in ports where there is nothing to return to.\r
 801          * Artificially force an assert. */\r
 802         configASSERT( ulCriticalNesting == 1000UL );\r
 803 }\r
 804 /*-----------------------------------------------------------*/\r
 805 \r
 806 #if( configENABLE_MPU == 1 )\r
 807         void vPortStoreTaskMPUSettings( xMPU_SETTINGS *xMPUSettings, const struct xMEMORY_REGION * const xRegions, StackType_t *pxBottomOfStack, uint32_t ulStackDepth )\r
 808         {\r
 809         uint32_t ulRegionStartAddress, ulRegionEndAddress, ulRegionNumber;\r
 810         int32_t lIndex = 0;\r
 811 \r
 812                 /* Setup MAIR0. */\r
 813                 xMPUSettings->ulMAIR0 = ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );\r
 814                 xMPUSettings->ulMAIR0 |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK );\r
 815 \r
 816                 /* This function is called automatically when the task is created - in\r
 817                  * which case the stack region parameters will be valid.  At all other\r
 818                  * times the stack parameters will not be valid and it is assumed that\r
 819                  * the stack region has already been configured. */\r
 820                 if( ulStackDepth > 0 )\r
 821                 {\r
 822                         /* Define the region that allows access to the stack. */\r
 823                         ulRegionStartAddress = ( ( uint32_t ) pxBottomOfStack ) & portMPU_RBAR_ADDRESS_MASK;\r
 824                         ulRegionEndAddress = ( uint32_t ) pxBottomOfStack + ( ulStackDepth * ( uint32_t ) sizeof( StackType_t ) ) - 1;\r
 825                         ulRegionEndAddress  &= portMPU_RLAR_ADDRESS_MASK;\r
 826 \r
 827                         xMPUSettings->xRegionsSettings[ 0 ].ulRBAR =    ( ulRegionStartAddress ) |\r
 828                                                                                                                         ( portMPU_REGION_NON_SHAREABLE ) |\r
 829                                                                                                                         ( portMPU_REGION_READ_WRITE ) |\r
 830                                                                                                                         ( portMPU_REGION_EXECUTE_NEVER );\r
 831 \r
 832                         xMPUSettings->xRegionsSettings[ 0 ].ulRLAR =    ( ulRegionEndAddress ) |\r
 833                                                                                                                         ( portMPU_RLAR_ATTR_INDEX0 ) |\r
 834                                                                                                                         ( portMPU_RLAR_REGION_ENABLE );\r
 835                 }\r
 836 \r
 837                 /* User supplied configurable regions. */\r
 838                 for( ulRegionNumber = 1; ulRegionNumber <= portNUM_CONFIGURABLE_REGIONS; ulRegionNumber++ )\r
 839                 {\r
 840                         /* If xRegions is NULL i.e. the task has not specified any MPU\r
 841                          * region, the else part ensures that all the configurable MPU\r
 842                          * regions are invalidated. */\r
 843                         if( ( xRegions != NULL ) && ( xRegions[ lIndex ].ulLengthInBytes > 0UL ) )\r
 844                         {\r
 845                                 /* Translate the generic region definition contained in xRegions\r
 846                                  * into the ARMv8 specific MPU settings that are then stored in\r
 847                                  * xMPUSettings. */\r
 848                                 ulRegionStartAddress = ( ( uint32_t ) xRegions[ lIndex ].pvBaseAddress ) & portMPU_RBAR_ADDRESS_MASK;\r
 849                                 ulRegionEndAddress = ( uint32_t ) xRegions[ lIndex ].pvBaseAddress + xRegions[ lIndex ].ulLengthInBytes - 1;\r
 850                                 ulRegionEndAddress  &= portMPU_RLAR_ADDRESS_MASK;\r
 851 \r
 852                                 /* Start address. */\r
 853                                 xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR =       ( ulRegionStartAddress ) |\r
 854                                                                                                                                                         ( portMPU_REGION_NON_SHAREABLE );\r
 855 \r
 856                                 /* RO/RW. */\r
 857                                 if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_READ_ONLY ) != 0 )\r
 858                                 {\r
 859                                         xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_ONLY );\r
 860                                 }\r
 861                                 else\r
 862                                 {\r
 863                                         xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_WRITE );\r
 864                                 }\r
 865 \r
 866                                 /* XN. */\r
 867                                 if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_EXECUTE_NEVER ) != 0 )\r
 868                                 {\r
 869                                         xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_EXECUTE_NEVER );\r
 870                                 }\r
 871 \r
 872                                 /* End Address. */\r
 873                                 xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR =       ( ulRegionEndAddress ) |\r
 874                                                                                                                                                         ( portMPU_RLAR_REGION_ENABLE );\r
 875 \r
 876                                 /* Normal memory/ Device memory. */\r
 877                                 if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_DEVICE_MEMORY ) != 0 )\r
 878                                 {\r
 879                                         /* Attr1 in MAIR0 is configured as device memory. */\r
 880                                         xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX1;\r
 881                                 }\r
 882                                 else\r
 883                                 {\r
 884                                         /* Attr1 in MAIR0 is configured as normal memory. */\r
 885                                         xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX0;\r
 886                                 }\r
 887                         }\r
 888                         else\r
 889                         {\r
 890                                 /* Invalidate the region. */\r
 891                                 xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR = 0UL;\r
 892                                 xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = 0UL;\r
 893                         }\r
 894 \r
 895                         lIndex++;\r
 896                 }\r
 897         }\r
 898 #endif /* configENABLE_MPU */\r
 899 /*-----------------------------------------------------------*/\r