git.sur5r.net Git - freertos/blob - FreeRTOS/Source/portable/IAR/ARM_CM33_NTZ/non_secure/portasm.s

   1 /*\r
   2  * FreeRTOS Kernel V10.2.1\r
   3  * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.\r
   4  *\r
   5  * Permission is hereby granted, free of charge, to any person obtaining a copy of\r
   6  * this software and associated documentation files (the "Software"), to deal in\r
   7  * the Software without restriction, including without limitation the rights to\r
   8  * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of\r
   9  * the Software, and to permit persons to whom the Software is furnished to do so,\r
  10  * subject to the following conditions:\r
  11  *\r
  12  * The above copyright notice and this permission notice shall be included in all\r
  13  * copies or substantial portions of the Software.\r
  14  *\r
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR\r
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS\r
  17  * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR\r
  18  * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER\r
  19  * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
  20  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.\r
  21  *\r
  22  * http://www.FreeRTOS.org\r
  23  * http://aws.amazon.com/freertos\r
  24  *\r
  25  * 1 tab == 4 spaces!\r
  26  */\r
  27 \r
  28         EXTERN pxCurrentTCB\r
  29         EXTERN vTaskSwitchContext\r
  30         EXTERN vPortSVCHandler_C\r
  31 \r
  32         PUBLIC xIsPrivileged\r
  33         PUBLIC vResetPrivilege\r
  34         PUBLIC vRestoreContextOfFirstTask\r
  35         PUBLIC vRaisePrivilege\r
  36         PUBLIC vStartFirstTask\r
  37         PUBLIC ulSetInterruptMaskFromISR\r
  38         PUBLIC vClearInterruptMaskFromISR\r
  39         PUBLIC PendSV_Handler\r
  40         PUBLIC SVC_Handler\r
  41 /*-----------------------------------------------------------*/\r
  42 \r
  43 /*---------------- Unprivileged Functions -------------------*/\r
  44 \r
  45 /*-----------------------------------------------------------*/\r
  46 \r
  47         SECTION .text:CODE:NOROOT(2)\r
  48         THUMB\r
  49 /*-----------------------------------------------------------*/\r
  50 \r
  51 xIsPrivileged:\r
  52         mrs r0, control                                                 /* r0 = CONTROL. */\r
  53         tst r0, #1                                                              /* Perform r0 & 1 (bitwise AND) and update the conditions flag. */\r
  54         ite ne\r
  55         movne r0, #0                                                    /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */\r
  56         moveq r0, #1                                                    /* CONTROL[0]==0. Return true to indicate that the processor is not privileged. */\r
  57         bx lr                                                                   /* Return. */\r
  58 /*-----------------------------------------------------------*/\r
  59 \r
  60 vResetPrivilege:\r
  61         mrs r0, control                                                 /* r0 = CONTROL. */\r
  62         orr r0, r0, #1                                                  /* r0 = r0 | 1. */\r
  63         msr control, r0                                                 /* CONTROL = r0. */\r
  64         bx lr                                                                   /* Return to the caller. */\r
  65 /*-----------------------------------------------------------*/\r
  66 \r
  67 /*----------------- Privileged Functions --------------------*/\r
  68 \r
  69 /*-----------------------------------------------------------*/\r
  70 \r
  71         SECTION privileged_functions:CODE:NOROOT(2)\r
  72         THUMB\r
  73 /*-----------------------------------------------------------*/\r
  74 \r
  75 vRestoreContextOfFirstTask:\r
  76         ldr  r2, =pxCurrentTCB                                  /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\r
  77         ldr  r1, [r2]                                                   /* Read pxCurrentTCB. */\r
  78         ldr  r0, [r1]                                                   /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */\r
  79 \r
  80 #if ( configENABLE_MPU == 1 )\r
  81         dmb                                                                             /* Complete outstanding transfers before disabling MPU. */\r
  82         ldr r2, =0xe000ed94                                             /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */\r
  83         ldr r4, [r2]                                                    /* Read the value of MPU_CTRL. */\r
  84         bic r4, r4, #1                                                  /* r4 = r4 & ~1 i.e. Clear the bit 0 in r4. */\r
  85         str r4, [r2]                                                    /* Disable MPU. */\r
  86 \r
  87         adds r1, #4                                                             /* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */\r
  88         ldr r3, [r1]                                                    /* r3 = *r1 i.e. r3 = MAIR0. */\r
  89         ldr r2, =0xe000edc0                                             /* r2 = 0xe000edc0 [Location of MAIR0]. */\r
  90         str r3, [r2]                                                    /* Program MAIR0. */\r
  91         ldr r2, =0xe000ed98                                             /* r2 = 0xe000ed98 [Location of RNR]. */\r
  92         movs r3, #4                                                             /* r3 = 4. */\r
  93         str r3, [r2]                                                    /* Program RNR = 4. */\r
  94         adds r1, #4                                                             /* r1 = r1 + 4. r1 now points to first RBAR in TCB. */\r
  95         ldr r2, =0xe000ed9c                                             /* r2 = 0xe000ed9c [Location of RBAR]. */\r
  96         ldmia r1!, {r4-r11}                                             /* Read 4 sets of RBAR/RLAR registers from TCB. */\r
  97         stmia r2!, {r4-r11}                                             /* Write 4 set of RBAR/RLAR registers using alias registers. */\r
  98 \r
  99         ldr r2, =0xe000ed94                                             /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */\r
 100         ldr r4, [r2]                                                    /* Read the value of MPU_CTRL. */\r
 101         orr r4, r4, #1                                                  /* r4 = r4 | 1 i.e. Set the bit 0 in r4. */\r
 102         str r4, [r2]                                                    /* Enable MPU. */\r
 103         dsb                                                                             /* Force memory writes before continuing. */\r
 104 #endif /* configENABLE_MPU */\r
 105 \r
 106 #if ( configENABLE_MPU == 1 )\r
 107         ldm  r0!, {r1-r3}                                               /* Read from stack - r1 = PSPLIM, r2 = CONTROL and r3 = EXC_RETURN. */\r
 108         msr  psplim, r1                                                 /* Set this task's PSPLIM value. */\r
 109         msr  control, r2                                                /* Set this task's CONTROL value. */\r
 110         adds r0, #32                                                    /* Discard everything up to r0. */\r
 111         msr  psp, r0                                                    /* This is now the new top of stack to use in the task. */\r
 112         isb\r
 113         bx   r3                                                                 /* Finally, branch to EXC_RETURN. */\r
 114 #else /* configENABLE_MPU */\r
 115         ldm  r0!, {r1-r2}                                               /* Read from stack - r1 = PSPLIM and r2 = EXC_RETURN. */\r
 116         msr  psplim, r1                                                 /* Set this task's PSPLIM value. */\r
 117         movs r1, #2                                                             /* r1 = 2. */\r
 118         msr  CONTROL, r1                                                /* Switch to use PSP in the thread mode. */\r
 119         adds r0, #32                                                    /* Discard everything up to r0. */\r
 120         msr  psp, r0                                                    /* This is now the new top of stack to use in the task. */\r
 121         isb\r
 122         bx   r2                                                                 /* Finally, branch to EXC_RETURN. */\r
 123 #endif /* configENABLE_MPU */\r
 124 /*-----------------------------------------------------------*/\r
 125 \r
 126 vRaisePrivilege:\r
 127         mrs  r0, control                                                /* Read the CONTROL register. */\r
 128         bic r0, r0, #1                                                  /* Clear the bit 0. */\r
 129         msr  control, r0                                                /* Write back the new CONTROL value. */\r
 130         bx lr                                                                   /* Return to the caller. */\r
 131 /*-----------------------------------------------------------*/\r
 132 \r
 133 vStartFirstTask:\r
 134         ldr r0, =0xe000ed08                                             /* Use the NVIC offset register to locate the stack. */\r
 135         ldr r0, [r0]                                                    /* Read the VTOR register which gives the address of vector table. */\r
 136         ldr r0, [r0]                                                    /* The first entry in vector table is stack pointer. */\r
 137         msr msp, r0                                                             /* Set the MSP back to the start of the stack. */\r
 138         cpsie i                                                                 /* Globally enable interrupts. */\r
 139         cpsie f\r
 140         dsb\r
 141         isb\r
 142         svc 2                                                                   /* System call to start the first task. portSVC_START_SCHEDULER = 2. */\r
 143 /*-----------------------------------------------------------*/\r
 144 \r
 145 ulSetInterruptMaskFromISR:\r
 146         mrs r0, PRIMASK\r
 147         cpsid i\r
 148         bx lr\r
 149 /*-----------------------------------------------------------*/\r
 150 \r
 151 vClearInterruptMaskFromISR:\r
 152         msr PRIMASK, r0\r
 153         bx lr\r
 154 /*-----------------------------------------------------------*/\r
 155 \r
 156 PendSV_Handler:\r
 157         mrs r0, psp                                                             /* Read PSP in r0. */\r
 158 #if ( configENABLE_FPU == 1 )\r
 159         tst lr, #0x10                                                   /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the FPU is in use. */\r
 160         it eq\r
 161         vstmdbeq r0!, {s16-s31}                                 /* Store the FPU registers which are not saved automatically. */\r
 162 #endif /* configENABLE_FPU */\r
 163 #if ( configENABLE_MPU == 1 )\r
 164         mrs r1, psplim                                                  /* r1 = PSPLIM. */\r
 165         mrs r2, control                                                 /* r2 = CONTROL. */\r
 166         mov r3, lr                                                              /* r3 = LR/EXC_RETURN. */\r
 167         stmdb r0!, {r1-r11}                                             /* Store on the stack - PSPLIM, CONTROL, LR and registers that are not automatically saved. */\r
 168 #else /* configENABLE_MPU */\r
 169         mrs r2, psplim                                                  /* r2 = PSPLIM. */\r
 170         mov r3, lr                                                              /* r3 = LR/EXC_RETURN. */\r
 171         stmdb r0!, {r2-r11}                                             /* Store on the stack - PSPLIM, LR and registers that are not automatically. */\r
 172 #endif /* configENABLE_MPU */\r
 173 \r
 174         ldr r2, =pxCurrentTCB                                   /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\r
 175         ldr r1, [r2]                                                    /* Read pxCurrentTCB. */\r
 176         str r0, [r1]                                                    /* Save the new top of stack in TCB. */\r
 177 \r
 178         cpsid i\r
 179         bl vTaskSwitchContext\r
 180         cpsie i\r
 181 \r
 182         ldr r2, =pxCurrentTCB                                   /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */\r
 183         ldr r1, [r2]                                                    /* Read pxCurrentTCB. */\r
 184         ldr r0, [r1]                                                    /* The first item in pxCurrentTCB is the task top of stack. r0 now points to the top of stack. */\r
 185 \r
 186 #if ( configENABLE_MPU == 1 )\r
 187         dmb                                                                             /* Complete outstanding transfers before disabling MPU. */\r
 188         ldr r2, =0xe000ed94                                             /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */\r
 189         ldr r4, [r2]                                                    /* Read the value of MPU_CTRL. */\r
 190         bic r4, r4, #1                                                  /* r4 = r4 & ~1 i.e. Clear the bit 0 in r4. */\r
 191         str r4, [r2]                                                    /* Disable MPU. */\r
 192 \r
 193         adds r1, #4                                                             /* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */\r
 194         ldr r3, [r1]                                                    /* r3 = *r1 i.e. r3 = MAIR0. */\r
 195         ldr r2, =0xe000edc0                                             /* r2 = 0xe000edc0 [Location of MAIR0]. */\r
 196         str r3, [r2]                                                    /* Program MAIR0. */\r
 197         ldr r2, =0xe000ed98                                             /* r2 = 0xe000ed98 [Location of RNR]. */\r
 198         movs r3, #4                                                             /* r3 = 4. */\r
 199         str r3, [r2]                                                    /* Program RNR = 4. */\r
 200         adds r1, #4                                                             /* r1 = r1 + 4. r1 now points to first RBAR in TCB. */\r
 201         ldr r2, =0xe000ed9c                                             /* r2 = 0xe000ed9c [Location of RBAR]. */\r
 202         ldmia r1!, {r4-r11}                                             /* Read 4 sets of RBAR/RLAR registers from TCB. */\r
 203         stmia r2!, {r4-r11}                                             /* Write 4 set of RBAR/RLAR registers using alias registers. */\r
 204 \r
 205         ldr r2, =0xe000ed94                                             /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */\r
 206         ldr r4, [r2]                                                    /* Read the value of MPU_CTRL. */\r
 207         orr r4, r4, #1                                                  /* r4 = r4 | 1 i.e. Set the bit 0 in r4. */\r
 208         str r4, [r2]                                                    /* Enable MPU. */\r
 209         dsb                                                                             /* Force memory writes before continuing. */\r
 210 #endif /* configENABLE_MPU */\r
 211 \r
 212 #if ( configENABLE_MPU == 1 )\r
 213         ldmia r0!, {r1-r11}                                             /* Read from stack - r1 = PSPLIM, r2 = CONTROL, r3 = LR and r4-r11 restored. */\r
 214 #else /* configENABLE_MPU */\r
 215         ldmia r0!, {r2-r11}                                             /* Read from stack - r2 = PSPLIM, r3 = LR and r4-r11 restored. */\r
 216 #endif /* configENABLE_MPU */\r
 217 \r
 218 #if ( configENABLE_FPU == 1 )\r
 219         tst r3, #0x10                                                   /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the FPU is in use. */\r
 220         it eq\r
 221         vldmiaeq r0!, {s16-s31}                                 /* Restore the FPU registers which are not restored automatically. */\r
 222 #endif /* configENABLE_FPU */\r
 223 \r
 224  #if ( configENABLE_MPU == 1 )\r
 225         msr psplim, r1                                                  /* Restore the PSPLIM register value for the task. */\r
 226         msr control, r2                                                 /* Restore the CONTROL register value for the task. */\r
 227 #else /* configENABLE_MPU */\r
 228         msr psplim, r2                                                  /* Restore the PSPLIM register value for the task. */\r
 229 #endif /* configENABLE_MPU */\r
 230         msr psp, r0                                                             /* Remember the new top of stack for the task. */\r
 231         bx r3\r
 232 /*-----------------------------------------------------------*/\r
 233 \r
 234 SVC_Handler:\r
 235         tst lr, #4\r
 236         ite eq\r
 237         mrseq r0, msp\r
 238         mrsne r0, psp\r
 239         b vPortSVCHandler_C\r
 240 /*-----------------------------------------------------------*/\r
 241 \r
 242         END\r